JPH05218644A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH05218644A
JPH05218644A JP1810892A JP1810892A JPH05218644A JP H05218644 A JPH05218644 A JP H05218644A JP 1810892 A JP1810892 A JP 1810892A JP 1810892 A JP1810892 A JP 1810892A JP H05218644 A JPH05218644 A JP H05218644A
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
multilayer printed
plating
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1810892A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hyodo
清志 兵頭
Toyomitsu Amada
豊光 天田
Hitoshi Ogawa
小川  均
Koichi Ishida
浩一 石田
Makoto Ishihara
真 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1810892A priority Critical patent/JPH05218644A/en
Publication of JPH05218644A publication Critical patent/JPH05218644A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Chemically Coating (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To provide the manufacture of a multilayer printed wiring board which has an interlayer insulating film made of organic resin and a conductor layer excellent in adhesion. CONSTITUTION:In the manufacture of a multilayer printed wiring board, wherein organic resin is used as interlayer insulating films 14 and 24, it is so constituted as to precipitate electroless palladium platings 16 and 26 on infer layer insulating films 14 and 24 as the plating base films 16 and 26 of conductor layers when forming the conductor layer on each interlayer insulating film 14 and 24.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は一般的に多層プリント配
線板の製造方法に関し、特に誘電率の低いポリイミド樹
脂等を層間絶縁膜として使用する多層プリント配線板の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board using a polyimide resin having a low dielectric constant as an interlayer insulating film.

【0002】プリント配線板は、半導体の発展と共に今
後大幅な伸長が期待されており、電子機器、装置類の小
型化、高性能化及び多機能化の要求に伴い、それらに用
いられるプリント配線板にも高密度化、高集積化、微細
回路化が要求され、これらの要求に対応するプリント配
線板製造技術が必要となってきている。
Printed wiring boards are expected to grow significantly in the future with the development of semiconductors, and with the demand for miniaturization, high performance, and multi-functionalization of electronic equipment and devices, the printed wiring boards used for them are being demanded. In particular, higher densities, higher integration, and finer circuits are required, and printed wiring board manufacturing technology that meets these requirements is required.

【0003】具体的にプリント配線板を高密度化、高集
積化する方法としては、複数の配線層を積層し、各配線
層をスルーホール、ビアホールで接続する多層化の方向
と、外層回路を微細化し、表裏の接続に小径ビアホール
を用いる方法とがある。
Specifically, as a method of densifying and highly integrating a printed wiring board, a plurality of wiring layers are laminated and the wiring layers are connected by through holes and via holes. There is a method of miniaturizing and using a small-diameter via hole for front and back connection.

【0004】多層プリント配線板のうち誘電率の低いポ
リイミド樹脂等を層間絶縁膜として使用する多層プリン
ト配線板の製造方法においては、高速回路実装パッケー
ジの要求から、銅ポリイミド配線技術、特に導体層形成
技術や層間接続用ビアホールの形成技術が重要な課題と
なっている。
In a method of manufacturing a multilayer printed wiring board using a polyimide resin or the like having a low dielectric constant as an interlayer insulating film among the multilayer printed wiring boards, copper polyimide wiring technology, especially formation of a conductor layer is required in order to meet the demand for a high-speed circuit mounting package. Technology and technology for forming via holes for interlayer connection have become important issues.

【0005】[0005]

【従来の技術】ポリイミド樹脂等の有機系樹脂を層間絶
縁膜として用いる従来の多層プリント配線板の製造方法
においては、無電解めっき法、又は蒸着法、スパッタリ
ング法を用いて導体層のめっき下地膜を形成していた。
2. Description of the Related Art In a conventional method for manufacturing a multilayer printed wiring board using an organic resin such as a polyimide resin as an interlayer insulating film, an electroless plating method, a vapor deposition method or a sputtering method is used to form a plating base film for a conductor layer. Had formed.

【0006】無電解めっき法においては、セラミック基
板上に第1層目のポリイミド層を形成し、ポリイミド層
上にめっき下地膜としての無電解銅めっき膜を0.2〜
0.3μmの厚さで析出させる。次いで、無電解銅めっ
き膜上に電解銅めっき膜を一様に形成し、パターニング
をして不要部分の銅めっきを除去する。
In the electroless plating method, a first polyimide layer is formed on a ceramic substrate, and an electroless copper plating film as a plating base film is formed on the polyimide layer in an amount of 0.2 to 0.2.
Precipitate to a thickness of 0.3 μm. Next, an electrolytic copper-plated film is uniformly formed on the electroless copper-plated film, and patterned to remove unnecessary portions of the copper-plated film.

【0007】次いで、第2層目のポリイミド層を一様に
形成した後、パターニングをして銅めっき膜上の第2層
目のポリイミド層を除去する。さらに、第2層目の無電
解銅めっき膜を一様に析出させた後、第2層目の電解銅
めっき膜を形成することにより、第1層目の電解銅めっ
き膜と第2層目の電解銅めっき膜とをビアホール部分で
接続する。
Next, after forming the second polyimide layer uniformly, patterning is performed to remove the second polyimide layer on the copper plating film. Further, after the second-layer electroless copper-plated film is uniformly deposited, the second-layer electrolytic copper-plated film is formed, whereby the first-layer electrolytic copper-plated film and the second-layer electrolytic copper-plated film are formed. And the electrolytic copper-plated film are connected at the via hole portion.

【0008】無電解銅めっき法により製造された多層プ
リント配線板が図4(A)に示されている。2はセラミ
ック基板、3は第1層目のポリイミド層、4は第1層目
の電解銅めっき膜、5は第2層目のポリイミド層、6は
第2層目の電解銅めっき膜、7は層間接続用ビアホール
である。
A multilayer printed wiring board manufactured by the electroless copper plating method is shown in FIG. 2 is a ceramic substrate, 3 is a first-layer polyimide layer, 4 is a first-layer electrolytic copper plating film, 5 is a second-layer polyimide layer, 6 is a second-layer electrolytic copper-plating film, 7 Is a via hole for interlayer connection.

【0009】蒸着法を用いた従来の多層プリント配線板
の製造方法では、クロム又はニッケルのめっき下地膜を
ポリイミド層上に蒸着する。蒸着法により製造された多
層プリント配線板が図4(B)に示されており、図4
(A)と実質的に同一構成部分については同一符号が付
されている。7′は層間接続用ビアホールである。
In the conventional method for manufacturing a multilayer printed wiring board using the vapor deposition method, a plating base film of chromium or nickel is deposited on the polyimide layer. A multilayer printed wiring board manufactured by the vapor deposition method is shown in FIG.
The same components as those in (A) are designated by the same reference numerals. 7'is a via hole for interlayer connection.

【0010】[0010]

【発明が解決しようとする課題】無電解銅めっき法を用
いた従来の多層プリント配線板の製造方法においては、
無電解銅めっきのめっき応力が大きいため、特に導体を
ビアホール部分で積層したときに、図4(A)に示すよ
うに、導体とポリイミド層3との間で密着不良8が発生
するという問題があった。
In the conventional method for manufacturing a multilayer printed wiring board using the electroless copper plating method,
Since the electroless copper plating has a large plating stress, there is a problem that adhesion failure 8 occurs between the conductor and the polyimide layer 3 as shown in FIG. there were.

【0011】また、蒸着法を用いた多層プリント配線板
の製造方法においては、図4(B)に示すように層間接
続用のビアホール部分7′でクロム又はニッケルの蒸着
膜の付き回りが不十分となり、接続不良部9が発生する
という問題があった。
Further, in the method of manufacturing a multilayer printed wiring board using the vapor deposition method, as shown in FIG. 4 (B), the coverage of the vapor deposition film of chromium or nickel is insufficient at the via hole portion 7'for interlayer connection. Therefore, there is a problem that the defective connection portion 9 occurs.

【0012】本発明はこのような点に鑑みてなされたも
のであり、その目的とするところは、有機系樹脂から形
成された層間絶縁膜と密着性に優れた導体層を有する多
層プリント配線板の製造方法を提供することである。
The present invention has been made in view of the above circumstances, and an object thereof is to provide a multilayer printed wiring board having an interlayer insulating film formed of an organic resin and a conductor layer having excellent adhesion. It is to provide a manufacturing method of.

【0013】[0013]

【課題を解決するための手段】本発明は、上述した目的
を達成するために、有機系樹脂を層間絶縁膜として用い
る多層プリント配線板の製造方法において、各層間絶縁
膜上に導体層を形成する際に、導体層のめっき下地膜と
して層間絶縁膜上に無電解パラジウムめっきを析出させ
ることを特徴とする多層プリント配線板の製造方法を提
供する。
In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a multilayer printed wiring board using an organic resin as an interlayer insulating film, wherein a conductor layer is formed on each interlayer insulating film. In this case, there is provided a method for producing a multilayer printed wiring board, characterized in that electroless palladium plating is deposited on the interlayer insulating film as a plating base film for the conductor layer.

【0014】[0014]

【作用】無電解パラジウムめっきは、従来法の無電解銅
めっきに比較してめっき応力が非常に小さいため、有機
系樹脂と強い密着力が得られる。その結果、従来の無電
解銅めっき法のように導体形成時に有機系樹脂との密着
不良が生じることがない。
[Function] Since electroless palladium plating has much smaller plating stress than conventional electroless copper plating, strong adhesion with an organic resin can be obtained. As a result, unlike the conventional electroless copper plating method, the adhesion failure with the organic resin does not occur when the conductor is formed.

【0015】また、有機系樹脂は化学的にアルカリに対
して弱いが、無電解パラジウムめっき浴は弱酸性のた
め、従来の強アルカリ無電解銅めっき浴に比べ有機系樹
脂への耐薬品性が向上する。
Further, the organic resin is chemically weak against alkali, but the electroless palladium plating bath is weakly acidic, so that the chemical resistance to the organic resin is higher than that of the conventional strong alkaline electroless copper plating bath. improves.

【0016】[0016]

【実施例】以下、本発明の実施例に係る多層プリント配
線板の製造プロセスを図1を参照して詳細に説明する。
EXAMPLE A manufacturing process of a multilayer printed wiring board according to an example of the present invention will be described in detail below with reference to FIG.

【0017】まず、図1(a)に示すように、セラミッ
ク基板12上にスピンクオータを使用して第1ポリイミ
ド層14を塗布し、約400℃に加熱して第1ポリイミ
ド層14を硬化させる。
First, as shown in FIG. 1 (a), the first polyimide layer 14 is coated on the ceramic substrate 12 using a spin coater and heated to about 400 ° C. to cure the first polyimide layer 14. ..

【0018】次いで、第1ポリイミド層14の表面粗化
をした後、無電解パラジウムめっき16を約2μmの厚
さで一様に析出させ、その上にフォトレジスト18を塗
布する。フォトレジスト18として、ドライフィルムを
ラミネートするようにしてもよい。次いで、マスクを用
いてパターニングを行うと、図1(b)に示す状態が得
られる。
Then, after roughening the surface of the first polyimide layer 14, electroless palladium plating 16 is uniformly deposited to a thickness of about 2 μm, and a photoresist 18 is applied thereon. A dry film may be laminated as the photoresist 18. Next, when patterning is performed using a mask, the state shown in FIG. 1B is obtained.

【0019】次いで、フォトレジスト18を除去した部
分に電解銅めっき膜20を約25μmの厚さで析出さ
せ、その上に電解ニッケルめっき膜22を薄く形成す
る。電解ニッケルめっき膜22を形成した状態が、図1
(c)に示されている。
Next, an electrolytic copper plating film 20 is deposited in a thickness of about 25 μm on the portion where the photoresist 18 is removed, and an electrolytic nickel plating film 22 is thinly formed thereon. The state in which the electrolytic nickel plating film 22 is formed is shown in FIG.
It is shown in (c).

【0020】銅めっき膜20上にニッケルめっき膜22
を形成するのは、後述するステップで塗布する第2ポリ
イミド層の剥離をこの部分で向上させるためである。次
いで、フォトレジスト18を剥離し、さらに無電解パラ
ジウムめっき膜16をエッチングにより除去する。この
状態が図1(d)に示されている。
A nickel plating film 22 is formed on the copper plating film 20.
Is formed in order to improve the peeling of the second polyimide layer applied in the step described later at this portion. Next, the photoresist 18 is peeled off, and the electroless palladium plating film 16 is removed by etching. This state is shown in FIG.

【0021】次いで、スピンクオータを使用して第2ポ
リイミド層24を一様に塗布し、約160℃で第2ポリ
イミド層24を半硬化させた状態で第2ポリイミド層2
4のパターニングを行うと、図1(e)に示す状態が得
られる。
Then, the second polyimide layer 24 is uniformly applied using a spin coater, and the second polyimide layer 24 is semi-cured at about 160 ° C.
When patterning 4 is performed, the state shown in FIG.

【0022】第2ポリイミド層24の表面粗化をした
後、第2の無電解パラジウムめっき膜26を約2μmの
厚さで一様に析出させ、その上にフォトレジスト28を
一様に塗布する。マスクを用いてフォトレジスト28の
パターニングを行うと、図1(f)の状態が得られる。
After roughening the surface of the second polyimide layer 24, a second electroless palladium plating film 26 is uniformly deposited to a thickness of about 2 μm, and a photoresist 28 is uniformly applied thereon. .. When the photoresist 28 is patterned using the mask, the state shown in FIG. 1F is obtained.

【0023】この状態で、フォトレジスト28の除去さ
れた部分に電解銅めっき膜30を約25μmの厚さで析
出させ、フォトレジスト28を剥離する。この状態が図
1(g)に示されている。
In this state, an electrolytic copper plating film 30 is deposited on the removed portion of the photoresist 28 to a thickness of about 25 μm, and the photoresist 28 is peeled off. This state is shown in FIG.

【0024】最後に、無電解パラジウムめっき膜26を
エッチングにより除去することにより、図1(h)に示
すようなビアホール32部分で導体層が互いに接続され
た二層プリント配線板を製造することができる。図1
(h)の拡大図が図2に示されている。
Finally, the electroless palladium plating film 26 is removed by etching to manufacture a two-layer printed wiring board in which the conductor layers are connected to each other at the via holes 32 as shown in FIG. 1 (h). it can. Figure 1
An enlarged view of (h) is shown in FIG.

【0025】三層以上のプリント配線板は、以上のステ
ップを繰り返すことにより容易に製造することができ
る。尚三層以上の導体層の接続は同一ビアホール部分で
行うのではなく、層間接続用ビアホールを段階的に離れ
た場所に形成し、各ビアホールでは二層の導体層を接続
するようにするのが望ましい。
A printed wiring board having three or more layers can be easily manufactured by repeating the above steps. Connection of three or more conductor layers should not be made in the same via hole portion, but via holes for interlayer connection should be formed at gradually separated locations, and two conductor layers should be connected in each via hole. desirable.

【0026】上述した実施例では、図1(c)のステッ
プで、電解銅めっき膜20及び電解ニッケル膜22を形
成しているが、本発明はこれに限定されるものではな
く、それぞれ無電解銅めっき膜及び無電解ニッケルめっ
き膜を析出させるようにしてもよい。同様に、図1
(g)のステップで析出させる電解銅めっき膜30に代
えて、無電解銅めっき膜を析出させるようにしてもよ
い。
In the above-mentioned embodiment, the electrolytic copper plating film 20 and the electrolytic nickel film 22 are formed in the step of FIG. 1 (c), but the present invention is not limited to this, and each is electroless. You may make it deposit a copper plating film and an electroless nickel plating film. Similarly, FIG.
Instead of the electrolytic copper plating film 30 deposited in the step (g), an electroless copper plating film may be deposited.

【0027】次に図3を参照して、本発明の他の実施例
による多層プリント配線板の製造方法について説明す
る。この実施例では、まずセラミック基板42上に第1
ポリイミド層44を形成し、アディティブ法を用いて第
1の無電解パラジウムめっき膜46を第1ポリイミド層
44上に形成する。
A method of manufacturing a multilayer printed wiring board according to another embodiment of the present invention will be described with reference to FIG. In this embodiment, first of all, a first substrate is formed on the ceramic substrate 42.
The polyimide layer 44 is formed, and the first electroless palladium plating film 46 is formed on the first polyimide layer 44 by using the additive method.

【0028】さらに、第2ポリイミド層48を一様に塗
布してパターニングをした後、第2の無電解パラジウム
めっき膜50を同じくアディティブ法で形成して、第1
の無電解パラジウムめっき膜46と第2の無電解パラジ
ウムめっき膜50とを接続する。
Further, after the second polyimide layer 48 is uniformly applied and patterned, the second electroless palladium plating film 50 is similarly formed by the additive method to form the first electroless palladium plating film 50.
The electroless palladium plating film 46 and the second electroless palladium plating film 50 are connected.

【0029】無電解パラジウムめっき浴は弱酸性のた
め、ポリイミド樹脂に対し化学的に安定している。従っ
て、本実施例のようにポリイミド樹脂上に厚付めっきす
ることが可能となり、無電解パラジウムめっきのみで導
体層を形成することができる。
Since the electroless palladium plating bath is weakly acidic, it is chemically stable with respect to the polyimide resin. Therefore, it becomes possible to perform thick plating on the polyimide resin as in this embodiment, and the conductor layer can be formed only by electroless palladium plating.

【0030】本実施例によれば、アディティブ法で導体
層を形成しているため、エッチング工程が不要となると
いう利点がある。上述した実施例では、層間絶縁膜とし
てポリイミド樹脂を採用した実施例について説明した
が、本発明の層間絶縁膜はこれに限定されるものではな
く、テフロン樹脂等の他の有機系樹脂を採用することも
できる。
According to this embodiment, since the conductor layer is formed by the additive method, there is an advantage that the etching process is unnecessary. In the above-mentioned embodiment, the embodiment in which the polyimide resin is adopted as the interlayer insulating film has been described, but the interlayer insulating film of the present invention is not limited to this, and other organic resin such as Teflon resin is adopted. You can also

【0031】[0031]

【発明の効果】本発明は導体層のめっき下地膜としてめ
っき応力が非常に小さい無電解パラジウムめっきを利用
しているため、ポリイミド樹脂との密着力が優れ、導体
層の剥離を防止できるという効果を奏する。
EFFECTS OF THE INVENTION Since the present invention uses electroless palladium plating with very low plating stress as the plating base film of the conductor layer, it has excellent adhesion to the polyimide resin and can prevent peeling of the conductor layer. Play.

【0032】また、無電解パラジウムめっきは弱酸性の
ため、ポリイミド樹脂に対し化学的に安定している。従
って、ポリイミド樹脂に厚付めっきすることが可能とな
り、無電解パラジウムめっきのみで導体層を形成するこ
とができる。
Since the electroless palladium plating is weakly acidic, it is chemically stable to the polyimide resin. Therefore, it becomes possible to perform thick plating on the polyimide resin, and the conductor layer can be formed only by electroless palladium plating.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の製造プロセスを示す図である。FIG. 1 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図2】図1(h)の拡大図である。FIG. 2 is an enlarged view of FIG. 1 (h).

【図3】他の実施例を示す図である。FIG. 3 is a diagram showing another embodiment.

【図4】従来例の問題点説明図である。FIG. 4 is a diagram illustrating a problem of a conventional example.

【符号の説明】[Explanation of symbols]

12 セラミック基板 14 第1ポリイミド層 16,26 無電解パラジウムめっき膜 20 銅めっき膜 22 ニッケルめっき膜 24 第2ポリイミド層 30 銅めっき膜 12 Ceramic Substrate 14 First Polyimide Layer 16,26 Electroless Palladium Plating Film 20 Copper Plating Film 22 Nickel Plating Film 24 Second Polyimide Layer 30 Copper Plating Film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 石田 浩一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 石原 真 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichi Ishida, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor: Makoto Ishihara, 1015, Ueda-anaka, Nakahara-ku, Kawasaki, Kanagawa

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 有機系樹脂を層間絶縁膜(14,24) として
用いる多層プリント配線板の製造方法において、 各層間絶縁膜(14,24) 上に導体層を形成する際に、導体
層のめっき下地膜(16,26) として層間絶縁膜(14,24) 上
に無電解パラジウムめっき(16,26) を析出させることを
特徴とする多層プリント配線板の製造方法。
1. In a method for manufacturing a multilayer printed wiring board using an organic resin as an interlayer insulating film (14, 24), when a conductor layer is formed on each interlayer insulating film (14, 24), A method for producing a multilayer printed wiring board, which comprises depositing electroless palladium plating (16, 26) on an interlayer insulating film (14, 24) as a plating underlayer film (16, 26).
【請求項2】 導体層が無電解パラジウムめっき(16,2
6) 上に銅めっき(20,30) を施した二層構成であること
を特徴とする請求項1記載の多層プリント配線板の製造
方法。
2. The electroless palladium plating (16,2) is used as the conductor layer.
6) The method for producing a multilayer printed wiring board according to claim 1, which has a two-layer structure in which copper plating (20, 30) is applied on the top.
【請求項3】 導体層が銅めっき(20)上にさらにニッケ
ルめっき(22)を施した三層構成であることを特徴とする
請求項2記載の多層プリント配線板の製造方法。
3. The method for manufacturing a multilayer printed wiring board according to claim 2, wherein the conductor layer has a three-layer structure in which nickel plating (22) is further applied on copper plating (20).
【請求項4】 有機系樹脂がポリイミド樹脂であること
を特徴とする請求項1〜3のいずれかに記載の多層プリ
ント配線板の製造方法。
4. The method for producing a multilayer printed wiring board according to claim 1, wherein the organic resin is a polyimide resin.
【請求項5】 無電解パラジウムめっき浴が酸性である
ことを特徴とする請求項1〜4のいずれかに記載の多層
プリント配線板の製造方法。
5. The method for producing a multilayer printed wiring board according to claim 1, wherein the electroless palladium plating bath is acidic.
JP1810892A 1992-02-04 1992-02-04 Manufacture of multilayer printed wiring board Pending JPH05218644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1810892A JPH05218644A (en) 1992-02-04 1992-02-04 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1810892A JPH05218644A (en) 1992-02-04 1992-02-04 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH05218644A true JPH05218644A (en) 1993-08-27

Family

ID=11962426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1810892A Pending JPH05218644A (en) 1992-02-04 1992-02-04 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH05218644A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127433A (en) * 1999-10-26 2001-05-11 Hitachi Chem Co Ltd Printed wiring board and method of production
JP2007016283A (en) * 2005-07-08 2007-01-25 C Uyemura & Co Ltd Direct plating method and palladium conductive body layer forming solution
US20140021491A1 (en) * 2012-07-18 2014-01-23 Carsem (M) Sdn. Bhd. Multi-compound molding
US8992756B2 (en) 2006-11-06 2015-03-31 C. Uyemura & Co., Ltd. Direct plating method and solution for palladium conductor layer formation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167096A (en) * 1983-03-11 1984-09-20 日本電気株式会社 Circuit board
JPH01270398A (en) * 1988-04-22 1989-10-27 Nec Corp Manufacture of multilayer interconnection board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167096A (en) * 1983-03-11 1984-09-20 日本電気株式会社 Circuit board
JPH01270398A (en) * 1988-04-22 1989-10-27 Nec Corp Manufacture of multilayer interconnection board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127433A (en) * 1999-10-26 2001-05-11 Hitachi Chem Co Ltd Printed wiring board and method of production
JP2007016283A (en) * 2005-07-08 2007-01-25 C Uyemura & Co Ltd Direct plating method and palladium conductive body layer forming solution
JP4662039B2 (en) * 2005-07-08 2011-03-30 上村工業株式会社 Direct plating method
TWI424099B (en) * 2005-07-08 2014-01-21 Uyemura C & Co Ltd A direct plating method and a palladium conductor layer to form a solution
US8992756B2 (en) 2006-11-06 2015-03-31 C. Uyemura & Co., Ltd. Direct plating method and solution for palladium conductor layer formation
US20140021491A1 (en) * 2012-07-18 2014-01-23 Carsem (M) Sdn. Bhd. Multi-compound molding
CN103579015A (en) * 2012-07-18 2014-02-12 嘉盛马来西亚公司 Semiconductor package and method for forming the same

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