TW423034B - Method for forming low-impedance high-density deposited-on-laminate structures having reduced stress - Google Patents

Abstract

A method for forming low-impedance high density deposited-on-laminate (D/L) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material which is typically present during thermal cycling of the structure.

Description

V. Description of the invention (1) Related cases of the present invention. The related cases of the present invention are US patent applications 60/0 97, 1 40, and the application date is August 18, 1998. The title is " EXTENDED LAMINATE STRUCTURE AND PROCESS " and U.S. Patent Application No. 60 / 097,169, filed on August 18, 1998, and titled "11 THICKNESS OF COPPER", both of which are owned by the inventor Jan Strandberd. Priority in this case The document also contains a U.S. patent application, 09/12, 7, 5, 7 applications dated July 31, 1998, entitled " METHOD FOR CONTROLLING STRESS IN THIN FILM LAYERS DEPOSITED OVER A HIGH DENSITY INTERCONNECT COMMON CIRCUIT BASE " is owned by Jan Stranberg; and 09/172, 178 application date is October 13, 1998, and is entitled " DEPOSITED THIN FILM LAYER DIMENSIONS AS A METHOD OF RELIEVING STRESS IN HIGH DENSITY INTERCONNECT PRINTED WIRING BOARD SUBSTRATES " as James L Owned by Lykins; and 09 / 191,594, dated 11/13/1998, entitled 11 AN IMPROVED METHOD AND STRUCTURE FOR DETECTING OPEN VIAS I N HIGH DENSITY INTERCONNECT SUBSTRATES " is owned by David J. Chazan. US Patent Provisional Applications 6 0/0 9 7, 1 40 and 6 0/0 9 7, 1 6 9, 09 / 127,579, 09 / 172,178 and 09 / 191,594 This case is also included as a reference for this case. The priority document of this case also contains the US patent application 0 9/1 2 7, 5 8 0 The application date of July 31, 1998 is owned by David J. Chazan. Invention background

O: \ 59 \ 5975S.PTD Page 4 423034-Five 'invention description (2) --- The present invention relates to the application of thin film deposition technology to produce high speed with high density interconnects on the substrate of printed circuit boards structure. In particular, the present invention relates to an improved method, which can minimize the effect of the cumulative stress between the printed circuit body and the top of the deposited film layer, and the soil obtains a relatively low impedance in the resulting structure. A method for generating an interconnect junction of a high-density daughter board in which a device is installed. ‘Packaging The semiconductor industry continues to make more complex integrated circuits with increased density. The increase in complexity has caused the limitations of input / output pads on integrated circuit chips. plus. At the same time, the increase in density on the wafer causes the input / output pads ^ to decrease. The combination of these two trends has led to a considerable increase in the line density of the connector pin rows that need to connect the chip to the external package, and interconnect other integrated circuit devices. Different technologies have been developed to interconnect one or more integrated circuits and related components. One such technology is based on the conventional printed circuit board (PWB) technology ' during the packaging cycle of a surface mount device such as a quad-plate package of integrated circuits '. This technology has been widely used. PWB technology basically uses copper and insulating dielectric material sub-stacks as building blocks to produce the required interconnect structure. The process of forming a copper conductive pattern on a sub-layer in PWB technology basically includes forming a dry film of photoresist on the copper layer, and applying the pattern and developing the photoresist to form a suitable photomask 'as needed. The copper is etched away, leaving a conductive layer on top of the pattern. The substrate used in PWB technology can be manufactured on large-area panels, while providing efficiency that reduces production costs. Interconnects used in this technology,

Page 5 423034-Five 'invention description (3) solution generally has quite good performance, this is because the use of copper and dielectric constant (4.0 or less). But the 'printed circuit board industry cannot keep up with pad density and pad count for semiconductor manufacturing. As a result, there is a capacity gap between the semiconductor manufacturer and the wafer printed circuit board manufacturer. Bonding required in some applications In some applications, one or more laminates are laminated together to form a final structure. The wafers between the stacks can be provided by through holes that are mechanically drilled and then plated. The deliberations process is quite slow and quite responsible, and requires considerable panel space. When the limit of the interconnect junction pad is increased, the interconnect structure is formed by increasing the number of signal layers. Because of these limitations, traditional printed circuit board technology must use Da Dong's metal layers (such as more than 8 layers) for certain applications such as high-density integrated circuit packaging and daughter board manufacturing. The use of too many metal layers in this regard will increase cost and reduce energy consumption. Moreover, the size of the pad limits the density of the cloth in any given layer under this technique. Moreover, PWB technology in some applications cannot provide the density at ’. 'In order to improve the interconnect density of PWB technology, an advanced printed circuit board technology has been developed.' This technology is called building multiple layers. In this technical title, the starting point is the printed circuit board core of Pass 2. Standard drilling and electro-money techniques are used in the core to form plated through holes. From this basic nucleus, this construction method has various applications. Basically, a dielectric layer with a thickness of about 50 microns is formed on the upper and lower main surfaces of the printed circuit board substrate manufactured in the conventional manner. 2 Thin layers ° Grinded by laser in the construction layer, photomask / plasma etching or other well-known = Technology = Make perforations. The electrodeless seeding step is then performed before the plating step of metalizing the upper and lower surfaces. Then apply masking and etch to

423034:

V. Description of the invention (4) Forming the required conductivity in the laminated dielectric layer_1 This technology is a great improvement over the standard PWB technology without a build layer. This build board requires multiple layers to meet the needs of the board. Therefore, this technology is still limited by the improvement of high development. This technology requires multiple layers of zinc to provide extremely dense packaging and sub-density. Another kind of cof ired is used to package high-density interconnect applications. A ceramic substrate, and is commonly referred to as a multilayer. The traditional method is to use a common method. MLC technology involves rolling a ceramic hybrid into MLC technology. Basically dry, punch out the perforation, apply it on the ceramic surface to 'thin one piece' to make this thin film paste to roll the thin moon, stack each layer and stack = rail pattern metal at high temperature (such as greater than 8 5 0 ° C) Cofire to get the required interconnect. MLC has been widely used in high-density and high-reliability applications where high-density interconnect junction packages are more expensive than cost considerations. This capability can lead to hermeticity in Tao Xian and improve the environment that traditional printed circuit board technology can't stand. The technology can be used in high-end packaging applications (such as larger than 丨 00 pads), but it is quite expensive. In addition, performance characteristics such as signal propagation time will cause conflicts due to the equivalent dielectric constant (between 5.0 and 9.0) of ceramic materials. MLC provides higher connection density than pWB technology, but cannot provide the connection density required for some of today's high-density interconnect applications. A third method used in the high-density interconnect and packaging industries is the use of thin film deposition to locate these high-density interconnects. Sometimes this is some D / L technology that is deposited on the stack or in board sensing, and MCM-D or MCM deposition technology in the field of multi-chip modules. In some applications, this D / L technology involves forming and patterning thin conductive conductors on a laminated printed circuit board as described above. This large substrate has a surface of 40 cm by 40 cm or more

Page 7 4 230 3 4 · = V. Description of the invention (5) Product ′ can effectively reduce production costs. D / L technology uses low-cost printed circuit board structural layers): Combined with the traditional large-scale printed circuit board technology and combination of high density = ^ as the starting point, it has considerable cost advantages and is compared with the above PM and MLC technology Its density has improved considerably. Erbei's distinctive feature is that it is only used on printed circuit boards: the film is privately sequenced to produce a high interconnect junction density matrix. High-density interconnects are formed by depositing different layers of insulation and conduction. These deposited layers make the total thickness of several layers less than the thickness of a single-traditional construction layer. This eliminates the need to balance on and below the building layers to prevent matrix entanglement. The D / L process includes first coating an insulating medium on the upper surface of the printed circuit board substrate, depositing a conductive material on the dielectric layer, generating a circuit pattern on the conductive material, and then depositing a lower-insulating and conductive layer. The different layers thus produced are shown using perforations of a variety of well-known techniques, such as chemical etching, exposure and development, or laser grinding. According to this method, a three-dimensional deposition stack structure can be achieved so that a high-density interconnect pattern can be achieved in a small substantial area. Regardless of the limited advantages of D / L technology, there are potential problems in it, that is, the mode or performance limitation of failure will be caused if the deposited thin film layer is not properly configured. An important aspect of the arrangement for depositing a thin film layer on the surface of a printed circuit board substrate is the control of mechanical stresses generated by procedures and operations. The key points of these stress controls are their source, how they are provided, and the structure that minimizes them.

Page 8 423034: V. Description of the invention (6) The stress in the high rear interconnect structure is generated by multiple sources. These sources include the differences in thermal expansion coefficients in dielectrics, laminates, and conductive materials, as well as the actual processing of water vapor absorbed by the printed circuit board substrate and the polymer of the dielectric material in the deposited thin concrete layer. Each of these stresses can be a source of failure, such as cracks in dielectric materials, cracks in conductive materials, and delamination. In any of these examples, an open or short circuit can completely destroy the function of a complete high density interconnect structure. This stress associated with the actual process can actually be removed with proper program design, operator training, and proper crack design. However, the stresses associated with thermal changes must be properly designed to minimize the high-density interconnect structure. There are several reasons for the stress that changes the thermal connection, but as a result, stress builds up at the interface between the conductive features of the metal and the surrounding dielectric of the high-density interconnect structure. If the accumulated amount of stress will cause cracks, if there is no interruption, then the failure caused by the transmission of the upper deposited film. When it is being deposited ', it is desirable to be stressable, including adding a filler to the dielectric layer. The action of the filler is to increase the tolerance of the dielectric layer when it receives stress caused by the thermal mismatch of the materials, which reduces its brittleness. Representative fillers include silicon compounds such as silicon dioxide, silica glass, and the like. Alternatively, rubber compounds can be used as fillers. The problem encountered when adding a filler to a dielectric layer is that the dielectric constant is proportional to the amount of filler contained in the layer. As a result, the tolerance of the dielectric layer becomes smaller. The impedance associated with the structure forming a layer becomes higher. Therefore, there is a need for a low-film, high-density laminate structure with reduced stress. Summary of invention

423034-Five 'invention description (υ) A low-resistance, high-density deposition (D / L) structure is formed on a laminated printed circuit board with reduced stress and reduced metallization = according to this method, it acts on The force per unit area on the electrical material adjacent to the laminated material will decrease, and this force will basically appear during the thermal cycling of the structure. Especially the laminated printed circuit board has two opposite main surfaces, and A conductive wiring pattern is formed on the opposite main surface. The conductive wiring pattern basically includes conductive tracks. Each conductive wire has two sides extending at least from a common area and defines contacts that are transverse to each other. Two One of the sides ends near the first surface. In order to reduce the force acting on the dielectric material, the method includes reducing the area of one of the two sides of the conductive wire. In one embodiment, Through a grinding process, the contact area is increased so that the area is reduced. Now considering the two sides that are actually orthogonal to each other, the formed contacts define a right angle. When the formed structure is provided with For a sharply distributed contact, the use of grinding can increase the surface area of the contact. The increase in surface area reduces the force per unit area of the dielectric material adjacent to the conductive track. In another embodiment, polishing The conductive wiring pattern is measured from the first main surface to reduce the height of a conductive track, ranging from 10 to 20 microns, and reduce the area of one of the two sides of the conductive track. Basis This method can effectively reduce the difference in thermal expansion coefficient between the conductive wiring pattern and the dielectric material. During the thermal cycle, the dielectric material expands or contracts at a greater rate than the conductive wiring pattern. By reducing the first surface and adjacent to the conductive material The spacing between the electrical materials of the wiring pattern can reduce the force acting by the conductive tracks

Page 10 4 2 3 0 3 4 --ί 5. Description of the invention (8) Amount. However, it must be understood that both embodiments can be used in a single structure to further reduce the overall stress. In another embodiment of the present invention, epoxy resin fillers can pass through the holes between opposing major surfaces to reduce stress in the structure. Basically, the through hole is coated with a conductive material and contains an epoxy resin filler. It is necessary to understand the isotropic expansion and contraction of epoxy resin_lipid filler, and it is necessary to understand that the force acting on the conductive material acts on the conductive track, causing the same failure on the dielectric material. To prevent this problem, epoxy fillers are selected with a coefficient of thermal expansion in the range of 20 to 25 X 10_6 / ° C. The features and advantages of the present invention will be further understood from the following description. Please refer to the accompanying drawings when reading. Brief Description of the Drawings Figure 1 is a cross-sectional view of a representative structure of the present invention; Figure 2 is a detailed cross-sectional view of the laminated board of Figure 1; Figure 3 is another view showing the characteristics of the conductive tracks of Figures 1 and 2 Figure 4 is a detailed view showing the characteristics of the conductive trajectory according to the conventional technical structure; Figure 5 is a schematic diagram of the method for forming the above-mentioned Figures 1, 2 and 3 according to the present invention; Figure 6 is a detailed view showing another method according to the present invention The characteristics of the conductive wire of an embodiment, and FIG. 7 are schematic diagrams of a method for forming the circuit of FIGS. 1 and 2 according to the second embodiment of the present invention. Detailed description of the preferred embodiment '' FIG. 1 shows a layer-on-deposit (D / L) structure 10 according to the present invention, which includes a

O: \ 59 \ 59758.PTD Page 11 A23 Ο 3 4 ^ V. Description of the invention (9) Laminated board 12 'This board has two opposite main surfaces 12a and i2b with conductive wiring patterns on it. Conductive wires 43 and 14b are designed. The structure of the laminated board 12 on the surfaces 12a and 12b is a laminated resin insulator 6 with a conductive path embedded therein, such as 18a, 18b. Basically, a through-hole 22 'formed in the laminated board 12 is a resin integrated circuit body inserted between the corresponding openings 22a and 22b in the corresponding opposite surfaces 丨 2a, 丨 2b. The conductive material is located in the through hole 2 2] and conforms to its shape. In this example, the conductive material forms a two-cylindrical shape. Basically, one or more conductive paths 18a, "are in electrical contact with the conductive material 24. Another conductive pad 26 surrounding the opening 22b and The surface 12a is adjacent to each other. In this structure, the conductive material 24 makes the conductive pads Λ phase Λ communicate. 51 The conductive elements of the structure 10 can be formed of any known two-spoon material, but it is preferably made of The same metallic material is shaped like copper containing the material. The phase is adjacent to the laminated board 12, and this layer contains the inverse of the surface ... the structure layer 30 in the dielectric material 32 to allow the connection between & M At this point, a lead contact 36 is disposed in the perforation 34, which is in electrical communication with the conductive track ⑷. The configuration of the conductor is "4 ° to the extended stack, which includes the dielectric layer 42 and the perforation 48, In order to simplify the conduction: the electrical connection between the bit layers 42 '44 through the dielectric layer 42 and the faj of the circuit between the electrical contact 46 and the adjacent extension stack 40-basically, the circuit 50 and the extended stack Layer 4 n-phase gate; between formation-gap 56. Provide mechanical support: two and in the material. Fang Shishi% lice secretion filler or other appropriate

^ 2303 4 '* V. Description of the Invention (ίο) —. _ The problem to be solved by the present invention is the failure of the stress between the conductors. In order to discuss the stress failure of the Λ μη # ^% material, it is necessary to understand the stress at the dielectric interface on the buildable layer of the present invention. In particular, conductive materials / dielectric adjacent material parts, and conductive ^ in / two electric track lines 14a, "b is represented by 6. Must believe this" 丄!, / 20%: parts, picture *. + 7 ′ forms the conductive track Ua, 4b and a and the thermal expansion coefficients of the materials of the construction layer 30 are different. "The material construction layer 30 will be said to be tempered" w. ', ^ 1G ^ CNippon Steel Chemirpl) V-259P coated with a thickness of 20 to 30 micrometers and # 士, A) ^ Gongdacancan .Nippon Steel Chemical Polymer Cardo Acrylic Material Crude By Light Ding Yiyi >

1. -6 /. … "County Chengcheng, and the coefficient of thermal expansion is about 50 X 1 U 6 / C. For example, it is best to be exhausted 99 蛣 埶 Baru uu Oxygen Moon Filler 1 4a, 1 4b and conductive rail pads 22a is made of copper-containing materials. The technology of the coin-injection procedure is from a well-known chromium / copper stack. Other copper alloys (such as chromium / copper / chrome or chromium / palladium, etc.) He Xiong ,,,, and now; and cans can be deposited from the electroplating process. This is the one that is familiar to those skilled in the art. Moreover, the thermal expansion coefficient of the copper containing the material may be equal to the neodymium of the copper ^ j The coefficient of thermal expansion, such as about 16. 5 X IO.6 / This leads to "丨 Electrical material 3 2 is even more than steel with material Specific expansion and contraction. The different shrinkage ratios cause the conductive tracks Ua, Ub, and the conductive conductors 22. When the dielectric material 32 shrinks, a greater force is exerted on the dielectric material 32 per unit area, thereby causing the dielectric material 32 to crack. Now, referring to Figure 2 '3', in order to overcome this problem, you can reduce the conductive rails! 4a, 14b and one or more areas on the side of the opening 22, minus: the force acting on the dielectric material 32 per unit area. It can be seen that there are three exposed sides in each part of the electric 1 4 a 1 4 b and the opening 2 2 a.

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Page 14 4 23 03 4 V. The sharp distribution of the description of the invention (12). Referring now to FIG. ⑴, in step 20 ", the method for forming the mechanical structure 10 includes providing a laminated board 12, the laminated board 12 has a wiring pattern, and is applied to the laminated board 12 using a grinding process A recognizer. For example, 'the laser can be used to perform operations on the laminated board according to the operation function. 12 It can have any desired thickness β. It is best that the laminated board is a micro-thickness. The board is from BT HL 81 by Mitsubishi Corporation. For those who have measured in the middle of the resin medium, the wiring pattern basically includes conductive tracks, generally the conductive tracks 14a, 14b and their thickness ranges between 20 and 30 microns. "From the surface to the guide + track 1 4 The side of a 1 5 a measures the thickness of the conductive wire. In step 202, as described above, the vibration grinding device is placed at the most different position. The two = copper contacts of the conductive track line with the f pattern. The sharp points " V. = 7 = 4 widely used to clean wiring diagrams using standard procedures in well-known techniques. In particular, in antioxidants, # produces oxides on the surface with 1000 angstroms on the surface. In step 206, a dielectric material is deposited by spin method in Table 1b. 32 'At this time, adjacent ones can be made; a flows and is planarized. If necessary', the desired layer is obtained. * Rotate multiple layers to create " The layer 30. In the best method 'the double layer of the material 32 can be made to provide a range At a thickness of 20 to 50 microns. ^ 二甲 20 " 'Form a perforation pattern, such as an image of perforation 34 in dielectric material 2, develop the dielectric material and then remove the developer. At 7 °, The laminated board was baked at 16 0 C for 290 seconds to cure, and the π-eight electrical layer 32 was reflowed. In step 2 i 2, the laminated board i 2 was placed at

O: \ 59 \ 59758.PTD Page 15; 42303 4

V. Description of the invention (13) Remove the residue from the plasma of the source (such as 〇2) and fluorine source (such as F2). Denso also hardens the remaining surface on the configuration opposite to the surface 12a. At step 214, expose the surface to the surface of the oxide on the surface of the “Packaging Section 32” sample. After that, remove the area of the surface 12a in the wiring diagram 'in step 216': to the laminate 12 According to this method, copper having a thickness of about 20,000 angstroms is covered in this method, and the metal layer is formed by a dielectric material 32 including metal red gold 1U ^ exposed. The method can be known to those skilled in the art. Deposit the seed layer. In the better case, the different crystals can be used. The seed layer is a superposition of copper / copper, and the chromium layer is about 2000 Angstroms thick. The adhesion layer is about 2000 angstroms, and each layer can be deposited by a sputtering process. 4 1 layer In the step 218, a photoresist layer is deposited on the seed layer and the seed layer is hidden. Multiple parts of the substrate were exposed to UV light, and the exposed layer was developed to remove the required parts in the photoresist. Thereafter, a plating process is performed in step 22o, in which the laminated board 12 is immersed in a plating bath (such as by Technics Corporation). 4 SFT key tool), and electrical contacts on the seed layer are made around the laminated board 12 (outside the action layer). In the plating bath, the laminate is positioned in two opposite anodes, so that the material can be plated on both surfaces 12a and 12b. This results in all exposed pads on surfaces i2a, 12b being plated. The exposed pad on the top contains conductive contacts 3 β. Because the method of the present invention uses a design criterion, in which all the recording through holes are electrically connected to the conductive pad 36 > can be placed on the bottom of the through holes that are connected to each plating Perform plating unless there is a defect (open) on the substrate α In step 222 t, remove the resistor and etch the copper to leave the required wiring pattern. Thereafter, in step 2 2 4, perform an electrical test to check the wiring pattern.

Page 16 -i Ο 3 4 1 V. Description of the invention (14) Efficiency Electrical performance. The above steps can be repeated to deposit another layer on the substrate 10. In addition, although there is no special explanation in the above, in any of the above steps, you can perform various visual observations to test the failure during manufacturing. 160 with 60 traditional right angles. As shown in the figure, the second line 14 and the second line 14 of FIG. 4 compete, and the pattern of the contact 160 causes the area of the side 115a, U5b, lie of the conductive track line ii4a to decrease. Product ϊ = Λ Figure 6. In another embodiment of the present invention, the wiring pattern on the surface 112a of the plate 112 can be polished by polishing, which can be further-step by step reduced Γ! = 32 per unit area acting on Strength, according to this side; n = fii4a, the height of the conductive traces on the surface u2a is reduced from the measurement of the surface 1123 edge 11513 by 10 to 20, which is a hindrance. As a result, the area of two = edges 115a, mc can be reduced. This can be seen in the significant reduction in failures in the region 160 in the dielectric material 132. In particular, it is believed that by the vertical separation of the dielectric material 132 from the region 160 of the surface 1123, a stress acts on the region during thermal cycling due to the accelerated shrinkage of the dielectric material 132. As described above, 'the less stress is applied to the area from the wiring pattern, the dielectric material can be made thinner, and less filtering is applied, so a lower dielectric constant can be provided to the structure, so Get lower impedance a. Now refer to Figure 7 'The procedure for manufacturing the structure is similar to that illustrated in Figure 5' except that step 202 is replaced by step 302, where the wiring pattern on the board can be polished to A height of 10 to 20 microns. However, a height of 12 microns is preferred. The other steps 300,304,306, and -423034 in Fig. 7 are described in the fifth invention description (15) 308, 310, 312, 314, 316, 318, 320, 322, and 324, which are the same as steps 204 and 206 in Fig. 5. , 208, 210, 212, 214, 218 * 220, 222 and 224. However, it must be understood that in steps 302, 202 can be combined into a common D / L structure 10. The result method can be the same as that in Fig. 7, and the method shown in Fig. 5 includes step 202. The combination of the above-mentioned sharply distributed contacts can reduce the stress and the amount by polishing the wiring pattern to the marginal height of 10 to 20 microns. Referring now to FIG. 1, in another embodiment of the present invention, the stress on the dielectric material 32 can be reduced by establishing the thermal expansion coefficient of the epoxy resin filler disposed in the through-hole 22. In particular, the stress on the electrical material adjacent to the contact 17 was found to swell with the grease filler. Resin filler 23 and other electrical materials 24 act on one, and most of the conductance is less than one millimeter. It is better than the force of the present invention, preferably in the range of ° C. The dielectric material is used in the same meter. The results used more epoxy inside. It is believed that the structural failure due to the large potential expansion of the material is less. The filling agent helps to arrange the thickness of the base layer 12 in the through hole 2 2. Shows the amount of crossings for the configuration. This power is transmitted to Jie. Previously, it was not believed that the laminated board in this similar structure was filled with epoxy resin in the through hole to reduce the conductivity of the epoxy hole in the dielectric material with a thermal expansion coefficient of 20 to 25 in epoxy resin. Material 3 2 question, the thickness of the test and the amount of filler should be X 10 ″ / Although Wen Shen already needs to understand the layer structure of the spirit and viewpoints that can be matched, it should be implemented according to the examples. For example, the three embodiments of the present invention are familiar to those skilled in the art without departing from the present invention. The use of a technology is described, but all of them can be used to explain the invention, alterations, and changes.

423034 ^ V. Description of the invention (16) is included in the common structure, or any combination of two of the three embodiments is included in the common structure, and the third embodiment may be omitted if omitted. The last 1 printed circuit board is made of copper as the conductive material, but any conductive material such as aluminum, gold, etc. may be used. Those skilled in the art may use other methods of using stress, which are all within the viewpoint of the present invention. Therefore, the viewpoint of the present invention is defined by the scope of patent application.

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Claims (1)

4 230 3 4-: VI. Scope of patent application 1. A method for forming a stacked structure on a laminated printed circuit board of a type having a metal wiring pattern, the method includes the following steps: A construction layer of a dielectric material is formed on the pattern, and the wiring diagram-· has a conductive track line, which extends from a common area on both sides, defines, contacts, and is arranged at an edge 1 with each other and the dielectric material and The conductive tracks have different thermal expansion coefficients, which results in that a force can be applied per unit area of the construction layer when cycling within a temperature range; and when the construction layer and the conductive track circulate through the temperature In the range, the force acting on the dielectric material per unit area is reduced by the contact. 2. The method of item 1 in the scope of patent application, wherein reducing the force per unit area includes increasing the area of the contact. 3. The method according to item 1 of the patent application scope, wherein reducing the force per unit area includes grinding the conductive track area near the contact. 4. The method according to item 1 of the patent application scope, further comprising forming an extended stack adjacent to the construction layer. 5. If the method of claim 1 of the scope of patent application, it further includes disposing a semiconductor circuit adjacent to the extended stack, and the extended stack and the construction layer include conductive lines, so that the semiconductor circuit and The wiring pattern is electrically connected. 6. If the method of claim 1 is applied, the laminated printed circuit board has a laminated surface, and reducing the force per unit area includes the step of polishing the metal wiring pattern so that the amount from the laminated surface ≫ Decrease the height of a conductive track in the range of 10 to 20 microns (including 10 and 20) Page 20 42303 ^ VI. Patent Application Range Micron) ° 7. For the method in the 6th Patent Application Range, the height is 12 μm. 8. The method according to item 1 of the scope of patent application, wherein the laminated printed circuit board has two opposite main surfaces, one of which has a through hole extending through the two surfaces, so that fluid can pass through the two surfaces. On the opposite surface, the through hole is covered with a metal material, and a non-conductive filler is arranged therein. The thermal expansion coefficient of the filler ranges from 20 to 25 X 1 0_6 / ° C. 9. A method of forming a deposition structure on a stack on a layered printed circuit board having a metal wiring pattern, the method comprising the following steps: forming a construction layer of a dielectric material on the wiring pattern, the The wiring pattern has a conductive track, two sides of which extend from a common area, define-contacts, are arranged laterally with each other, and reduce the area of one of the two sides. 1 0. The method according to item 9 of the patent application scope, wherein reducing the force per unit area includes grinding the conductive track area near the contact > thus reducing the area of the contact. 11. The method of claim 9 in which the laminated printed circuit board has a laminated surface, and reducing the force per unit area includes the step of polishing the metal wiring pattern so that it is measured from the laminated surface. , Reduce the height of a conductive track, which ranges from 10 to 20 microns (including 10 and 20 microns). 1 2. The method according to item 9 of the scope of patent application, wherein reducing the area includes grinding the conductive track area close to the contact, and polishing the metal wiring pattern. O: \ 59V59758.FTD Page 21 423034 6. Scope of patent application To reduce the height of the conductive wire from 10 to 20 microns from the surface of the laminate. 1 3. The method according to item 9 of the scope of patent application, which further comprises forming an extended stack adjacent to the construction layer. 14. The method according to item 13 of the scope of patent application, which further comprises forming an extended stack adjacent to the construction layer. 15. —A method of forming a stacked structure on a laminated printed circuit board of a type having two opposing major surfaces, wherein a through hole extends between the two opposing major surfaces, the method comprising: A conductive material is coated on the through hole; and a filler is arranged in the through hole, and its thermal expansion coefficient is between 20 and 25 X 10_6 / ° C. 16. The method according to item 15 of the patent application scope, further comprising forming a metal wiring pattern on one of the two opposite main surfaces, and disposing a construction layer of a dielectric material on the wiring pattern. The wiring pattern has a conductive track line, and the two sides of the conductive track line extend from a common area to form a contact. The two sides are arranged laterally to each other to reduce the area of one of the two sides. 1 7. The method according to item 16 of the scope of patent application, wherein reducing the area includes grinding the area adjacent to the conductive track line adjacent to the contact, thereby increasing the contact area. 18. The method according to item 17 of the scope of patent application, wherein reducing the area includes polishing the metal wiring pattern, and reducing the height of a conductive track from one of the two opposite main surfaces, the range of which is 10 Within 20 microns. Page 22 423034 VI. Application for Patent Scope 1 9. The method for applying for item 18 in the scope of patent application, where the height is 12 μ °° 2 0. For the method for applying for item 18 in the scope of patent application, which is also included in An extended stack is formed adjacent to the construction layer, and a semiconductor circuit is disposed adjacent to the extended stack. The extended stack and the construction layer include conductive lines, which can make the semiconductor circuit and the circuit pattern. China Unicom. Page 23