JP2018113392A - Wiring board, multilayer wiring board, and method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a glass wiring board improving reliability of connection among wiring layers on a front surface and a rear surface of a glass substrate, and conductive layers in through-holes; and a method for manufacturing the glass wiring board.SOLUTION: A wiring board 100 comprises through-holes 2 for electrically connecting wiring layers 6 formed on a front surface and a rear surface of a glass substrate 1. The wiring board further comprises: conductive seed layers 3 and 4, and a conductive layer 5 which are arranged on an inner wall face of each through-hole in this order; and an insulative substance filled inside the conductive layers of the through-holes. In the wiring board, protrusions extending from the inner wall faces of the through-holes are provided on the through-holes of the front surface and the rear surface of the glass substrate; and the conductive seed layers and the conductive layer are arranged on side faces of the protrusions in this order. On top portions of the protrusions opposed to the front surface and the rear surface of the glass substrate, wiring layers are provided through the conductive seed layers.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board using a glass substrate with high connection reliability, a multilayer wiring board using the wiring board, and a method for manufacturing the wiring board.

  In recent years, a semiconductor device using a semiconductor chip and an external connection device has been used in many products such as electronic devices and automobiles. As these products become more sophisticated, smaller, and lighter, semiconductor devices are required to be smaller, have more pins, and have fine pitches for external connection terminals. Conventionally, organic materials such as epoxy resins and glass-epoxy materials impregnated with glass fibers have been used as semiconductor substrate materials. However, many organic materials have a relatively high water absorption rate. Compared with a silicon semiconductor chip, the shrinkage and expansion due to temperature are large, so it is difficult to form fine wiring that matches the scale of the semiconductor chip and reliability after connecting to the semiconductor chip. There was a big problem in terms of securing.

  Accordingly, silicon and glass are attracting attention as materials for semiconductor substrates that can replace organic materials. Since the expansion and contraction due to moisture absorption and temperature is greatly reduced as compared with organic materials, these have great advantages in terms of formation of fine wiring and connection reliability with a semiconductor chip.

  Comparing the two, a substrate made of silicon can be formed with finer wiring than a glass substrate by utilizing know-how of manufacturing a semiconductor chip, and further, a through electrode (TSV: Through-Silicon-Via) is formed. Although the process has been established, its shape is limited to a disk shape, and there are also disadvantages that the periphery of the wafer cannot be used, and that it is difficult to manufacture in a large size. On the other hand, a glass substrate has not yet been established, but can be enlarged using know-how in display materials.

  Furthermore, considering the comparison in terms of electrical characteristics, the silicon substrate is a semiconductor, whereas the glass substrate is an insulator. Therefore, even in a high-speed transmission circuit, there is no concern about the generation of parasitic elements, and it can be said that the electrical characteristics are superior. . In the first place, in the case of a glass substrate, a process itself for forming an insulating film on the surface thereof is not necessary, so that the insulation reliability is essentially high and the process can be shortened.

  As described above, the glass substrate has many advantages, but there is a problem that the manufacturing process has not been sufficiently established. In particular, due to its brittleness, it is difficult to form a through electrode (TGV: Through-Glass-Via) required for electrical conduction on the surface, and the adhesion between copper, which is the mainstream of wiring materials, is weak. Therefore, there is a problem in that the reliability of wiring formation is not high.

As a method for manufacturing a wiring board using a glass substrate that is widely used at present, there are the following methods. 11A to 12L are cross-sectional views for explaining a method for manufacturing a wiring board according to the prior art.
(1) First, a through hole 2 is formed in a glass substrate 1 (FIG. 11A) by a method such as laser processing or etching (FIG. 11B).
(2) The conductive seed layer 3 is formed on the side wall of the through hole 2 and the front and back surfaces of the glass substrate 1 by a method such as sputtering or vacuum deposition (FIG. 11C).
(3) A conductive seed layer 4 (electroless plating layer, for example, copper) is formed on the side wall of the through hole 2 and on the front and back surfaces of the glass substrate 1 (FIG. 11 (d)).
(4) The conductive layer 5 (for example, copper) is formed on the side wall of the through hole 2 and the front and back surfaces of the glass substrate 1 (FIG. 11 (e)).
(5) The insulating resin 7 is filled into the through hole 2 by a method such as screen printing (FIG. 11 (f)).
(6) The insulating resin 7 and each conductive layer on the front and back surfaces of the glass substrate 1 are removed by a method such as CMP (physicochemical polishing) (FIG. 11G).
(7) A conductive seed layer 10 is laminated on the front and back surfaces of the glass substrate 1 by a method such as sputtering or vacuum deposition so as to establish conduction with the conductive layer 5 on the front and back surfaces of the glass substrate 1 (FIG. 11 (h)).
(8) A resist pattern 13 is formed on the front and back surfaces of the glass substrate 1 by photolithography or the like (FIG. 11 (i)).
(9) The wiring pattern 6 is plated up by electrolytic plating (for example, copper) to form the wiring layer 6 (FIG. 11 (j)).
(10) The resist pattern 13 is peeled off (FIG. 12 (k)).
(12) The conductive seed layer 10 exposed by etching is removed (FIG. 12L).
In the case of manufacturing a multilayer wiring board, in addition to this, build-up layer formation, plating on the outermost layer, etc. are followed.

  Through the above steps, the wiring substrate 200 having the cross-sectional configuration as shown in FIG. 9 is completed. Further, the multilayer insulating substrate 201 is manufactured by forming the interlayer insulating layer 8 and the connection hole 9, the conductive seed layer 10, the wiring layer 12, the conductive layer 11 and the like on the front and back surfaces of the wiring substrate 200 by the build-up method. be able to.

The problem in the manufacturing process of the wiring board is to ensure the reliability of the electrical connection between the conductive layer 5 and the wiring layer 6 on the front and back surfaces of the glass substrate 1 in the processes (7) and (9). .
As shown in FIG. 13, the insulating resin 7 such as the openings of the through holes 2 on the front and back surfaces of the glass substrate 1, the conductive layer 5, and the underlying conductive seed layers 3 and 4 are removed (FIG. 11 (f)). , (G)), when the front and back surfaces of the glass substrate 1 and the exposed surface of the insulating resin 7 and the like are substantially in the same plane, the contact between the conductive seed layer 10 and the conductive layer 5 formed in the subsequent process. Is only the exposed cross section of the conductive layer 5, and the contact area between the two is reduced (see the enlarged view on the right side of FIG. 13). Therefore, when the conductive layer 5 is kept thin due to requests for processing cost, processing speed, etc., the contact area is further reduced, and connection reliability may be insufficient.

  Thus, as a technique for improving the connection reliability in a structure in which two conductors are brought into contact to establish electrical conduction, for example, in Patent Document 1, it is formed on the front and back surfaces of an insulating film of a double-sided flexible printed wiring board. As a structure for conducting the conductor wiring, a conductor press-fitting hole that is expanded on one or both sides is provided at a portion where the conductor wiring on the front and back surfaces overlaps, and the conductor is pressed into the conductor press-fitting hole without any gap. In the interlayer connection part where the press-fitting hole is deformed into a mortar shape, the conductor wiring layer formed on one surface and the conductor are joined, and the part protruding from the other wiring layer is covered and partly covered. An interlayer connection structure is disclosed in which a conductor is joined to a conductor wiring layer on both sides deformed into a drum shape of a conductor press-fitting hole.

In this interlayer connection structure, since the conductor wiring layer deformed into a drum shape of the conductor press-fitting hole and the conductor of the conductor press-fitting hole are joined, the contact area increases, so that the connection reliability can be improved. Become.
However, this technique cannot be applied to a configuration in which an insulating resin is filled in the through holes of the insulating substrate as shown in FIG.

  Therefore, after forming the through hole in the glass substrate, in the wiring substrate using the glass substrate of the configuration in which the conductor is formed on the front and back surfaces of the glass substrate and the inner wall surface of the through hole, and the through hole is filled with an insulating resin, There has been a demand for a wiring board having improved connection reliability of a through hole interlayer connection structure in which front and back conductor wirings are formed on a glass substrate.

JP 2007-189125 A

  The present invention has been made in view of the above circumstances, and provides a glass wiring board having improved connection reliability between a wiring layer on the front and back surfaces of a glass substrate and a conductive layer in a through hole, and a method for manufacturing the same. The task is to do.

As means for solving the above-mentioned problem, the invention according to claim 1 of the present invention is a wiring board having a through hole for electrically connecting wiring layers formed on the front and back surfaces of a glass substrate,
The inner wall surface of the through hole is provided with a conductive seed layer and a conductive layer,
The inside of the conductive layer is filled with an insulating material,
The through holes on the front and back surfaces of the glass substrate are provided with protrusions extending from the inner wall surface of the through holes,
At least a conductive layer and a conductive seed layer are provided on the side surface of the protrusion, and a wiring layer is provided on the top of the protrusion facing the front and back surfaces of the glass substrate via the conductive seed layer. A wiring board characterized by the above.

  According to a second aspect of the present invention, there is provided a multilayer wiring board having a build-up layer on one side or both sides of the wiring board according to the first aspect.

The invention according to claim 3 is a step of providing a through hole in the glass substrate;
Providing a conductive seed layer and a conductive layer in this order on the front and back surfaces of the glass substrate and the inner wall of the through hole;
Filling the through hole with an insulating material;
A step of exposing the glass surface by removing the insulating substance, the conductive seed layer, and the conductive layer attached to the front and back surfaces of the glass substrate;
Etching and removing the glass on the front and back surfaces of the glass substrate to reduce the thickness by a predetermined dimension;
Providing a conductive seed layer on the front and back surfaces of the glass substrate;
Providing a resist pattern comprising a negative pattern of the wiring pattern to be formed on the surface of the conductive seed layer;
And a step of providing a wiring layer on a conductive seed layer on which no resist pattern is formed.

  According to the wiring board of the present invention, since the contact area between the conductive layer and the wiring layer can be increased, it is possible to reduce defects that cannot be connected to each other when the wiring layer is formed on the surface of the glass substrate. In a use environment after completion, the possibility of disconnection between the conductive layer and the wiring layer is reduced.

  Further, according to the manufacturing method of the present invention, the insulating material and the conductive layer on the front and back surfaces of the glass substrate are once removed to expose the upper and lower end surfaces of the insulating material and the front and back surfaces of the glass substrate. By etching, a part of the conductive layer can be protruded, so that the contact area between the conductive layer and the wiring layer can be increased.

The principal part sectional view of the wiring board concerning one embodiment of the present invention. The principal part sectional view of the wiring board concerning one embodiment of the present invention. 1 is a cross-sectional view of a main part of a multilayer wiring board according to an embodiment of the present invention. Sectional drawing explaining the manufacturing method of the wiring board which concerns on one embodiment of this invention. Sectional drawing explaining the manufacturing method of the wiring board which concerns on one embodiment of this invention. Sectional drawing explaining the manufacturing method of the wiring board which concerns on one embodiment of this invention. The top view and enlarged view which showed arrangement | positioning of the test pattern which evaluates the electrical connectivity of an Example and a comparative example. Sectional drawing and a top view for demonstrating the structure of the test pattern which evaluates the electrical connectivity of an Example and a comparative example. Sectional drawing of the principal part of the wiring board which concerns on a prior art. Sectional drawing of the principal part of the multilayer wiring board which concerns on a prior art. Sectional drawing explaining the manufacturing method of the wiring board which concerns on a prior art. Sectional drawing explaining the manufacturing method of the wiring board which concerns on a prior art. Sectional drawing of the principal part of the wiring board which concerns on a prior art.

  Hereinafter, a wiring board, a multilayer wiring board, and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the drawings.

<Wiring board>
The wiring board of this invention is a wiring board provided with the through-hole which electrically connects the wiring layer formed in the front and back of a glass substrate.
A conductive seed layer and a conductive layer are provided in this order on the inner wall surface of the through hole of the wiring board of the present invention. The inside of the conductive layer of the through hole is filled with an insulating resin that is an insulating material. The through holes on the front and back surfaces of the glass substrate are provided with protrusions extending from the inner wall surface of the through hole.
A conductive seed layer and a conductive layer are provided in this order on the side surface of the protrusion, and a wiring layer is provided on the top of the protrusion facing the front and back surfaces of the glass substrate via the conductive seed layer. .

  1 and 2 are sectional views of the main part of a wiring board 100 according to an embodiment of the present invention. As shown in FIGS. 1 and 2, the wiring board 100 includes a glass substrate 1 having a through hole 2, The conductive layer 5 laminated on the side wall of the through hole 2 and the insulating resin 7 filling the through hole 2 are included. Conductive seed layers 3 and wiring layers 6 are formed on the front and back surfaces of the glass substrate 1, and conductor seed layers 3 and 4 are laminated on the lower layer of the conductive layer 5 on the side walls of the through holes 2 of the glass substrate 1. . The insulating resin 7 and the conductor layers (conductive seed layers 3, 4 and conductive layer 5) that cover the side wall surfaces thereof are formed so as to protrude from the front and back surfaces of the glass substrate 1 by a predetermined height. A wiring layer 6 is laminated on the front and back surfaces of the glass substrate 1, and the wiring layer 6 and the conductive layer 5 are electrically connected via a conductive seed layer 30.

  As shown in FIG. 2, the insulating resin 7 filled in the through hole 2 and the conductor layer covering the side wall surface are in a position protruding from the entrance of the through hole 2, and the front and back surfaces of the glass substrate 1 and the insulating resin 7 There is a step 16 between the exposed surface. Since the wiring layer 6 and the conductive layer 5 on the surface of the glass substrate 1 can be connected along the side wall forming the step 16, the connection area can be increased as compared with the case where there is no step 16. A convex portion extending from the through hole 2 forming the step 16 in a direction orthogonal to the surface of the glass substrate 1 is referred to as a protruding portion.

  FIG. 3 is a cross-sectional view of a main part of the multilayer wiring board 110 according to the embodiment of the present invention. As shown in FIG. 3, the multilayer wiring board 110 is formed by alternately laminating interlayer insulating layers 8 having wiring holes 9 and wiring layers 12 on one or both sides of the wiring board 100 via conductive seeds 10. 6 and the wiring layer 12 are conducted by the conductor layer 11 formed in the connection hole 9 of the interlayer insulating layer 8. A plating layer 15 is formed on the wiring layer 12.

  Next, a method for manufacturing the wiring board 100 and the multilayer wiring board 110 will be described in detail with reference to FIGS.

  First, a through hole 2 is opened at a desired position on the glass substrate 1 (FIG. 4A) (FIG. 4B). The type of glass is not particularly limited, and for example, quartz glass, alkali-free glass, borosilicate glass, or the like can be used. The means for forming is not particularly limited, and wet etching, dry etching, laser processing, electric discharge processing, and the like can be used.

  Next, conductive seed layers 3 and 4 are formed at least inside the through hole 2 formed in the glass substrate 1 (FIGS. 4C and 4D). As the conductive seed layers 3 and 4, an electroless plating layer, a sputter layer, a vacuum vapor deposition layer, and the like are conceivable. From the viewpoint of ensuring adhesion with the glass substrate 1, It is desirable to laminate Ti by sputtering. And when laminating | stacking a copper layer on it, it is desirable on the surface of adhesiveness to laminate | stack a copper layer on a Ti layer similarly by sputtering.

  Note that when the conductor seed layers 3 and 4 are formed in the through hole 2, it is formed only in the through hole 2, and a resist layer is formed in advance on the front and back surfaces of the glass substrate 1. It is also conceivable to prevent the conductor from adhering. However, since the process becomes complicated and it is convenient that the entire substrate is conductive when the electrolytic plating is performed later, in this description, the conductor seed layer 3, Although the process of forming 4 and removing it later will be described, the present invention is not limited to this.

  Next, electrolytic plating is performed to form a strong conductive layer 5 at least in the through hole 2 (FIG. 4E). The metal to be electroplated is not limited, but copper that is excellent in terms of cost, electrical properties, workability and the like is desirable.

  Through the previous steps, the inside of the through hole 2 is in a hollow state in which the conductive seed layers 3 and 4 and the conductive layer 5 are laminated on the side wall thereof. This causes rupture and conductor peeling in the subsequent process and the use environment after the completion of the substrate. Therefore, in the next process, the hollow portion is sealed (FIG. 4F). As a material for sealing, there may be both an insulating substance mainly composed of an organic polymer or the like, a conductive paste in which silver particles or the like are dispersed. Here, since the conductive layer 5 is formed on the side wall of the through hole 2 in the previous process, the insulating resin 7 is filled, but a conductive paste may be filled. The insulating resin 7 is not particularly limited, but an epoxy resin is desirable from the standpoints of insulation and workability.

  The filling method of the insulating resin 7 is not particularly limited, and there are a press method, a printing method, a molding method, etc., but printing using a silk screen mask is possible due to the ease of processing and high processing quality. The method is preferably used. When this method is used, the insulating resin 7 overflows on the front and back surfaces of the glass substrate 1 after filling the through holes 2. The overflowed resin becomes a layer having a uniform thickness and can be laminated on the front and back surfaces of the glass substrate 1, but in many cases, the resin is scattered in islands having a non-uniform thickness.

  In the steps so far, the conductive layer 5 is laminated on the front and back surfaces of the glass substrate 1, and the insulating resin 7 overflowing from the through hole 2 is formed thereon. Next, the front and back surfaces of the glass substrate 1 are polished and removed. This means is not particularly limited, but CMP (Chemical Mechanical Polishing) is preferable from the viewpoint of high processing quality and easy processing. CMP is performed until the front and back surfaces of the glass substrate 1 are completely exposed (FIG. 4G).

  Through the steps so far, the front and back surfaces of the glass substrate 1 and the exposed surfaces of the conductive layer 5 and the insulating resin 7 are substantially flush with each other. Next, the insulating resin 7 and the conductor layers (conductive seed layers 3, 4 and conductive layer 5) that cover the side wall surfaces thereof are projected from the front and back surfaces of the glass substrate 1. Although this method is not particularly limited, there is selective etching of the glass surface as a method that can be simply carried out without covering the front and back surfaces of the glass substrate 1 with a mask, a resist, or the like. Specifically, by dipping the entire glass substrate 1 in the state shown in FIG. 4G in a glass etching solution containing hydrofluoric acid as a main component under appropriate conditions, the insulating resin 7 and the conductor Since the layer is not affected and only the glass is etched, as a result, the insulating resin 7 and the conductor layer covering the side wall surface protrude from the surface of the glass substrate 1 (FIG. 4H). Although depending on the type of plating solution, the front and back surfaces of the glass substrate 1 and the exposed surface of the conductive layer that covers the side wall surface of the insulating resin 7 that protrudes as the glass etching progresses (protrusion portion), The growth rate of plating is different. Therefore, assuming a conformal shape, the height of the protrusion near the entrance of this TGV (Through Glass Via) is required to be at least as high as the thickness of the conductive layer 5. On the other hand, if the protruding portion is too high, there is a possibility that an adverse effect may occur due to resin embedding properties, plating coverage, and the like. Therefore, the height of the protrusion (step 16) is preferably 0.25 times or more the thickness of the wiring layer 6 formed on the glass substrate 1. And more preferably, it is 0.5 times or more.

  Next, the conductive seed layer 30 is again laminated on the front and back surfaces of the glass substrate 1, the conductive seed layers 3 and 4, the conductive layer 5, and the insulating resin 7. The method is not particularly limited, but in the present embodiment, film formation of Ti and copper by a sputtering method is employed (FIG. 4 (i)). In this step, the conductive seed layer 30 newly formed on the front and back surfaces of the glass substrate 1 is bonded to the conductive layer 5 with a wider contact area due to the effect of providing the protruding portion from the glass surface in the previous step. doing.

  Next, a resist pattern 13 is formed on the conductive seed layer 30 on the front and back surfaces of the glass substrate 1 by photolithography (FIG. 4J). After applying the resist pattern 13 to the entire surface of the glass substrate 1, the resist pattern 13 is formed by exposing through a predetermined mask and removing the excess pattern of the resist by development. In this case, the resist pattern 13 needs to be formed thicker than a desired plating thickness in the subsequent electrolytic plating process. Further, the resist pattern 13 in this case is a so-called negative pattern in which the resist in a necessary portion of the wiring is removed when the semi-additive method is used in the subsequent wiring forming process, and the subtractive method is used. In the case of doing so, it is a positive pattern.

  Next, the wiring layer 6 is formed on the conductive seed layer 3. In this figure, the semi-additive method is adopted, but the present invention is not limited to this. In this embodiment, a conductor is grown on the conductive seed layer 30 to a desired thickness by electrolytic plating (FIG. 5 (k)).

  Next, the resist pattern 13 is removed (FIG. 5L). Subsequently, the conductive seed layer 30 is removed to complete the wiring pattern (FIG. 5M). In removing the conductive seed layer 30, a method of sequential selective etching according to the materials constituting the layer is suitable, but the method is not limited to this. In this embodiment, since the conductive seed layer 30 is in the order of sputtered copper and sputtered Ti when viewed from the outside, first, a conductive seed is formed using a copper etching solution, specifically, a sulfuric acid-hydrogen peroxide etching solution. Remove the copper of layer 30. At this time, since the copper forming the wiring layer 6 is also dissolved, the copper in the conductive seed layer 30 is completely removed, and the etching of the copper in the wiring layer 6 can be performed under conditions that do not cause a problem. is necessary. Next, Ti is etched. In this case, if an etchant having selectivity for Ti is used, there is no need to worry about dissolution of the wiring layer 6.

  Thus, the wiring board 100 is completed. Subsequently, processing of the buildup layer will be described.

<Multilayer wiring board>
The multilayer wiring board of the present invention is a multilayer wiring board in which a buildup layer is formed on one side or both sides of the wiring board of the present invention.

A method for manufacturing a multilayer wiring board according to the present invention will be described.
First, the interlayer insulating layer 8 is formed on the front and back surfaces of the wiring substrate 100 (FIG. 5 (n)). Examples of the material include, but are not limited to, an epoxy resin, a polyimide resin, and a SiO ₂ film. The lamination method may be a sol-gel method, a vacuum deposition method, spin coating, lamination, press, or the like, but is not limited thereto. In this embodiment, it is assumed that an epoxy film-like insulator is laminated and formed by a vacuum press. About the thickness of the interlayer insulation layer 8, the thickness which can cover a protrusion part reliably is selected.

  Subsequently, a via hole is formed in the interlayer insulating layer 8 for electrical connection with the lower wiring layer 6. First, connection holes 9 are formed in the interlayer insulating layer 8 by laser processing, drilling, or the like (FIG. 5 (o)). By filling the connection hole 9 with a conductive material, a via hole is completed. In this embodiment, this is performed simultaneously with the formation of the wiring pattern on the interlayer insulating layer 8.

  After providing the connection hole 9 in the interlayer insulating layer 8, the conductive seed layer 10 is provided in the connection hole 9 and on the surface of the interlayer insulating layer 8. The formation method is not particularly limited, but electroless copper plating is used in the present embodiment (FIG. 5 (p)).

  Next, a resist pattern 14 is formed on the conductive seed layer 10 (FIG. 5 (q)). About a detailed method, it is the same as that of formation of the resist pattern 13 on the glass substrate 1 demonstrated previously. The connection hole 9 subjected to electroless copper plating as described above is handled in the resist pattern 14 in the same manner as a portion where wiring is formed.

  Next, the wiring layer 12 is grown according to the resist pattern 14 (FIG. 5 (r)). In this embodiment, it is assumed that the electroplating is performed as in the case where the conductive layer 6 is formed on the glass substrate 1, but the present invention is not particularly limited thereto. However, since this step is intended to form the conductive layer 11 by embedding a conductive material in the connection hole 9 provided in the interlayer insulating layer 8 in addition to the wiring pattern, the plating solution in the case of performing electrolytic plating, The plating conditions are selected according to so-called filled plating conditions so that the inside of the connection hole 9 is completely filled with the wiring layer 12.

  Next, the resist pattern 14 is removed (FIG. 6 (s)), and then the conductive seed layer 10 without the wiring layer 12 thereon is removed (FIG. 6 (t)). In this description, it is assumed that selective etching is performed as in the case of forming a conductor pattern on the glass substrate 1, but the present invention is not particularly limited to this.

  In FIG. 6 (t), a structure in which a single interlayer insulating layer 8 and a wiring layer 12 are provided on the front and back surfaces of the glass substrate 1, respectively, is described. The process of forming the wiring layer 12 may be repeated from the process of forming the insulating layer 8.

  Finally, plating is performed on a predetermined portion of the wiring layer 12 to form a plating layer 15 in order to connect to a semiconductor element, a printed wiring board, or the like by wire bonding, solder ball connection, or the like (FIG. 6 ( u)). The type of plating is not particularly limited, and may be appropriately selected from Au, silver, nickel, palladium, tin, zinc, an alloy thereof, a laminated structure thereof, or the like according to the application. When it is better to mask a part of the outermost layer at the time of subsequent connection, a solder resist layer may be provided further above the outermost layer. Thus, the multilayer wiring board 110 is completed.

  Examples based on the embodiments of the present invention will be described below.

<Example 1>
A non-alkali glass having a thickness of 400 μm and a diameter of 300 mm is prepared as the glass substrate 1 (FIG. 4A). As shown in FIG. 4B, a through hole 2 having a diameter of 100 μm is obtained by laser processing from both sides. It was provided in the position. Subsequently, as shown in FIGS. 4C and 4D, the conductive seed layer 3 having a thickness of 0.05 μm and 0.3 μm, respectively, in the order of titanium and copper by sputtering on both sides of each side, 4 was formed. Further, as shown in FIG. 4E, a nickel layer was laminated to a thickness of 0.3 μm by an electroless plating process. At this time, liquid agitation and a liquid jet were used so that the liquid also reached the inside of the through hole 2 and was laminated on the inner wall. Subsequently, copper was laminated with a thickness of 10 μm in an electrolytic copper plating process.

  In the steps so far, the lamination of the conductive layer 5 on the side wall of the through hole 2 was completed, and then the insulating resin 7 was filled into the through hole 2 as shown in FIG. At the time of filling, a metal mask in which the through hole 2 part to be filled was opened was used to fill the hole filling ink as the insulating resin 7 by printing. As the ink, “PHP900IF10F” manufactured by Sanei Chemical Co., Ltd. was used. Printing was performed from one surface of the glass substrate 1 and was able to be filled without voids by vacuum suction from the opposite surface side. After the filling process, excess insulating resin 7 was scattered in islands on the front and back surfaces of the glass substrate 1.

  Next, as shown in FIG. 4G, the insulating resin 7 scattered on the front and back surfaces of the glass substrate 1, and the conductive layer 5 and the conductive seed layers 3 and 4 laminated thereunder are subjected to CMP processing. Removed. Processing was performed until the front and back surfaces of the glass substrate 1 were completely exposed. At this stage, CMP processing was performed so that the conductive seed layers 3 and 4, the conductive layer 5, and the insulating resin 7 exposed on the front and back surfaces of the glass substrate 1 were on the same plane as the front and back surfaces of the glass substrate 1.

  Next, as shown in FIG. 4 (h), the glass substrate 1 was etched by immersing the glass substrate 1 in a glass etching solution containing hydrofluoric acid as a main component. The target thickness for etching was set to 10 μm, and the removal thickness due to the immersion time was examined by preliminary experiments, and the processing conditions were set based on the result.

  Next, as shown in FIG. 4 (i), the exposed front and back surfaces of the glass substrate 1, the conductive seed layers 3, 4, the conductive layer 5, and the insulating resin 7 are subjected to the same sputtering treatment as the through hole 2, Conductive seed layers 3 and 4 made of a titanium layer and a copper layer were formed. Subsequently, as shown in FIG. 4 (j), a negative type dry film resist is laminated on both sides, exposed through a predetermined mask, developed, and subjected to a development process. An image was formed. Considering the thickness of the wiring layer 6 when the wiring is formed later by electrolytic plating, the thickness of the dry film resist is set to 25 μm. Subsequently, as shown in FIG. 5K, the wiring layer 6 was formed by electrolytic copper plating. The thickness of the wiring layer 6 was set to 15 μm as a target film thickness.

  Next, as shown in FIG. 5 (l), the dry film resist is peeled off by immersing the substrate in a peeling solution containing sodium hydroxide as a main component, and as shown in FIG. 5 (m). In addition, the sputtered copper layer of the conductive seed layer under the wiring negative pattern made of dry film resist was dissolved and removed by performing a treatment with an etching solution mainly composed of sulfuric acid and hydrogen peroxide solution for a short time. . Subsequently, the sputtered titanium layer was dissolved and removed with a titanium etching solution mainly composed of ammonium fluoride and hydrogen peroxide. Through the steps so far, the wiring layers 6 on the front and back surfaces of the glass substrate 1 are completed.

  By the way, when designing the pattern of the wiring layer 6 on the front and back surfaces of the glass substrate 1, in order to verify the connectivity between the conductive layer 5 in the through hole 2 and the wiring layer 6 on the front and back surfaces of the glass substrate 1, 2 is provided with a test pattern 17 provided with an electrode for continuity check in the vicinity of the end portion. FIG. 7 shows a plan view (FIG. 7A) and an enlarged view (FIG. 7B) of the glass wafer showing the arrangement of the test pattern 17, and FIG. 8 shows a cross-sectional view (upper side) of the test pattern 17. Figure) and a plan view (lower view) are shown. As shown in FIG. 7A, 100 test patterns 17 were provided at five locations on the glass wafer, respectively (FIG. 7B). As shown in FIG. 8, each test pattern 17 is composed of a pad 18 on the conductive layer 5 formed in the wiring layer, a pad 20 with which a measurement terminal is brought into contact, and a wiring 19 between them. Before proceeding to, all continuity checks were performed with a hand tester.

  Subsequently, as shown in FIG. 5 (n), an interlayer insulating layer 8 was laminated on both surfaces of the substrate. Specifically, an interlayer insulating film “ABF-GX13” (thickness 25 μm) manufactured by Ajinomoto Fine Techno Co. was laminated on both surfaces. Next, as shown in FIG. 5 (o), connection holes 9 were formed on the interlayer insulating layer 8 by laser processing. The connection hole 9 was formed in accordance with a predetermined position of the wiring layer 6 on the front and back surfaces of the glass substrate 1, and then a desmear process for removing processing residues was performed.

  Subsequently, as shown in FIG. 5 (p), the wiring layer 12 formed on the interlayer insulating layer 8 and the seed layer 10 for the conductive layer 11 inside the connection hole 9 provided in the interlayer insulating layer 8 are not used. An electrolytic copper plating layer was formed (see FIG. 5 (r)). Next, as shown in FIG. 5 (q), a dry film resist was affixed on both sides, exposed through a predetermined mask, and developed to form a wiring negative pattern. Subsequently, as shown in FIG. 5 (r), the wiring layer 12 is laminated by electrolytic copper plating, and subsequently, as shown in FIG. 6 (s), the dry film resist is peeled and removed. Further, as shown in FIG. 6 (t), the electroless copper plating layer as the electrolytic seed layer was dissolved and removed by flash etching. Thus, the formation of the wiring layer 12 on the interlayer insulating layer 8 was completed.

  Finally, as shown in FIG. 6 (u), the outermost wiring layer 12 was plated to form a plating layer 15. Specifically, nickel 5 μm, palladium 0.05 μm, and gold 0.1 μm were laminated in this order by electroless plating. Thus, the production of the multilayer wiring board 110 is completed.

<Comparative Example 1>
As shown in FIG. 4G, after the front and back surfaces of the glass substrate 1 are exposed by CMP, the glass substrate 1 is not etched with the glass etching solution as shown in FIG. A multilayer wiring board was produced by the same method as in Example 1 except that.

  About the multilayer wiring board of Example 1 and Comparative Example 1, after wiring directly on the front and back surfaces of the glass substrate 1, the connection between the conductive layer 5 and the wiring layer 6 of the glass substrate 1 was checked. Specifically, the continuity of the pads 20 in the wiring layer 6 connected to both ends of the conductive layer 5 was checked with a tester “3540 mΩ HiTESTER” manufactured by Hioki Electric Co., Ltd. As the timing of the continuity check, it is performed in a room temperature environment immediately after the production of the substrate, or after cold storage (-55 ° C, 15 minutes → 25 ° C, 5 minutes → 120 ° C, 15 minutes → 25 ° C, 5 minutes 1 Cycle, which was repeated 1000 cycles). In the pass / fail judgment, when the resistance value between the pads indicates less than 1Ω and indicates 1Ω or more, the connection is regarded as having a problem and is rejected. The measurement results are shown in Table 1. In Example 1, there were none that failed at each of the 100 test locations in one glass wafer, whereas in Comparative Example 1, those that failed even after fabrication appeared. However, after the cooling test, some of the test points failed.

  As described above, according to the present invention, it is possible to provide a wiring substrate having high reliability in connection between the conductive layer in the glass substrate and the wiring layer on the glass surface, and thus high reliability as a whole. .

  ADVANTAGE OF THE INVENTION According to this invention, the utilization as a manufacturing method of the interposer which can respond | correspond to the high performance and high speed of the electronic device in 3D mounting or 2.5D mounting is attained.

1 Glass substrate 2 Through hole 3 Conductive seed layer (inside glass substrate)
4 Conductive seed layer (inside glass substrate)
5 Conductive layer (inside glass substrate)
6 Wiring layer (Glass substrate front and back)
7 Insulating resin 8 Interlayer insulating layer 9 Connection hole 10 Conductive seed layer (on interlayer insulating layer)
11 Conductive layer (inside the interlayer insulating layer)
12 Wiring layer (on interlayer insulation layer)
13 Resist pattern (on glass substrate)
14 Resist pattern (on interlayer insulating layer)
15 Plating layer 16 Step 17 Test pattern 18 Pad on conductive layer 19 Wiring between pads 20 Pad 30 Conductive seed layer (front and back surfaces of glass substrate)
100, 200 Wiring board 110, 210 Multilayer wiring board

Claims (3)

A wiring board having a through hole for electrically connecting a wiring layer formed on the front and back surfaces of the glass substrate,
The inner wall surface of the through hole is provided with a conductive seed layer and a conductive layer,
The inside of the conductive layer is filled with an insulating material,
The through holes on the front and back surfaces of the glass substrate are provided with protrusions extending from the inner wall surface of the through holes,
At least a conductive layer and a conductive seed layer are provided on the side surface of the protrusion, and a wiring layer is provided on the top of the protrusion facing the front and back surfaces of the glass substrate via the conductive seed layer. A wiring board characterized by.   A multilayer wiring board comprising a buildup layer on one side or both sides of the wiring board according to claim 1. Providing a through hole in the glass substrate;
Providing a conductive seed layer and a conductive layer in this order on the front and back surfaces of the glass substrate and the inner wall of the through hole;
Filling the through hole with an insulating material;
A step of exposing the glass surface by removing the insulating substance, the conductive seed layer, and the conductive layer attached to the front and back surfaces of the glass substrate;
Etching and removing the glass on the front and back surfaces of the glass substrate to reduce the thickness by a predetermined dimension;
Providing a conductive seed layer on the front and back surfaces of the glass substrate;
Providing a resist pattern comprising a negative pattern of the wiring pattern to be formed on the surface of the conductive seed layer;
And a step of providing a wiring layer on a conductive seed layer on which no resist pattern is formed.