JPH0546998B2 - - Google Patents
Info
- Publication number
- JPH0546998B2 JPH0546998B2 JP61089219A JP8921986A JPH0546998B2 JP H0546998 B2 JPH0546998 B2 JP H0546998B2 JP 61089219 A JP61089219 A JP 61089219A JP 8921986 A JP8921986 A JP 8921986A JP H0546998 B2 JPH0546998 B2 JP H0546998B2
- Authority
- JP
- Japan
- Prior art keywords
- polyimide film
- insulating layer
- filler
- layers
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920001721 polyimide Polymers 0.000 claims description 40
- 239000010410 layer Substances 0.000 claims description 39
- 239000000945 filler Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 6
- 238000007689 inspection Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000032798 delamination Effects 0.000 description 3
- 230000000704 physical effect Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- NWZSZGALRFJKBT-KNIFDHDWSA-N (2s)-2,6-diaminohexanoic acid;(2s)-2-hydroxybutanedioic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O.NCCCC[C@H](N)C(O)=O NWZSZGALRFJKBT-KNIFDHDWSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- IKDUDTNKRLTJSI-UHFFFAOYSA-N hydrazine monohydrate Substances O.NN IKDUDTNKRLTJSI-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はコンピユータ等の電子機器に使用され
る大規模集積回路（LSI）実装用多層配線基板の
層間絶縁層の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an interlayer insulating layer of a multilayer wiring board for mounting a large-scale integrated circuit (LSI) used in electronic devices such as computers.
従来、この種の多層配線基板の層間絶縁層に
は、第２図又は第３図に示されるように、通常の
ポリイミド膜のみ又はフイラーポリイミド膜のみ
から成る有機絶縁層が使用されており、電気的絶
縁性および表面凹凸の平坦化のために２層以上繰
返し形成されていた。
Conventionally, as shown in FIG. 2 or 3, an organic insulating layer consisting only of a normal polyimide film or only a filler polyimide film has been used for the interlayer insulating layer of this type of multilayer wiring board. Two or more layers were repeatedly formed for physical insulation and flattening of surface irregularities.
第２図を参照すると、基板１と下層配線パター
ン２の表面に通常のポリイミド膜３が２層形成さ
れている。このポリイミド膜３の厚さは１層当り
５〜10μである。この場合、２層形成すると、膜
厚は10〜20μとなるが、透明度が大きいため、表
面からポリイミド膜３を通して下層配線パターン
が透過して見え、検査、チエツクが容易である。 Referring to FIG. 2, two layers of ordinary polyimide films 3 are formed on the surfaces of the substrate 1 and the lower wiring pattern 2. As shown in FIG. The thickness of this polyimide film 3 is 5 to 10 μm per layer. In this case, if two layers are formed, the film thickness will be 10 to 20 μm, but since the transparency is high, the lower layer wiring pattern can be seen through the polyimide film 3 from the surface, making inspection and checking easy.
第３図を参照すると、基板１と下層配線パター
ン２の表面にSiO2などが含まれ耐クラツク性に
すぐれているフイラーポリイミド膜４が２層形成
されている。フイラーポリイミド膜４は機械的強
度が強いため、クラツク不良が激減する。 Referring to FIG. 3, two layers of a filler polyimide film 4 containing SiO 2 and the like and having excellent crack resistance are formed on the surfaces of the substrate 1 and the lower wiring pattern 2. Since the filler polyimide film 4 has high mechanical strength, crack defects are drastically reduced.
第５図ａ〜ｅを参照すると、第２図の絶縁層の
構造の従来の製造方法が示されている。先ず、基
板１上に下層配線パターン２が形成される（第５
図ａ）。この表面に、通常のポリイミド膜３を２
層、スピンコート等により全面塗布し、乾燥、キ
ユアさせる（第５図ｂ）。次に、キユアしたポリ
イミド膜３表面にフオトレジスト５を塗布し、図
示しないガラスマスクを通して紫外線露光し、フ
オトレジスト５をパターン化する（第５図ｃ）。
次に、ヒドラジンヒドラート系溶剤によるウエツ
トエツチングかあるいはCF4ガス等によるドライ
エツチングにより、フオトレジスト５をマスクに
してポリイミド膜３をエツチングする（第５図
ｄ）。最後に、フオトレジスト５を剥離する（第
５図ｅ）。 Referring to FIGS. 5a-5e, a conventional method of manufacturing the insulating layer structure of FIG. 2 is illustrated. First, the lower wiring pattern 2 is formed on the substrate 1 (fifth
Diagram a). Two layers of ordinary polyimide film 3 are applied to this surface.
It is coated over the entire surface by layering, spin coating, etc., and dried and cured (Figure 5b). Next, a photoresist 5 is applied to the surface of the cured polyimide film 3 and exposed to ultraviolet light through a glass mask (not shown) to pattern the photoresist 5 (FIG. 5c).
Next, the polyimide film 3 is etched using the photoresist 5 as a mask by wet etching using a hydrazine hydrate solvent or dry etching using CF 4 gas or the like (FIG. 5d). Finally, the photoresist 5 is peeled off (FIG. 5e).
又、第５図ａ〜ｅ中のポリイミド膜３の代りに
フイラーポリイミド膜４を使用することにより、
第３図の絶縁層の構造が製造できる。 Also, by using filler polyimide film 4 instead of polyimide film 3 in FIGS. 5a to 5e,
The structure of the insulating layer shown in FIG. 3 can be manufactured.
しかしながら、第２図のように、通常のポリイ
ミド膜３のみで２層以上形成したものでは、熱ス
トレスや吸湿のために内部にクラツクが生じやす
く、第３図のようにSiO2などが含まれたフイラ
ーポリイミド膜４のみで２層以上形成すると、フ
イラーSiO2のために膜の透明度が著しく悪くな
り、表面からフイラーポリイミド膜４を通して下
層配線パターン２が見えなくなつてしまい、検
査、チエツクが不可能となる欠点がある。又、第
５図ａ〜ｅに示したような、従来の製造方法で
は、製造工程が複雑となる欠点がある。
However, as shown in Fig. 2, when two or more layers are formed using only the ordinary polyimide film 3, cracks tend to occur internally due to heat stress and moisture absorption, and as shown in Fig. 3, SiO 2 etc. are included. If two or more layers are formed using filler polyimide film 4 alone, the transparency of the film will deteriorate significantly due to the filler SiO 2 , and the lower wiring pattern 2 will no longer be visible through filler polyimide film 4 from the surface, making inspection and checking impossible. There are possible drawbacks. Further, the conventional manufacturing method as shown in FIGS. 5a to 5e has the disadvantage that the manufacturing process is complicated.
また、ポリイミドとガラス系の２層からなる絶
縁層の構造も知られている（例えば、特開昭55−
105399号公報参照）。しかしながら、このような
ガラス系（無機材料）とポリイミド（有機材料）
とを併用した構造では、２つの材料間の物理的特
性の違いに起因する歪あるいは層間剥離が生じや
すいなど、多層基板の品質、信頼性に劣るという
欠点がある。 In addition, an insulating layer structure consisting of two layers of polyimide and glass is also known (for example,
(See Publication No. 105399). However, such glass-based (inorganic materials) and polyimide (organic materials)
A structure using both materials has the disadvantage that the quality and reliability of the multilayer board are poor, such as distortion or delamination likely to occur due to the difference in physical properties between the two materials.
したがつて、本発明の目的は、絶縁性、検査、
チエツク性および耐クラツク性に優れた、絶縁層
の構造を提供することにある。 Therefore, the object of the present invention is to improve insulation, inspection,
The object of the present invention is to provide an insulating layer structure with excellent checkability and crack resistance.
本発明の他の目的は、層間の物理的特性の相違
が緩和され、歪、層間剥離等が生じにくい、絶縁
層の構造を提供することにある。 Another object of the present invention is to provide an insulating layer structure in which differences in physical properties between layers are alleviated and distortion, delamination, etc. are less likely to occur.
本発明による絶縁層の構造は、多層配線基板の
層間絶縁層が、ポリイミド膜とフイラーポリイミ
ド膜との組合せ構造を有することを特徴とする。
The structure of the insulating layer according to the present invention is characterized in that the interlayer insulating layer of the multilayer wiring board has a combination structure of a polyimide film and a filler polyimide film.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
第１図を参照すると、基板１と下層配線パター
ン２の表面に、第１層目として通常のポリイミド
膜３が、そして第２層目にSiO2を含むフイラー
ポリイミド膜４が重ねて形成されている。このよ
うな構造によると、絶縁性、検査、チエツクおよ
び耐クラツク性にすぐれた層間絶縁層が形成可能
となる。 Referring to FIG. 1, a normal polyimide film 3 is formed as a first layer on the surfaces of a substrate 1 and a lower wiring pattern 2, and a filler polyimide film 4 containing SiO 2 is formed as a second layer. There is. With such a structure, it is possible to form an interlayer insulating layer with excellent insulation properties, inspection, check, and crack resistance.
なお、上記実施例では、第１層目に通常のポリ
イミド膜３を、第２層目にフイラーポリイミド膜
４を形成しているが、第１層目にフイラーポリイ
ミド膜４を、第２層目に通常のポリイミド膜３を
形成しても良い。但し、この方が上記実施例に比
べ耐クラツク性が若干悪くなる。 In the above embodiment, the ordinary polyimide film 3 is formed in the first layer and the filler polyimide film 4 is formed in the second layer. A normal polyimide film 3 may be formed on the surface. However, the crack resistance is slightly worse in this case than in the above embodiment.
第４図ａ〜ｅを参照すると、第１図の絶縁層の
構造の一製造方法が示されている。先ず、第５図
ａと同様に、基板１上に下層配線パターン２が形
成される（第４図ａ）。この表面全面に、感光性
ポリイミド膜３′及び感光性フイラーポリイミド
膜４′をコーテイング、低温乾燥する（第４図
ｂ）。従つて、この状態では、感光性ポリイミド
膜３′及び感光性フイラーポリイミド膜４′はイミ
ド化していない。次にガラスマスク１０を通して
紫外線露光する（第４図ｃ）。次に、現像すると、
紫外線が照射されなかつた部分が除去される（第
４図ｄ）。最後に、上記乾燥状態のイミド化され
ていないポリイミド膜３及びフイラーポリイミド
膜４をキユアしてイミド化させる（第４図ｅ）。 Referring to FIGS. 4a-4e, one method of manufacturing the structure of the insulating layer of FIG. 1 is illustrated. First, similar to FIG. 5a, the lower wiring pattern 2 is formed on the substrate 1 (FIG. 4a). The entire surface is coated with a photosensitive polyimide film 3' and a photosensitive filler polyimide film 4' and dried at low temperature (FIG. 4b). Therefore, in this state, the photosensitive polyimide film 3' and the photosensitive filler polyimide film 4' are not imidized. Next, it is exposed to ultraviolet light through a glass mask 10 (FIG. 4c). Next, when developed,
The portions that were not irradiated with ultraviolet light are removed (FIG. 4d). Finally, the dry unimidized polyimide film 3 and filler polyimide film 4 are cured and imidized (FIG. 4e).
このように、本実施例の製造方法（第４図ａ〜
ｅ）は、従来の製造方法（第５図ａ〜ｅ）に比較
して、製造工程が簡単となる。 In this way, the manufacturing method of this example (Fig. 4 a to
In e), the manufacturing process is simpler than the conventional manufacturing method (FIGS. 5a to 5e).
以上の説明で明らかなように、本発明によれ
ば、多層配線基板の層間絶縁層の構造を、通常の
ポリイミド膜とフイラーポリイミド膜との組合せ
構造とすることにより、絶縁性、検査、チエツク
性および耐クラツク性に優れた層間絶縁層を形成
できる。また、層間絶縁層に通常のポリイミド膜
とフイラーポリイミド膜とから成る同じポリイミ
ド系樹脂を使用しているので、層間の物理的特性
の相違が緩和され、歪、層間剥離等が生じにくい
という利点もある。
As is clear from the above explanation, according to the present invention, the structure of the interlayer insulating layer of the multilayer wiring board is a combination structure of a normal polyimide film and a filler polyimide film, thereby improving insulation properties, inspection, and checkability. Also, an interlayer insulating layer with excellent crack resistance can be formed. In addition, since the same polyimide resin consisting of a normal polyimide film and a filler polyimide film is used for the interlayer insulating layer, differences in physical properties between the layers are alleviated, and there is an advantage that distortion, delamination, etc. are less likely to occur. be.
第１図は本発明による絶縁層の構造の一実施例
を示した断面図、第２図は従来の絶縁層の構造の
一例を示した断面図、第３図は従来の絶縁層の構
造の他の一例を示した断面図、第４図ａ〜ｅは第
１図の絶縁層の構造の一製造方法を示した断面
図、第５図は第２図の絶縁層の構造の従来の製造
方法を示した断面図である。
１……基板、２……配線パターン、３……通常
のポリイミド膜、４……フイラーポリイミド膜。
FIG. 1 is a cross-sectional view showing an example of the insulating layer structure according to the present invention, FIG. 2 is a cross-sectional view showing an example of the conventional insulating layer structure, and FIG. 3 is a cross-sectional view showing an example of the conventional insulating layer structure. 4a to 4e are cross-sectional views showing one manufacturing method of the insulating layer structure of FIG. 1, and FIG. 5 is a conventional manufacturing method of the insulating layer structure of FIG. 2. FIG. 3 is a cross-sectional view showing the method. 1...Substrate, 2...Wiring pattern, 3...Ordinary polyimide film, 4...Filler polyimide film.
Claims (1)
とフイラーポリイミド膜との組合せ構造を有する
ことを特徴とする絶縁層の構造。 ２ 上記フイラーポリイミド膜のフイラー成分が
SiO2である特許請求の範囲第１項記載の絶縁層
の構造。[Scope of Claims] 1. An insulating layer structure characterized in that an interlayer insulating layer of a multilayer wiring board has a combination structure of a polyimide film and a filler polyimide film. 2 The filler component of the filler polyimide film mentioned above is
The structure of the insulating layer according to claim 1, which is SiO2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8921986A JPS62247597A (en) | 1986-04-19 | 1986-04-19 | Structure of insulating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8921986A JPS62247597A (en) | 1986-04-19 | 1986-04-19 | Structure of insulating layer |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP231793A Division JPH0831696B2 (en) | 1993-01-11 | 1993-01-11 | Structure of insulating layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62247597A JPS62247597A (en) | 1987-10-28 |
| JPH0546998B2 true JPH0546998B2 (en) | 1993-07-15 |
Family
ID=13964614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8921986A Granted JPS62247597A (en) | 1986-04-19 | 1986-04-19 | Structure of insulating layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62247597A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101525664B1 (en) * | 2013-06-12 | 2015-06-03 | 현대중공업 주식회사 | A treatment System of Liquefied Gas and A Method for the same |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2517369B2 (en) * | 1988-10-06 | 1996-07-24 | イビデン株式会社 | Method for manufacturing multilayer wiring board |
| JP2803684B2 (en) * | 1990-03-27 | 1998-09-24 | 富士通株式会社 | Circuit board |
| JPH04103196A (en) * | 1990-08-23 | 1992-04-06 | Nec Corp | Coating method of high density multilayer wiring board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52149358A (en) * | 1976-06-08 | 1977-12-12 | Fujitsu Ltd | Multilayer wiring method |
| JPS55105399A (en) * | 1979-02-08 | 1980-08-12 | Cho Lsi Gijutsu Kenkyu Kumiai | Multilayer wired circuit board |
-
1986
- 1986-04-19 JP JP8921986A patent/JPS62247597A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52149358A (en) * | 1976-06-08 | 1977-12-12 | Fujitsu Ltd | Multilayer wiring method |
| JPS55105399A (en) * | 1979-02-08 | 1980-08-12 | Cho Lsi Gijutsu Kenkyu Kumiai | Multilayer wired circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101525664B1 (en) * | 2013-06-12 | 2015-06-03 | 현대중공업 주식회사 | A treatment System of Liquefied Gas and A Method for the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62247597A (en) | 1987-10-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |