JPS6234159B2 - - Google Patents
Info
- Publication number
- JPS6234159B2 JPS6234159B2 JP1357279A JP1357279A JPS6234159B2 JP S6234159 B2 JPS6234159 B2 JP S6234159B2 JP 1357279 A JP1357279 A JP 1357279A JP 1357279 A JP1357279 A JP 1357279A JP S6234159 B2 JPS6234159 B2 JP S6234159B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- insulating
- insulating film
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920001721 polyimide Polymers 0.000 claims description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 229920006015 heat resistant resin Polymers 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 30
- 239000009719 polyimide resin Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は多層配線回路基板にかかり、とくに
LSIパツケージ用の多層配線回路基板の構造に関
する。[Detailed Description of the Invention] The present invention relates to a multilayer wiring circuit board, and particularly relates to a multilayer wiring circuit board.
Concerning the structure of multilayer wiring circuit boards for LSI packages.
従来、ICやLSIを搭載するためのLSIパツケー
ジ用多層配線回路基板に用いられる絶縁層は
Al2O3，SiO2，CaOなどの無機ガラス系物質より
なるものが主であつた。これは、いわゆる絶縁ペ
ーストという形で提供されたものを、スクリーン
印刷で基板上に塗布し、乾燥、焼成工程により、
絶縁層膜が形成されるもので、プロセス的に容易
であること、厚い絶縁層膜が形成出来ることなど
の特長を有している。しかし、形成された絶縁層
膜はポーラスであり、ピンホールが多く、上下の
導体層のシヨートを防ぐには20〜40μｍの膜厚が
必要である。一方、絶縁層膜材料としてポリイミ
ド系樹脂を用いる方法もある。これは樹脂溶液を
スピンナー等を用いて基板上に塗布し、そのあと
キユアすることにより形成される。得られた膜は
ピンホールが少なく、数μｍの厚さで十分良好な
絶縁性をする。しかし、数十μｍの厚さに厚付け
することは不向きである。これは、信号線と電
源、グランド間の電気容量を小さくしたい場合に
は問題となる。また、樹脂と金属導体との密着強
度も、アルミナ等の無機ガラス系物質と、金属導
体との密着強度と比較すると弱く、特にこの樹脂
上に、ボンデイング用のパツドなどを形成するこ
とはなかなか困難である。 Conventionally, the insulating layer used in multilayer wiring circuit boards for LSI packages to mount ICs and LSIs is
They were mainly made of inorganic glass-based materials such as Al 2 O 3 , SiO 2 , and CaO. This is provided in the form of a so-called insulating paste, which is applied onto a substrate by screen printing, and then dried and fired through a process of drying and baking.
It forms an insulating layer, and has the advantages of being easy to process and being able to form a thick insulating layer. However, the formed insulating layer film is porous and has many pinholes, and a film thickness of 20 to 40 μm is required to prevent the upper and lower conductor layers from being shot. On the other hand, there is also a method of using polyimide resin as the insulating layer material. This is formed by applying a resin solution onto a substrate using a spinner or the like, and then curing it. The resulting film has few pinholes and has sufficiently good insulating properties with a thickness of several μm. However, it is not suitable to increase the thickness to several tens of μm. This becomes a problem when it is desired to reduce the capacitance between the signal line, power supply, and ground. Additionally, the adhesion strength between a resin and a metal conductor is weak compared to the adhesion strength between an inorganic glass-based material such as alumina and a metal conductor, and it is particularly difficult to form bonding pads on this resin. It is.
本発明の目的は上記従来技術の欠点を除去して
有効な多層配線回路基板を提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide an effective multilayer wiring circuit board.
本発明は絶縁層膜として、アルミナを主成分と
した無機ガラス系物質と、ポリイミド系耐熱樹脂
の二層構成をとることにある。アルミナとポリイ
ミド系樹脂の密着は良好であり、絶縁膜として信
頼性のある二層構成が可能である。これにより、
ピンホールがなく、そして信号線電気容量を小さ
くするだけの適当な厚みのある絶縁膜が得られ
る。又、金属導体との密着が必要とされる部分の
み、ポリイミド樹脂をとりのぞいた窓あき構造に
することによりボンデイングパツドなどを形成す
ることも出来る。 The present invention has a two-layer structure for the insulating layer film, consisting of an inorganic glass-based material containing alumina as a main component and a polyimide-based heat-resistant resin. The adhesion between alumina and polyimide resin is good, and a reliable two-layer structure is possible as an insulating film. This results in
An insulating film without pinholes and having an appropriate thickness to reduce signal line capacitance can be obtained. Furthermore, a bonding pad or the like can be formed by forming a window-perforated structure by removing the polyimide resin only in the portion where close contact with the metal conductor is required.
すなわち本発明は、セラミツク基板上に形成さ
れた多層配線回路基板において、所定の絶縁層膜
がアルミナを主成分とする無機ガラス系物質から
なる第１の絶縁膜と、ポリイミド系樹脂からなる
第２の絶縁膜との二層構成よりなることを特徴と
する。 That is, the present invention provides a multilayer wiring circuit board formed on a ceramic substrate, in which a predetermined insulating layer film includes a first insulating film made of an inorganic glass-based material containing alumina as a main component, and a second insulating film made of a polyimide-based resin. It is characterized by having a two-layer structure with an insulating film.
次に、本発明の実施例について図面を参照して
説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明が適用されたLSIパツケージ用
多層配線回路基板の縦断側面図を示す。同図にお
いて耐熱性絶縁基板であるアルミナ基板１の上面
には第１配線信号層２、第１絶縁層３、第２配線
信号層４が形成されている。そして、これら配線
信号層と回路基板表層に形成されている電源層８
との間に二層構成絶縁層７が形成されている。二
層構成絶縁層７は、アルミナを主成分とする無機
ガラス絶縁膜５と、ポリイミド系樹脂膜６よりな
る。又、表層にはLSI用のチツプボンデイングパ
ツド１０や、リードボンデイングパツド９も形成
されているが、このように強い密着を必要とする
ものはポリイミド樹脂膜６に窓をあけ、直接（ア
ルミナ系）無機ガラス絶縁膜５と接着する構造を
とることにより密着性を保証している。 FIG. 1 shows a longitudinal sectional side view of a multilayer wiring circuit board for an LSI package to which the present invention is applied. In the figure, a first wiring signal layer 2, a first insulating layer 3, and a second wiring signal layer 4 are formed on the upper surface of an alumina substrate 1, which is a heat-resistant insulating substrate. Then, a power supply layer 8 formed on these wiring signal layers and the surface layer of the circuit board.
A two-layer insulating layer 7 is formed between the two layers. The two-layer insulating layer 7 is composed of an inorganic glass insulating film 5 containing alumina as a main component and a polyimide resin film 6. In addition, chip bonding pads 10 for LSI and lead bonding pads 9 are also formed on the surface layer, but for those that require strong adhesion, a window is opened in the polyimide resin film 6 and bonded directly (alumina). system) Adhesion is guaranteed by adopting a structure in which it adheres to the inorganic glass insulating film 5.
本実施例では（アルミナ系）無機ガラス絶縁膜
５の膜厚は15〜20μｍポリイミド系樹脂６の膜厚
は３〜５μｍ、合計二層構成で18〜25μｍの膜厚
となつている。この構成でリーク電流を調べるこ
とにより、ピンホールはほとんど０であることが
わかる。無機ガラス系絶縁膜だけで、これと同等
の絶縁性を得るためには、50〜60μｍ以上の膜厚
が必要となる。 In this embodiment, the thickness of the (alumina-based) inorganic glass insulating film 5 is 15 to 20 μm, the thickness of the polyimide resin 6 is 3 to 5 μm, and the total thickness of the two-layer structure is 18 to 25 μm. By examining the leakage current in this configuration, it is found that there are almost no pinholes. In order to obtain the same insulation properties using only an inorganic glass insulating film, a film thickness of 50 to 60 μm or more is required.
また、本実施例では配線信号線の電気容量は、
約2PF／cmであり、この値を実現するのに、ポリ
イミド樹脂だけでは15〜20μｍの膜厚が必要であ
り、スピンナーによる塗布では、４〜６回に及ぶ
繰返し塗布が必要となる。 In addition, in this example, the electrical capacity of the wiring signal line is
This value is approximately 2PF/cm, and to achieve this value, a film thickness of 15 to 20 μm is required using polyimide resin alone, and repeated application of 4 to 6 times is required when coating with a spinner.
また、これだけの膜厚ではヴイアホールをあけ
るためのエツチングが非常に困難となる。さらに
ポリイミド樹脂上におけるボンデイングパツドの
密着性にも問題がある。 Furthermore, with such a film thickness, etching for making via holes becomes extremely difficult. Furthermore, there is a problem in the adhesion of the bonding pad onto the polyimide resin.
本発明は以上説明したように、所定の絶縁層膜
をアルミナを主成分とする無機ガラス系物質と、
ポリイミド系樹脂の二層構成で形成することによ
り、ピンホールがなく、信号線容量を小さくする
だけの厚みのある、そして、その上に密着よく金
属導体層を形成出来る絶縁膜を提供することが出
来る。 As explained above, the present invention includes a predetermined insulating layer film made of an inorganic glass-based material containing alumina as a main component;
By forming a two-layer structure of polyimide resin, it is possible to provide an insulating film that has no pinholes, is thick enough to reduce signal line capacitance, and allows a metal conductor layer to be formed on it with good adhesion. I can do it.
第１図は本発明が適用されたLSIパツケージ用
多層配線回路基板の縦断側面図である。
尚、図において、１……アルミナ基板、２……
第１配線信号層、３……第１絶縁層、４……第２
配線信号層、５……アルミナ系無機ガラス絶縁
膜、６……ポリイミド系樹脂膜、７……２層構成
絶縁膜、８……電源層、９……リードボンデイン
グパツド、１０……チツプボンデイングパツドで
ある。
FIG. 1 is a longitudinal sectional side view of a multilayer wiring circuit board for an LSI package to which the present invention is applied. In addition, in the figure, 1... alumina substrate, 2...
1st wiring signal layer, 3...first insulating layer, 4...second
Wiring signal layer, 5... Alumina-based inorganic glass insulating film, 6... Polyimide resin film, 7... Two-layer insulating film, 8... Power supply layer, 9... Lead bonding pad, 10... Chip bonding It's padded.
Claims (1)
を設けた多層配線回路基板において、前記絶縁層
膜がアルミナを主成分とする無機ガラス系物質か
らなる第１の絶縁膜と、ポリイミド系耐熱樹脂か
らなる第２の絶縁膜との二層を含むことを特徴と
する多層配線回路基板。1. In a multilayer wiring circuit board in which multilayer wiring is provided on a ceramic substrate via an insulating layer film, the insulating layer film is made of a first insulating film made of an inorganic glass-based material containing alumina as a main component and a polyimide-based heat-resistant resin. What is claimed is: 1. A multilayer wiring circuit board comprising a second insulating film and a second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1357279A JPS55105399A (en) | 1979-02-08 | 1979-02-08 | Multilayer wired circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1357279A JPS55105399A (en) | 1979-02-08 | 1979-02-08 | Multilayer wired circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55105399A JPS55105399A (en) | 1980-08-12 |
| JPS6234159B2 true JPS6234159B2 (en) | 1987-07-24 |
Family
ID=11836875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1357279A Granted JPS55105399A (en) | 1979-02-08 | 1979-02-08 | Multilayer wired circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55105399A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62119951A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Multilayer interconnection substrate |
| JPS62247597A (en) * | 1986-04-19 | 1987-10-28 | 日本電気株式会社 | Structure of insulating layer |
-
1979
- 1979-02-08 JP JP1357279A patent/JPS55105399A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55105399A (en) | 1980-08-12 |
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