JP3025560B2 - Ceramic wiring board and method of manufacturing the same - Google Patents

Ceramic wiring board and method of manufacturing the same

Info

Publication number
JP3025560B2
JP3025560B2 JP3238054A JP23805491A JP3025560B2 JP 3025560 B2 JP3025560 B2 JP 3025560B2 JP 3238054 A JP3238054 A JP 3238054A JP 23805491 A JP23805491 A JP 23805491A JP 3025560 B2 JP3025560 B2 JP 3025560B2
Authority
JP
Japan
Prior art keywords
substrate
ceramic
layer
wiring board
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3238054A
Other languages
Japanese (ja)
Other versions
JPH0574979A (en
Inventor
澄人 冨永
幸広 木村
Original Assignee
日本特殊陶業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本特殊陶業株式会社 filed Critical 日本特殊陶業株式会社
Priority to JP3238054A priority Critical patent/JP3025560B2/en
Publication of JPH0574979A publication Critical patent/JPH0574979A/en
Application granted granted Critical
Publication of JP3025560B2 publication Critical patent/JP3025560B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B60VEHICLES IN GENERAL
    • B60NSEATS SPECIALLY ADAPTED FOR VEHICLES; VEHICLE PASSENGER ACCOMMODATION NOT OTHERWISE PROVIDED FOR
    • B60N3/00Arrangements or adaptations of other passenger fittings, not otherwise provided for
    • B60N3/02Arrangements or adaptations of other passenger fittings, not otherwise provided for of hand grips or straps
    • B60N3/023Arrangements or adaptations of other passenger fittings, not otherwise provided for of hand grips or straps movable

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic wiring substrate used for, for example, a substrate on which a semiconductor is mounted and on which fine wiring is formed on the surface, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a ceramic substrate used for a semiconductor substrate or the like is provided with a via hole penetrating in the thickness direction of the substrate in order to establish conduction between an upper surface and a lower surface of the ceramic substrate. The via hole is a through-hole provided in the ceramic substrate filled with a conductive member such as tungsten.For example, when manufacturing a ceramic multilayer substrate by laminating a plurality of ceramic substrates, the upper and lower holes are formed. It is used for ensuring conduction of the substrate.

In such a semiconductor substrate, a large number of fine wirings are formed on the surface of the ceramic substrate together with the via holes. In order to provide these wirings, holes formed when the ceramic substrate is fired are formed. It is necessary to smooth the surface of the substrate by closing surface defects such as (voids).

For this reason, as a technique for smoothing the surface of a ceramic substrate, there has been proposed a technique for forming an inorganic coating layer by applying a coating agent such as silica sol or alkyl silicate to the substrate surface and baking the coating agent. See Japanese Unexamined Patent Publication No. Sho 62-105987). Also,
In addition to this coating agent, a technique for smoothing the surface of a ceramic substrate using a synthetic resin such as polyimide is known.

[0005]

However, in the above-described technique, there is a problem that it is not easy to smooth the surface of the ceramic substrate and to ensure conduction of via holes and the like exposed on the substrate surface. .

In other words, conventionally, a coating layer is formed by using an inorganic material on the surface of the ceramic substrate other than the via holes in order to ensure conduction in the via holes, for example. There is a problem that the work is not easy and takes much time. In addition, since via holes are generally small, there is also a problem that the coating around the via hole cannot be performed firmly without excess or shortage, and a problem that the coating layer spreads to the surface of the via hole and the conduction of the via hole cannot be sufficiently ensured. Had occurred.

In recent years, as another method, after coating the entire surface of a ceramic substrate, a photosensitive resin (resist) is applied, and the photosensitive resin is removed only in a via hole portion by so-called photolithography to form a coating layer. Although an etching technique has been developed, an etching process using this light is not always easy because it usually requires many processing steps such as coating and cleaning. When the coating layer is formed using a synthetic resin, there is another problem that the coating layer is weak to heat.

The present invention has been made to solve the above-mentioned problems, and a ceramic wiring board capable of forming a smooth coating layer having excellent heat resistance on a substrate surface by a simple manufacturing process and sufficiently securing conduction of via holes and the like. And a method for producing the same.

[0009]

In order to achieve the above object, an invention according to claim 1 is an electroless plating layer in which a via hole provided in a ceramic substrate is exposed on the substrate surface.
Provided with a surface conductive layer that is summarized as ceramic wiring board characterized by comprising a coating layer made of an inorganic material on the surface of the ceramic substrate other than the surface conductive layer.

According to a second aspect of the present invention, a ceramic substrate is provided with a conductive portion exposed on the substrate surface, and a surface conductive layer is formed on the surface of the conductive portion by electroless plating .
Next, a sol or / and solution of an inorganic material is applied to cover the ceramic substrate and the surface conductive layer, then dried and fired to form a coating layer, and then the coating layer on the surface conductive layer is removed to remove the surface layer. A method for manufacturing a ceramic wiring board, characterized by exposing a conductive layer to ensure electrical continuity.

Here, as the ceramic substrate, a substrate made of alumina, mullite, aluminum nitride or the like can be used. Examples of the conductive portion include a via hole that penetrates the upper and lower surfaces of the ceramic substrate to ensure conduction.

The surface conductive layer is formed by electroless plating.
The formed conductive film is made of , for example, Ni, Cu, Au, Pt, or the like. Examples of the inorganic material include SiO 2 and Al 2 O 3 materials, and a sol or solution of the material may be used alone or as a mixture thereof. In addition, as the solution, for example, an alkoxide or the like can be used.

As a method of applying a liquid material such as a sol or a solution, for example, there is a so-called immersion method in which a substrate is immersed in the liquid material and then pulled up, or a so-called spinner method in which the substrate is fixed on a rotating body and the liquid material is dropped on the substrate surface. And other methods using a spray, a roll, a brush and the like.

The firing temperature is, for example, 800 to 150.
A range of 0 ° C. is preferable, and around 1000 ° C. is preferable. The thickness of the formed coating layer is preferably 1 μm or less, and the coating layer desirably makes the surface smooth and the voids 10 μm or less.

[0015] As a method of removing the coating layer,
Although not particularly limited, lap polishing or the like is preferable.

[0016]

According to the first aspect of the present invention, since the surface of the ceramic substrate is provided with a coating layer made of an inorganic material such as SiO 2 and / or Al 2 O 3 , voids and scratches on the surface are provided. Are smoothed by being covered with the coating layer, and fine wiring can be provided on the surface of the coating layer. At the same time, via hole Table Menshirube conductive layer is formed is an electroless plating layer exposed on the substrate surface, the and since the coating layer is not formed on the surface conductive layer, of the ceramic substrate via a via hole The conductivity of the upper and lower surfaces can be secured.

According to the second aspect of the present invention, in manufacturing the ceramic wiring board, first, a conductive portion exposed on the surface of the ceramic substrate is provided, and the surface of the conductive portion is electrolessly plated.
A surface conductive layer is formed with a pin . Next, a sol or / and solution of an inorganic material is applied so as to cover the ceramic substrate and the surface conductive layer, and then dried and fired to form a coating layer, thereby coating the entire ceramic substrate including the surface conduction portion. Next, only the coating layer on the surface conductive layer is removed by polishing or the like to expose the surface conductive layer, thereby ensuring conduction of the conductive portion.

That is, once the entire substrate is coated, only the necessary portion of the coating layer is removed, so that sufficient coating can be maintained and necessary conduction can be ensured.

[0019]

Next, embodiments of the ceramic wiring board and the method of manufacturing the same according to the present invention will be described. The ceramic wiring board of this embodiment has a large number of fine wirings formed on the surface thereof, and is used, for example, as a substrate on which a semiconductor is mounted.

As shown in FIG. 1 (A) and FIG. 1 (B) in which a part thereof is cut away and enlarged, the ceramic wiring board 1 of this embodiment is a 1.5 mm thick ceramic substrate 2 made of alumina. In addition, a large number of via holes 3 (0.25 mm diameter is 20
The ceramic substrate 2 has a coating made of SiO 2 and Al 2 O 3 having a thickness of 1 μm or less (for example, about 0.8 μm). Layer 4 is formed. The ceramic substrate 2 is obtained by baking and stacking four green sheets 10 (FIG. 2) as described later.

The via hole 3 is formed by filling a through hole 5 penetrating the upper and lower surfaces of the ceramic substrate with tungsten, which is a conductive material, in order to obtain conduction in the thickness direction of the ceramic substrate 2. 1.5μm thick
Ni plating layer 6 is formed. And this Ni
The coating layer 4 above the plating layer 6 has been removed to obtain continuity.

Next, a method for manufacturing the ceramic wiring board 1 will be described. First, as shown in FIG. 2A, a well-known green sheet 10 is formed using Al 2 O 3 as a main material by a doctor blade method. And FIG.
As shown in (B), a large number of through holes 5 penetrating the green sheet 10 in the thickness direction are formed.

Next, as shown in FIG.
Is filled with a tungsten paste to form a via hole 3 for ensuring conduction in the upper and lower surface directions of the ceramic substrate 2. Similarly, via holes 3 are further formed in three green sheets 10, and a tungsten paste is screen-printed on each of the green sheets 10 to form wirings 12 such as signal lines and power supply layers (FIG. 2).
(D)) is formed.

Thereafter, as shown in FIG. 2D, four layers of these green sheets 10 are laminated, cut into a 36 mm square outer diameter, and fired in a reducing atmosphere to obtain a ceramic substrate 2. Next, as shown in FIG. 2E, the exposed portion of the via hole 3 is subjected to electroless Ni plating,
The plating layer 6 is formed.

The entire surface of the ceramic substrate 2 including the surface of the Ni plating layer 6 is coated with 20 wt% Al 2
The O 3 sol and the 20 wt% SiO 2 sol are each coated to a thickness of about 1 μm by an immersion method. Next, as shown in FIG. 2 (F), the ceramic substrate 2 to which the coating agent has been applied is dried and then baked at 1000 ° C. to bake the coating agent to form a coating layer 4.

Finally, as shown in FIG. 2 (G), the coating layer 4 located on the Ni plating layer 6 is polished and removed, and the Ni plating layer 6 is exposed on the surface. Complete. The ceramic wiring board 1 manufactured in this manner has a smooth substrate surface without any large voids or defects, and is coated firmly around the Ni plating layer 6. In addition, since only the Ni plating layer 6 is disposed on the surface of the ceramic wiring substrate 1 in a state where the Ni plating layer 6 is exposed, conduction by the via hole 3 and the Ni plating layer 6 can be reliably obtained. There is an advantage that it is easy.

Furthermore, the method of the above-described embodiment has an excellent effect that the manufacturing process can be greatly simplified as compared with the conventional method, although sufficient coating can be performed and reliable conduction can be obtained. Next, an experimental example performed to confirm the effect of the present embodiment will be described. (Experimental Example 1) In this experimental example, in order to examine the smoothness of the surface of the ceramic multilayer substrate, samples Nos. 1 to 5 as shown in Table 1 below were manufactured, and the diameter of voids generated on the surface was measured. . In addition, the coating layer above the Ni plating layer was removed by polishing, the Ni plating layer was exposed, and the conduction between the upper surface and the lower surface of the via hole was measured. Table 1 shows the results.

[0028]

[Table 1]

As shown in Table 1, the sample No.
Samples Nos. 1 and 2 are preferable because the void diameter of the surface is small and the surface is smooth, but those of Sample No. 5 of the comparative example are not preferable because the void diameter is large and the surface is not smooth. In addition, the samples No. 1 and No. 2 of this example have a coating layer removed by polishing, so that conduction can be reliably obtained. However, the samples No. 3 and No. 4 of the comparative example are not polished. This is not preferable because conduction cannot be obtained. In Experimental Example 2 This experimental example, in order to examine in more detail the smoothness of the surface of the ceramic wiring board, as shown in FIG. 3, thin film of the Ta 2 N of 100μm angle to the surface of the substrate 20
Were formed (10 vertical × 10 horizontal), Au thin-film electrodes 21a and 21b were formed on both ends of the resistive thin film 20, and the resistance between the two thin-film electrodes 21a and 21b was measured. The results are shown in Table 2 below.

[0030]

[Table 2]

As shown in Table 2, the sample No.
Samples Nos. 6 and 7 are suitable because they have a smooth surface and thus have little variation in resistance value.
Since the surface is not smooth, there is a large variation in the resistance value, which is not preferable. (Experimental example 3) In this experimental example, in order to examine the smoothness of the surface of the ceramic wiring substrate in more detail, as shown in FIG. 4, a thin film wiring having a line width of 25 μm and 50 μm made of Ti / Cu + Ni + Au was formed on the surface of the substrate. Fifty pieces each of 30 and 31 were formed, and the conduction at both ends thereof and the occurrence of voids in the wirings 30 and 31 and defective shape were examined. The results are shown in Table 3 below.

[0032]

[Table 3]

As shown in Table 3, the sample No.
Samples Nos. 9 and 10 are preferable because the surface is smooth and no conduction failure and shape defect are observed. However, Sample No. 11 of the comparative example has a non-smooth surface and defects are observed in both wirings 30 and 31. Is not preferred.

It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be carried out in various modes within the scope of the present invention.

[0035]

As described in detail above, according to the first aspect of the present invention, the surface of the ceramic wiring board is smooth, free from large voids and defects, and is coated firmly around the surface conductive layer which is an electroless plating layer. There is an effect that a layer is formed. Further, since the surface conductive layer is exposed on the surface of the ceramic wiring substrate, there is an advantage that conduction can be reliably obtained and connection with the wiring is easy.

According to the invention of claim 2, electroless plating is performed.
By such a process, a ceramic wiring board having excellent smoothness of the substrate surface and high conductivity of the conductive portion as described in claim 1 can be easily manufactured in a simple process, and in particular, a via hole is provided. This is suitable when a large number of conductive portions such as are formed.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a ceramic wiring board of the present embodiment.

FIG. 2 is an explanatory view showing a procedure for manufacturing the ceramic wiring board of the present embodiment.

FIG. 3 is an explanatory diagram showing an experimental method of Experimental Example 2.

FIG. 4 is an explanatory view showing an experimental method of Experimental Example 3.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Ceramic wiring board 2 ... Ceramics substrate 3 ... Via hole 6 ... Ni plating layer 4 ... Coating layer

Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/15 H01L 23/12 H05K 3/28 H05K 3/46

Claims (2)

(57) [Claims]
1. A ceramic substrate comprising a surface conductive layer which is an electroless plating layer in which a via hole provided in the ceramic substrate is exposed on the surface of the substrate, and a coating layer made of an inorganic material on a surface of the ceramic substrate other than the surface conductive layer. A ceramic wiring board, comprising:
A conductive portion exposed on the surface of the ceramic substrate; and an electroless mesh formed on the surface of the conductive portion.
A surface conductive layer is formed by a coating, and then a sol or / and solution of an inorganic material is applied to cover the ceramic substrate and the surface conductive layer, and then dried and fired to form a coating layer. A method for manufacturing a ceramic wiring board, comprising: removing an upper coating layer to expose a surface conductive layer to ensure conduction.
JP3238054A 1991-09-18 1991-09-18 Ceramic wiring board and method of manufacturing the same Expired - Fee Related JP3025560B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3238054A JP3025560B2 (en) 1991-09-18 1991-09-18 Ceramic wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3238054A JP3025560B2 (en) 1991-09-18 1991-09-18 Ceramic wiring board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH0574979A JPH0574979A (en) 1993-03-26
JP3025560B2 true JP3025560B2 (en) 2000-03-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3025560B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4624754B2 (en) * 2003-09-29 2011-02-02 日本特殊陶業株式会社 Ceramic substrate for thin film electronic component, manufacturing method thereof, and thin film electronic component using the same
JP4690000B2 (en) * 2003-09-29 2011-06-01 日本特殊陶業株式会社 Ceramic substrate for thin film electronic component and thin film electronic component using the same
JP2005277385A (en) * 2004-02-27 2005-10-06 Tdk Corp Laminate chip inductor forming member and method of manufacturing laminate chip inductor comonent
JP5245989B2 (en) * 2009-03-31 2013-07-24 三菱マテリアル株式会社 Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink

Also Published As

Publication number Publication date
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