JPS6089996A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPS6089996A JPS6089996A JP19695583A JP19695583A JPS6089996A JP S6089996 A JPS6089996 A JP S6089996A JP 19695583 A JP19695583 A JP 19695583A JP 19695583 A JP19695583 A JP 19695583A JP S6089996 A JPS6089996 A JP S6089996A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resin
- conductor layer
- circuit conductor
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、産業用から一般民生用に至る広範な電子機器
に用いることができる多層回路基板に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multilayer circuit board that can be used in a wide variety of electronic devices ranging from industrial to general consumer use.
(従来例の構成とその問題点)
近年、VTRをはじめとする多くの電子機器はますます
小型、軽量化や高機能化を指向し、それとともに電子機
器を構成する電子回路の小型、高密度化が必要不可欠な
条件となってきている。このような状況の中で、電子回
路の高密度化を図る方策が種々講じられているが、とり
わけ電子回路を構成するための回路基板の多層化は重要
な課題となっている。(Conventional configurations and their problems) In recent years, many electronic devices such as VTRs have become smaller, lighter, and more highly functional. has become an indispensable condition. Under these circumstances, various measures have been taken to increase the density of electronic circuits, and in particular, increasing the number of layers of circuit boards for configuring electronic circuits has become an important issue.
従来から、多層回路基板はその目的に応じているいろな
タイプのものが用いられているが、その中でも代表的な
ものとして第1図に示すよう々多層回路基板があげられ
る。この多層回路基板は、主に回路ブロックのモジュー
ール基板として用いられるもので、次のように構成され
ている。第1図において、1はガラスエポキシなどの合
成樹脂やアルミナなどのセラミックスからなる絶縁基板
で、その表面に銅箔や銀糸の厚膜導体からなる第1の回
路導体層2が形成されている。そして、との第1の回路
導体層2が形成された絶縁基板1の表面が、ドライフィ
ルム化されたアクリル系樹脂からなる感光性樹脂層を露
光・現像して微細孔3を設けてなる層間絶縁層4で被覆
されていて、この層間絶縁層4」二に第2の回路導体層
5がアディティブ法などにより形成されている。なお、
第2の回路導体層5は、層間絶縁層4の微細孔3、いわ
ゆるピアホールを通して第1の回路導体層2に電気的に
接続されている。Conventionally, various types of multilayer circuit boards have been used depending on the purpose, and among them, a multilayer circuit board as shown in FIG. 1 is a typical one. This multilayer circuit board is mainly used as a module board for circuit blocks, and is configured as follows. In FIG. 1, reference numeral 1 denotes an insulating substrate made of synthetic resin such as glass epoxy or ceramics such as alumina, on the surface of which is formed a first circuit conductor layer 2 made of a thick film conductor such as copper foil or silver thread. The surface of the insulating substrate 1 on which the first circuit conductor layer 2 is formed is an interlayer formed by exposing and developing a photosensitive resin layer made of an acrylic resin formed into a dry film to provide micropores 3. It is covered with an insulating layer 4, and a second circuit conductor layer 5 is formed on this interlayer insulating layer 4 by an additive method or the like. In addition,
The second circuit conductor layer 5 is electrically connected to the first circuit conductor layer 2 through minute holes 3, so-called peer holes, in the interlayer insulating layer 4.
しかしながら、このような従来の多層回路基板では、層
間絶縁層4がアクリル系樹脂で形成されているために次
の」:うな欠点を有していた。即ち、層間絶縁層4と絶
縁基板1+に形成された第1の回路導体層2との密着性
が乏しいため、耐湿、温度ザイクルテストにおける層間
絶縁層4の信頼性が低かった。まだ、層間絶縁層4の熱
膨張係数が大きいため、熱衝撃テストにおいて層間絶縁
層4の剥離まだは絶縁基板1のクラックや割れ不良が生
じやすく、特に絶縁基板1に熱膨張係数の小さいセラミ
ックス基板を用いた場合、このような欠点が顕著になり
、セラミックス基板」−に抵抗体層を形成1−だ抵抗体
内蔵型の多層回路基板では、抵抗体層にもクラックなど
が生じるだめ、回路基板としての機能が果せなくなるこ
とがあった。さらに、層間絶縁層4の誘電率が太きいた
め、多層配線化する際に浮遊容量を考慮する必要があり
、回路投網の自由度が小さく々っでいた。However, such conventional multilayer circuit boards have the following drawbacks because the interlayer insulating layer 4 is made of acrylic resin. That is, since the adhesion between the interlayer insulating layer 4 and the first circuit conductor layer 2 formed on the insulating substrate 1+ was poor, the reliability of the interlayer insulating layer 4 in the moisture resistance and temperature cycle tests was low. However, since the interlayer insulating layer 4 has a large coefficient of thermal expansion, the interlayer insulating layer 4 is likely to peel off in a thermal shock test, and the insulating substrate 1 is likely to crack or break. When using a multilayer circuit board with a built-in resistor, the resistor layer is formed on a ceramic substrate.However, in the case of a multilayer circuit board with a built-in resistor, cracks may occur in the resistor layer as well. There were times when it became impossible to perform its functions. Furthermore, since the dielectric constant of the interlayer insulating layer 4 is large, it is necessary to take stray capacitance into consideration when creating multilayer wiring, and the degree of freedom in wiring the circuit is limited.
(発明の目的)
本発明は、」1記従来例の欠点に鑑みてなされたもので
、層間絶縁層と第1の回路導体層および絶縁基板の表面
との密着性および層間絶縁層の耐熱衝撃性を向上させて
、信頼性の高い多層回路基板を提供するものである。(Object of the Invention) The present invention has been made in view of the drawbacks of the conventional example described in 1. The purpose of the present invention is to provide a multilayer circuit board with improved properties and high reliability.
(発明の構成)
上記目的を達成するために、本発明は、第1の回路導体
層が形成された絶縁基板」二に、面j熱衝撃性の優れた
樹脂と耐熱性の優れた樹脂とを順次積層した二層構造を
有し且つ微細孔を有する層間絶縁層を形成し、この層間
絶縁層」二に微細孔を通して第1の回路導体層と電気的
に接続する第2の回路導体層を形成するようにしたもの
である。(Structure of the Invention) In order to achieve the above object, the present invention provides an insulating substrate on which a first circuit conductor layer is formed. A second circuit conductor layer is formed which has a two-layer structure in which layers are sequentially laminated and has micropores, and the second circuit conductor layer is electrically connected to the first circuit conductor layer through the micropores in this interlayer insulator layer. It is designed to form a .
(実施例の説明) 以下、図面により本発明の実施例を詳細に説明する。(Explanation of Examples) Embodiments of the present invention will be described in detail below with reference to the drawings.
第2図は、本発明の一実施例の要部断面図である。第2
図において、絶縁基板6は、ガラスエポキシ、ガラスポ
リイミド、紙フェノールまたはコンポジット材などの合
成樹脂から々す、1ず、その−主面にエツチングにより
銅箔からなる第1の5−
回路導体層7が形成されている。そして、第1の回路導
体層7が形成された絶縁基板6上に、耐熱衝撃性の優れ
た樹脂と耐熱性の優れた樹脂とが順次積層された二層構
造の層間絶縁層8が形成されていて、1だ、層間絶縁層
8には微細孔9が形成されている。ここで、この二層構
造の層間絶縁層8は、第1層目の耐熱衝撃性の優れた樹
脂、即ち絶縁基板6およびその表面に形成された第1の
回路導体層7と密着する樹脂として環化ゴム系ポリブタ
ジェン樹脂、第2層目の耐熱性の優れた樹脂としてアク
リル系樹脂がそれぞれ使用されている。FIG. 2 is a sectional view of a main part of an embodiment of the present invention. Second
In the figure, the insulating substrate 6 is made of synthetic resin such as glass epoxy, glass polyimide, paper phenol or composite material, and first has a first circuit conductor layer 7 made of copper foil etched on its main surface. is formed. Then, on the insulating substrate 6 on which the first circuit conductor layer 7 is formed, an interlayer insulating layer 8 having a two-layer structure in which a resin with excellent thermal shock resistance and a resin with excellent heat resistance are sequentially laminated is formed. 1, minute holes 9 are formed in the interlayer insulating layer 8. Here, the interlayer insulating layer 8 having a two-layer structure is a first layer of resin having excellent thermal shock resistance, that is, a resin that is in close contact with the insulating substrate 6 and the first circuit conductor layer 7 formed on the surface thereof. A cyclized rubber-based polybutadiene resin and an acrylic resin are used as the resin with excellent heat resistance for the second layer.
これらの樹脂材料はポリエステルフィルム上に二層に塗
布されてフィルム化され、感光性を付与されていて、こ
れが感光性樹脂層として第1の回路導体層7が形成され
た絶縁基板6上に被着され、露光・現像などの7定の作
業を経て、微細孔9、いわゆるピアホールが形成されて
いる。こうして形成された層間絶縁層8上に、無電解メ
ッキ法、蒸着法およびイオンブレーティング法などの薄
膜技術捷たは導体ペースi・を印刷するなどの方法に−
6=
より第2の回路導体層10が形成され、壕だその際に、
層間絶縁層8に形成された微細孔9を通して第2の回路
導体層10が第1の回路導体層7と電気的に接続されて
いる。These resin materials are coated in two layers on a polyester film to form a film and are imparted with photosensitivity, and this is coated as a photosensitive resin layer on the insulating substrate 6 on which the first circuit conductor layer 7 is formed. The microscopic holes 9, so-called pier holes, are formed through seven different operations such as exposure and development. On the interlayer insulating layer 8 formed in this way, a thin film technique such as electroless plating, vapor deposition, and ion blating, or a method such as printing a conductive paste i.
6= When the second circuit conductor layer 10 is formed and the trench is formed,
The second circuit conductor layer 10 is electrically connected to the first circuit conductor layer 7 through the microholes 9 formed in the interlayer insulating layer 8 .
上記の構成において、本実施例での1、層間絶縁層8が
二層構造を有し、第1の回路導体層7が形成された絶縁
基板60表面に密着する第1層目が可とう性を有する環
化ゴム系ポリブタジェン樹脂からなるので、層間絶縁層
8の第1層目とアクリル系樹脂から々る第2層目との間
および層間絶縁層8と第1の回路導体層6との間の密着
性が非常に良く、層間絶縁層8の耐湿性が向」ニすると
ともに、この第1層目の環化ゴム系ポリブクジエン樹脂
が熱に対する緩衝材として作用するため、急激な熱衝撃
に対する層間絶縁層8の剥離を防止することができる。In the above configuration, 1 in this embodiment, the interlayer insulating layer 8 has a two-layer structure, and the first layer that is in close contact with the surface of the insulating substrate 60 on which the first circuit conductor layer 7 is formed is flexible. Since it is made of a cyclized rubber-based polybutadiene resin having a The adhesion between the layers is very good, improving the moisture resistance of the interlayer insulating layer 8, and the cyclized rubber-based polybucdiene resin in the first layer acts as a buffer against heat, so it is resistant to sudden thermal shocks. Peeling of the interlayer insulating layer 8 can be prevented.
さらに、」−記のように層間絶縁層8をアクリル系樹脂
と環化ゴム系ポリブタジェン樹脂との二層で構成するこ
とにより、層間絶縁層8の誘電率を従来に比べて小さく
することができ、従来のアクリル系樹脂だけのもので誘
電率が4.0であったのに対して本実施例では30以下
となるので、層間絶縁層8を挾んで信1する第1の回路
導体層7および第2の回路導体層10への浮遊容量の影
響を緩和することができ、回路膜n」の自由度が増大す
る。Furthermore, by constructing the interlayer insulating layer 8 with two layers of acrylic resin and cyclized rubber-based polybutadiene resin as shown in ``-'', the dielectric constant of the interlayer insulating layer 8 can be made smaller than that of the conventional one. The dielectric constant of the conventional acrylic resin alone was 4.0, but in this example it is 30 or less. Also, the influence of stray capacitance on the second circuit conductor layer 10 can be alleviated, and the degree of freedom of the circuit film n'' is increased.
また、本発明の他の実施例として抵抗体内蔵型の多層回
路基板を第3図に示す。なお、第2図と同一機能のもの
には同一符号をイ」シである。本実施例は、絶縁基板6
としてアルミナなどのセラミックス基板を用いて、その
表面に銀や銀−パラジウム系などのメタルブレース系の
導体月料からなる厚膜導体により第1の回路導体層7を
形成し、さらに同一面上にメタルブレース系の抵抗体材
料からなる抵抗体層11を形成している。そして、第1
の回路導体層7と抵抗体層11とを形成した絶縁基板6
」−に、前記の実施例と同様にして、微細孔9を有し且
つ環化ゴム系ポリブタジェン樹脂とアクリル系樹脂との
二層構造を有する層間絶縁層8をフォト技術を用いて形
成し、この層間絶縁層8の表面、すなわちアクリル系樹
脂層の表面に、無電解メッキ技術を利用したアディティ
ブ法により微細孔9を通して第1の回路導体層7と電気
的に接続する第2の回路導体層10を形成して、抵抗体
内蔵型の多層回路基板としだものである。Further, as another embodiment of the present invention, a multilayer circuit board with a built-in resistor is shown in FIG. Components with the same functions as those in FIG. 2 are designated by the same reference numerals. In this embodiment, the insulating substrate 6
A ceramic substrate such as alumina is used as a substrate, and a first circuit conductor layer 7 is formed on the surface of the substrate using a thick film conductor made of a metal brace conductor material such as silver or silver-palladium. A resistor layer 11 made of a metal brace resistor material is formed. And the first
An insulating substrate 6 on which a circuit conductor layer 7 and a resistor layer 11 are formed.
-, in the same manner as in the above embodiment, an interlayer insulating layer 8 having micropores 9 and having a two-layer structure of a cyclized rubber-based polybutadiene resin and an acrylic resin is formed using photo technology, A second circuit conductor layer is formed on the surface of this interlayer insulating layer 8, that is, on the surface of the acrylic resin layer, and is electrically connected to the first circuit conductor layer 7 through micropores 9 by an additive method using electroless plating technology. 10 to form a multilayer circuit board with a built-in resistor.
上記の構成において、本実施例は、絶縁基板6に熱膨張
係数の極めて小さいセラミックスを用いているが、この
よう々熱膨張係数の小さい基板を用いた場合でも、二層
構造を有する層間絶縁層8の環化ゴム系ポリブタジェン
樹脂の層が絶縁基板6の表面に密着し、緩衝材として作
用するために、はんだ付けや温度サイクルテストなどの
熱衝撃による層間絶縁層8の絶縁基板6からの剥離およ
び絶縁基板6へのクラックや割れ不良を生じるととがな
く、さらに、絶縁基板6上に形成した抵抗体層11への
悪影響もない。In the above configuration, this embodiment uses ceramics with an extremely small coefficient of thermal expansion for the insulating substrate 6, but even when a substrate with such a small coefficient of thermal expansion is used, the interlayer insulating layer having a two-layer structure Since the layer of cyclized rubber-based polybutadiene resin 8 adheres to the surface of the insulating substrate 6 and acts as a buffer material, the interlayer insulating layer 8 is not peeled off from the insulating substrate 6 due to thermal shock during soldering or temperature cycle testing. Moreover, there is no possibility of cracking or cracking of the insulating substrate 6, and furthermore, there is no adverse effect on the resistor layer 11 formed on the insulating substrate 6.
なお、前記の2つの実施例では、絶縁基板6の一方の主
面にだけ第1の回路導体層7を形成し、その上に二層構
造の層間絶縁層8を介して第2の回路導体層10を形成
した二段構成の多層回路基板について説明したが、本発
明は」1記の構造に限9一
定されるものではなく、」−記の実施例の土にさらに層
間絶縁層8と回路導体層とを交互に積層してより多層化
したり、捷だ、絶縁基板6の両主面に第1の回路導体層
7をそれぞれ形成し、且つ両者をスルーホール接続して
おき、この絶縁基板6の両主面の第1の回路導体層7を
それぞれ多層配線化して、絶縁基板6の表裏両方向に多
層化を進めたりしてもよい。In the above two embodiments, the first circuit conductor layer 7 is formed only on one main surface of the insulating substrate 6, and the second circuit conductor layer is formed thereon via the interlayer insulating layer 8 having a two-layer structure. Although a two-stage multilayer circuit board in which the layer 10 is formed has been described, the present invention is not limited to the structure described in ``1''. The first circuit conductor layer 7 can be formed on both main surfaces of the insulating substrate 6, and the first circuit conductor layer 7 can be formed on both main surfaces of the insulating substrate 6, and the two can be connected through holes. The first circuit conductor layers 7 on both main surfaces of the substrate 6 may be formed into multilayer wiring, and multilayering may be promoted in both the front and back directions of the insulating substrate 6.
(発明の効果)
以上説明したように、本発明は、第1の回路導体層を形
成した絶縁基板」−に、耐熱衝撃性の優れた樹脂と耐熱
性の優れた樹脂とを順次積層した二層構造の層間絶縁層
を形成し、その」−に等20回回路体層を形成して多層
配線化を行うことにより、層間絶縁層と第1の回路導体
層との密着性が著しく改善されるとともに、層間絶縁層
の第1層目の耐熱衝撃性の優れた樹脂の層が熱に対する
緩衝材として作用するので、はんだ付は作業時などの急
激な熱衝撃における層間絶縁層の剥離または絶縁基板へ
のクラックや割れ不良を防止して、多層回−10=
路基板の信頼性を向−1−させるととができ、寸だ、層
間絶縁層の誘電率を小さくして浮遊容量の影響を緩和す
ることができるので、回路設剖の自由度が増大する等の
効果を有するものである。(Effects of the Invention) As explained above, the present invention provides a double layer in which a resin with excellent thermal shock resistance and a resin with excellent heat resistance are sequentially laminated on an insulating substrate on which a first circuit conductor layer is formed. The adhesion between the interlayer insulating layer and the first circuit conductor layer is significantly improved by forming an interlayer insulating layer with a layered structure and forming a circuit body layer 20 times on top of the interlayer insulating layer to form multilayer wiring. At the same time, the first layer of the interlayer insulating layer, a resin layer with excellent thermal shock resistance, acts as a buffer against heat. It is possible to prevent cracks and breakage defects on the board, improve the reliability of multilayer circuit boards, and reduce the dielectric constant of the interlayer insulation layer to reduce the effects of stray capacitance. This has the effect of increasing the degree of freedom in circuit design.
第1図は、従来の多層回路基板の要部断面図、第2図は
、本発明の一実施例の要部断面図、第3図は、本発明の
他の実施例の要部断面図である。
6 ・・・・・・・・絶縁基板、 7・・・・・・・第
1の回路2蜀体層、 8・・・・・・・・・層間絶縁層
、 9・・・・・・・・微細孔、IO・・・・・・・・
第2の回路導体層、 11・・・・・・・・・抵抗体層
。
特許出願人 松下電器産業株式会社
:、−t
11−
第1図
第2図
第3図FIG. 1 is a sectional view of a main part of a conventional multilayer circuit board, FIG. 2 is a sectional view of a main part of an embodiment of the present invention, and FIG. 3 is a sectional view of a main part of another embodiment of the present invention. It is. 6...Insulating substrate, 7...First circuit 2 layer, 8...Interlayer insulating layer, 9...・・Micropore, IO・・・・・・・・
Second circuit conductor layer, 11...Resistor layer. Patent applicant Matsushita Electric Industrial Co., Ltd.: -t 11- Figure 1 Figure 2 Figure 3
Claims (4)
に形成した第1の回路導体層と、該第1の回路導体層を
形成した前記絶縁基板上に耐熱衝撃性の優れた樹脂と耐
熱性の優れた樹脂とを順次積層してなる感光性樹脂層を
露光・現像して微細孔を形成した二層構造の層間絶縁層
と、該層間絶縁層上に設け、前記微細孔を通して前記第
1の回路導体層と電気的に接続した第2の回路導体層と
を有することを特徴とする多層回路基板。(1) An insulating substrate, a first circuit conductor layer formed on at least one main surface of the insulating substrate, and a resin having excellent thermal shock resistance on the insulating substrate on which the first circuit conductor layer is formed. an interlayer insulating layer with a two-layer structure in which fine pores are formed by exposing and developing a photosensitive resin layer made by sequentially laminating a resin with excellent heat resistance; A multilayer circuit board comprising a second circuit conductor layer electrically connected to the first circuit conductor layer.
た樹脂として環化ゴム系ポリブタジェン樹脂、耐熱性の
優れた樹脂としてアクリル系樹脂をそれぞれ用いたこと
を特徴とする特許請求の範囲第(])項記載の多層回路
基板。(2) The interlayer insulating layer of the two-layer structure uses a cyclized rubber-based polybutadiene resin as the resin with excellent thermal shock resistance, and an acrylic resin as the resin with excellent heat resistance. A multilayer circuit board as described in Range No. ( ]).
路導体層は金属箔からなることを特徴とする特許請求の
範囲第(1)項記載の多層回路基板。(3) The multilayer circuit board according to claim (1), wherein the insulating substrate is made of synthetic resin, and the first circuit conductor layer is made of metal foil.
の回路導体層はメタルグレーズ系の導体旧材からなり、
さらに、前記絶縁基板上に前記第1の回路導体層ととも
にメタルグレーズ系の抵抗体層を形成したことを特徴と
する特許請求の範囲第(1)項記載の多層回路基板。(4) The insulating substrate is made of ceramics, and the first
The circuit conductor layer is made of old metal glaze conductor material.
The multilayer circuit board according to claim 1, further comprising a metal glaze-based resistor layer formed on the insulating substrate together with the first circuit conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19695583A JPS6089996A (en) | 1983-10-22 | 1983-10-22 | Multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19695583A JPS6089996A (en) | 1983-10-22 | 1983-10-22 | Multilayer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6089996A true JPS6089996A (en) | 1985-05-20 |
Family
ID=16366428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19695583A Pending JPS6089996A (en) | 1983-10-22 | 1983-10-22 | Multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6089996A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2013145043A1 (en) * | 2012-03-27 | 2015-08-03 | パナソニックIpマネジメント株式会社 | Build-up substrate, manufacturing method thereof, and semiconductor integrated circuit package |
-
1983
- 1983-10-22 JP JP19695583A patent/JPS6089996A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2013145043A1 (en) * | 2012-03-27 | 2015-08-03 | パナソニックIpマネジメント株式会社 | Build-up substrate, manufacturing method thereof, and semiconductor integrated circuit package |
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