JPH04274345A - Manufacture of multilayer wiring substrate - Google Patents

Manufacture of multilayer wiring substrate

Info

Publication number
JPH04274345A
JPH04274345A JP3496491A JP3496491A JPH04274345A JP H04274345 A JPH04274345 A JP H04274345A JP 3496491 A JP3496491 A JP 3496491A JP 3496491 A JP3496491 A JP 3496491A JP H04274345 A JPH04274345 A JP H04274345A
Authority
JP
Japan
Prior art keywords
polyimide film
insulating layer
substrate
via hole
ultraviolet rays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3496491A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Tamura
田村 浩悦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3496491A priority Critical patent/JPH04274345A/en
Publication of JPH04274345A publication Critical patent/JPH04274345A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent generation of pattern open by embedding a sensitive polyimide film having high solubility in viaholes by screen printing after forming viaholes of a sensitive polyimide film of a first insulating layer on a wiring pattern. CONSTITUTION:A sensitive polyimide film 3a is applied to the whole surface of a substrate 1, the surface of the sensitive polyimide film 3a of the upper part having a formed wiring pattern 2 is exposed to ultraviolet rays through a shielding glass mask, and the exposed substrate 1 is developed so as to form a first insulating layer having viaholes generated on the part not irradiated with ultraviolet rays. Before forming a second insulating layer, a sensitive polyimide film 4 having high solubility is imbedded in the viaholes formed in a first insulating layer by screen printing.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は多層配線基板の製造方法
に関し、特にコンピュータ等の電子機器に使用する大規
模集積回路装着用の高密度多層配線基板の製造において
、上下の導体層の間を接続するビィアホールを形成する
工程を含む多層配線基板の製造方法に関する。
[Industrial Application Field] The present invention relates to a method for manufacturing a multilayer wiring board, and in particular to a method for manufacturing a high-density multilayer wiring board for mounting large-scale integrated circuits used in electronic equipment such as computers. The present invention relates to a method of manufacturing a multilayer wiring board including a step of forming via holes for connection.

【0002】0002

【従来の技術】従来、コンピュータ等の電子機器に使用
する大規模集積回路装着用の高密度多層配線基板の製造
においては、上下の導体層の間を接続するビィアホール
の形成は、次の工程に従って行われていた。
[Prior Art] Conventionally, in manufacturing high-density multilayer wiring boards for mounting large-scale integrated circuits used in electronic devices such as computers, via holes connecting upper and lower conductor layers are formed according to the following process. It was done.

【0003】まず、図3(a)に示すように、基板1上
に配線パターン2を形成する。
First, as shown in FIG. 3(a), a wiring pattern 2 is formed on a substrate 1.

【0004】次に、図3(b)に示すように、基板1の
表面に感光性ポリイミド膜3をスピンコート法によって
塗布して、70〜80℃の状態で40〜60分間の低温
乾燥を行う。この状態では、感光性ポリイミド膜3の膜
厚は、20〜30μmであり、まだイミド化していない
Next, as shown in FIG. 3(b), a photosensitive polyimide film 3 is coated on the surface of the substrate 1 by spin coating, and low-temperature drying is performed at 70 to 80° C. for 40 to 60 minutes. conduct. In this state, the thickness of the photosensitive polyimide film 3 is 20 to 30 μm and has not been imidized yet.

【0005】次に、図3(c)に示すように、感光性ポ
リイミド膜3の表面の一部を遮蔽したガラスマスク5を
通して、配線パターン設計に従ってあらかじめ定められ
た感光性ポリイミド膜3の表面の一部分のみを紫外線で
照射する。この後、70〜80℃の状態で90〜120
分間の低温乾燥を行う。
Next, as shown in FIG. 3(c), the surface of the photosensitive polyimide film 3 determined in advance according to the wiring pattern design is exposed through a glass mask 5 that partially shields the surface of the photosensitive polyimide film 3. Only a portion is irradiated with ultraviolet light. After this, at 70-80℃, 90-120℃
Dry at low temperature for 1 minute.

【0006】次に、上記の基板1を現像すると、図3(
d)に示すように、紫外線が照射されていない部分の感
光性ポリイミド膜3が除去され、ビィアホールが形成さ
れるが、ビィアホールは、正テーパ形(穴の上面が広く
、底面が狭くなる形状)のビィアホールが形成される。 このときの現像液は、メチルセルソルブ,N・メチル・
2・ピロリドン,メチルアルコール等の混合液が使用さ
れる。
Next, when the above substrate 1 is developed, it becomes as shown in FIG.
As shown in d), the photosensitive polyimide film 3 in the part not irradiated with ultraviolet rays is removed to form a via hole, which has a regular taper shape (the top surface of the hole is wide and the bottom surface is narrow). A via hall will be formed. The developer used at this time was Methylcellosolve, N.Methyl.
2. A mixture of pyrrolidone, methyl alcohol, etc. is used.

【0007】次に、このパターン加工された感光性ポリ
イミド膜3を300〜400℃でキュアすると、感光性
ポリイミド膜3はイミド化され、1層目の絶縁層が形成
される。
Next, when this patterned photosensitive polyimide film 3 is cured at 300 to 400° C., the photosensitive polyimide film 3 is imidized and a first insulating layer is formed.

【0008】上記でイミド化された感光性ポリイミド膜
3を一層だけ形成する処理を行ったことになるが、高密
度多層配線基板としては、電気的絶縁性のためにこの処
理を繰り返して二層以上の絶縁層が形成されている。
[0008] In the above process, only one layer of the imidized photosensitive polyimide film 3 was formed, but for high-density multilayer wiring boards, this process is repeated to form two layers for electrical insulation. The above insulating layers are formed.

【0009】[0009]

【発明が解決しようとする課題】上述した従来の多層配
線基板の製造方法では、第1絶縁層を形成した後の第2
絶縁層の形成時において、第1絶縁層と同じ厚さになる
ように、スピンコーティングすると、図3(e)に示す
ように、配線パターンの上部では、第2絶縁層の厚さ7
が、第1絶縁層の厚さ6に比較し厚く形成されるので、
次の工程で第2絶縁層の感光性ポリイミド膜を露光する
と、膜厚が厚いため、紫外線の透過が少なくなる。そし
て、膜厚が厚く、紫外線の透過が少ないことにより、次
の現像工程ではビィアホールの深さ方向の現像速度より
も、ビィアホール側面の現像速度が速くなるため、ビィ
アホール底部の感光性ポリイミド膜が除去されたとき、
第2絶縁層の感光性ポリイミド膜は、図3(f)に示す
ように、穴の上面が狭く、底面が広くなる形状の逆テー
パ形のビィアホール8が形成されやすくなる。この逆テ
ーパ形ビィアホール8が形成されると、上下の導体層を
接続する工程において、逆テーパ形ビィアホールの側面
により、上下の導体層の配線パターンの切断であるパタ
ーンオープンが生じやすくなるという欠点を有している
[Problems to be Solved by the Invention] In the conventional method for manufacturing a multilayer wiring board as described above, after forming the first insulating layer,
When forming the insulating layer, if spin coating is performed so that the thickness is the same as that of the first insulating layer, the thickness of the second insulating layer will be 7.5 mm above the wiring pattern, as shown in FIG. 3(e).
is formed thicker than the thickness 6 of the first insulating layer, so
When the photosensitive polyimide film of the second insulating layer is exposed in the next step, since the film is thick, less ultraviolet rays are transmitted. Because the film is thick and transmits little ultraviolet rays, the development speed on the sides of the via hole is faster than the development speed in the depth direction of the via hole in the next development process, so the photosensitive polyimide film at the bottom of the via hole is removed. When it is done,
In the photosensitive polyimide film of the second insulating layer, as shown in FIG. 3(f), an inversely tapered via hole 8 is easily formed in which the top surface of the hole is narrow and the bottom surface is wide. When this inverted tapered via hole 8 is formed, the disadvantage is that in the process of connecting the upper and lower conductor layers, pattern open, which is the disconnection of the wiring pattern of the upper and lower conductor layers, is likely to occur due to the side surface of the inverted tapered via hole. have.

【0010】本発明の目的は、正テーパ形のビィアホー
ルを形成することができ、パターンオープンの発生を防
止できる多層配線基板の製造方法を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a multilayer wiring board that can form a normally tapered via hole and prevent pattern opening.

【0011】[0011]

【課題を解決するための手段】本発明の多層配線基板の
製造方法は、(A)基板上に配線パターンを形成する第
一の工程、(B)前記基板の全面に亘って前記感光性樹
脂膜を塗布し、前記配線パターンが形成された上部の前
記感光性樹脂膜の表面の一部を遮蔽した遮蔽マスクを通
して紫外線を露光し、露光後前記基板の現像を行い、紫
外線が照射されなかった部分に生成された第1のビィア
ホールを有した第1絶縁層を形成する第二の工程、(C
)前記基板の全面に亘って感光性樹脂膜を再度塗布し、
前記配線パターンが形成された上部の前記感光性樹脂膜
の表面の一部を遮蔽した遮蔽マスクを通して紫外線を再
度露光し、露光後前記基板の現像を行い、紫外線が照射
されなかった部分に生成された第2のビィアホールを有
した第2絶縁層を形成する第三の工程、を含む多層配線
基板の製造方法において、前記第二の工程と第三の工程
との間に、(D)前記第1のビィアホールに溶解速度の
速い感光性樹脂膜を埋め込む工程、を備えて構成されて
いる。
[Means for Solving the Problems] The method for manufacturing a multilayer wiring board of the present invention includes (A) a first step of forming a wiring pattern on the board, (B) coating the photosensitive resin over the entire surface of the board. A film was applied, and ultraviolet rays were exposed through a shielding mask that shielded a part of the surface of the photosensitive resin film on which the wiring pattern was formed, and after exposure, the substrate was developed, and no ultraviolet rays were irradiated. a second step of forming a first insulating layer with a first via hole created in the part (C
) Applying a photosensitive resin film again over the entire surface of the substrate,
Ultraviolet rays are exposed again through a shielding mask that shields a part of the surface of the photosensitive resin film on which the wiring pattern is formed, and after exposure, the substrate is developed, so that no ultraviolet rays are generated in the portions that were not irradiated with ultraviolet rays. a third step of forming a second insulating layer having a second via hole. The first via hole is filled with a photosensitive resin film having a high dissolution rate.

【0012】0012

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

【0013】図1は、本発明の多層配線基板の製造方法
の一実施例を示し、工程の進行順に多層配線基板の断面
の状態を示した図である。
FIG. 1 shows an embodiment of the method for manufacturing a multilayer wiring board according to the present invention, and is a diagram showing a cross-sectional state of the multilayer wiring board in the order of progress of the steps.

【0014】本実施例の多層配線基板の製造方法は、基
板1上に配線パターン2を形成する工程、基板1の全面
に亘って感光性ポリイミド膜3aを塗布し、配線パター
ン2が形成された上部の感光性ポリイミド膜3aの表面
の一部を遮蔽したガラスマスク5を通して紫外線を露光
し、露光後基板1の現像を行い、紫外線が照射されなか
った部分に生成されたビィアホールを有した第1絶縁層
を形成する工程、第1絶縁層のビィアホールに溶解速度
の速い感光性ポリイミド膜4を埋め込む工程、基板1の
全面に亘って感光性ポリイミド膜3bを再度塗布し、配
線パターン2が形成された上部の感光性ポリイミド膜3
bの表面の一部を遮蔽したガラスマスク5を通して紫外
線を再度露光し、露光後基板1の現像を行い、紫外線が
照射されなかった部分に生成されたビィアホールを有し
た第2絶縁層を形成する工程から構成されている。
The method for manufacturing a multilayer wiring board according to this embodiment includes a step of forming a wiring pattern 2 on a substrate 1, a photosensitive polyimide film 3a is applied over the entire surface of the substrate 1, and the wiring pattern 2 is formed. Ultraviolet rays are exposed through a glass mask 5 that shields a part of the surface of the upper photosensitive polyimide film 3a, and after exposure, the substrate 1 is developed, and a first layer having a via hole formed in a portion not irradiated with ultraviolet rays is formed. A process of forming an insulating layer, a process of embedding a photosensitive polyimide film 4 having a high dissolution rate into the via holes of the first insulating layer, and a process of recoating the photosensitive polyimide film 3b over the entire surface of the substrate 1 to form a wiring pattern 2. The upper photosensitive polyimide film 3
The substrate 1 is exposed again to ultraviolet light through the glass mask 5 that shields a part of the surface of b, and after the exposure, the substrate 1 is developed to form a second insulating layer having via holes formed in the parts that were not irradiated with the ultraviolet light. It consists of processes.

【0015】次に、本実施例の多層配線基板の製造方法
について説明する。
Next, a method for manufacturing the multilayer wiring board of this embodiment will be explained.

【0016】図1において、図1(a)に示す配線パタ
ーン2を形成する工程から、図1(d)に示す、感光性
ポリイミド膜3aにビィアホールを形成して第1絶縁層
を形成する工程までは、従来技術の場合と同様である。
In FIG. 1, there are steps from the step of forming a wiring pattern 2 shown in FIG. 1(a) to the step of forming a first insulating layer by forming a via hole in the photosensitive polyimide film 3a, shown in FIG. 1(d). The steps up to this point are the same as in the prior art.

【0017】本実施例の多層配線基板の製造方法では、
第2絶縁層を形成する工程の前に、次の工程を設ける。 すなわち、図1(e)に示すように、第1絶縁層で形成
されたビィアホールに、溶解速度の速い感光性ポリイミ
ド膜4をスクリー印刷によって埋め込み、その後70〜
80℃の状態で30分間の低温乾燥を行う。
In the method for manufacturing a multilayer wiring board of this embodiment,
The following process is provided before the process of forming the second insulating layer. That is, as shown in FIG. 1(e), a photosensitive polyimide film 4 having a high dissolution rate is embedded in the via hole formed in the first insulating layer by screen printing, and then 70~
Low-temperature drying is performed at 80°C for 30 minutes.

【0018】上記の工程の後は、従来の場合と同様であ
り、図1(f)に示すように、第2絶縁層の感光性ポリ
イミド膜3bをスピンコート法によって塗布して、70
〜80℃の状態で40〜60分間の低温乾燥を行われる
。そして、このときの感光性ポリイミド膜3bも、従来
の場合と同様に1層目の感光性ポリイミド膜3aと同様
に20〜30μmの膜厚である。また、図1(g)に示
すように、ガラスマスク5を通して、配線パターン設計
に従ってあらかじめ定められた表面の一部分のみを紫外
線で露光し、70〜80℃の状態で90〜120分間の
低温乾燥が行われる。
After the above steps are the same as in the conventional case, as shown in FIG. 1(f), a photosensitive polyimide film 3b as a second insulating layer is applied by spin coating, and
Low-temperature drying is performed at ~80°C for 40-60 minutes. The photosensitive polyimide film 3b at this time also has a thickness of 20 to 30 μm, similar to the first layer photosensitive polyimide film 3a, as in the conventional case. In addition, as shown in FIG. 1(g), only a predetermined part of the surface according to the wiring pattern design is exposed to ultraviolet light through the glass mask 5, and low-temperature drying is performed at 70 to 80°C for 90 to 120 minutes. It will be done.

【0019】続いて、従来の場合と同様に現像が行われ
るが、図2に示すように第2絶縁層の感光性ポリイミド
膜3bのビィアホールが開いた後、直ぐに、埋め込んだ
溶解速度の速い感光性ポリイミド膜4が現像されるため
、従来よりビィアホールの深さ方向の現像速度が速くな
り、ビィアホール側面の感光性ポリイミド膜3bの現像
速度が抑えられる。このため、図1(h)に示すように
、接続性の良い正テーパ形のビィアホールが形成される
Next, development is carried out in the same manner as in the conventional case, but as shown in FIG. 2, immediately after the via hole in the photosensitive polyimide film 3b of the second insulating layer is opened, Since the photosensitive polyimide film 4 is developed, the development speed in the depth direction of the via hole is faster than before, and the development speed of the photosensitive polyimide film 3b on the side surface of the via hole is suppressed. Therefore, as shown in FIG. 1(h), a normally tapered via hole with good connectivity is formed.

【0020】このように、配線パターン上に第1絶縁層
の感光性ポリイミド膜3aのビィアホールを形成した後
に、溶解速度の速い感光性ポリイミド膜4をスクリー印
刷によってビィアホールに埋め込むことにより、第2絶
縁層の感光性ポリイミド膜3bの現像が、埋め込んだ溶
解速度の速い感光性ポリイミド膜4と同時に現像される
ので、ビィアホール側面の現像速度が抑えられ、正テー
パ形のビィアホールを形成することができる。
In this manner, after forming the via holes of the photosensitive polyimide film 3a of the first insulating layer on the wiring pattern, the photosensitive polyimide film 4 having a high dissolution rate is buried in the via holes by screen printing, thereby forming the second insulating layer. Since the layer photosensitive polyimide film 3b is developed at the same time as the buried photosensitive polyimide film 4 which has a high dissolution rate, the development rate of the side surface of the via hole is suppressed, and a normally tapered via hole can be formed.

【0021】[0021]

【発明の効果】以上説明したように、本発明の多層配線
基板の製造方法は、配線パターン上に第1絶縁層の感光
性ポリイミド膜のビィアホールを形成した後に、溶解速
度の速い感光性ポリイミド膜をスクリー印刷によってビ
ィアホールに埋め込むことにより、第2絶縁層の感光性
ポリイミド膜の現像が、埋め込んだ溶解速度の速い感光
性ポリイミド膜と同時に現像されるので、ビィアホール
側面の現像速度が抑えられ、正テーパ形のビィアホール
を形成することができ、上下の導体層間のビィアホール
の接続性を向上でき、パターンオープンの発生を防止で
きるという効果を有している。
As explained above, in the method for manufacturing a multilayer wiring board of the present invention, after forming via holes in the photosensitive polyimide film of the first insulating layer on the wiring pattern, By filling the via hole with screen printing, the photosensitive polyimide film of the second insulating layer is developed at the same time as the embedded photosensitive polyimide film, which has a high dissolution rate, so the development speed on the sides of the via hole is suppressed and the This has the effect that a tapered via hole can be formed, the connectivity of the via hole between the upper and lower conductor layers can be improved, and the occurrence of pattern open can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の多層配線基板の製造方法の一実施例を
示し、工程の進行順に多層配線基板の断面の状態を示し
た図である。
FIG. 1 is a diagram illustrating an embodiment of the method for manufacturing a multilayer wiring board according to the present invention, and showing a cross-sectional state of the multilayer wiring board in the order of progress of the steps.

【図2】図1に示す多層配線基板の製造方法における第
2絶縁層の感光性ポリイミド膜と第1絶縁層のビィアホ
ールに埋め込まれた溶解速度の速い感光性ポリイミド膜
の現像工程の途中の状態を示した図である。
FIG. 2 is a state during the development process of the photosensitive polyimide film of the second insulating layer and the photosensitive polyimide film with a fast dissolution rate embedded in the via holes of the first insulating layer in the method for manufacturing the multilayer wiring board shown in FIG. FIG.

【図3】従来の多層配線基板の製造方法を示し、工程の
進行順に多層配線基板の断面の状態を示した図である。
FIG. 3 is a diagram illustrating a conventional method for manufacturing a multilayer wiring board, showing the state of a cross section of the multilayer wiring board in the order of progress of the steps.

【符号の説明】[Explanation of symbols]

1    基板 2    配線パターン 3    感光性ポリイミド膜 4    感光性ポリイミド膜 5    ガラスマスク 6    第1絶縁層の厚さ 7    第2絶縁層の厚さ 8    逆テーパ形のビィアホール 1    Substrate 2 Wiring pattern 3 Photosensitive polyimide film 4 Photosensitive polyimide film 5 Glass mask 6 Thickness of first insulating layer 7 Thickness of second insulating layer 8 Reverse tapered via hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】(A)基板上に配線パターンを形成する第
一の工程、(B)前記基板の全面に亘って前記感光性樹
脂膜を塗布し、前記配線パターンが形成された上部の前
記感光性樹脂膜の表面の一部を遮蔽した遮蔽マスクを通
して紫外線を露光し、露光後前記基板の現像を行い、紫
外線が照射されなかった部分に生成された第1のビィア
ホールを有した第1絶縁層を形成する第二の工程、(C
)前記基板の全面に亘って感光性樹脂膜を再度塗布し、
前記配線パターンが形成された上部の前記感光性樹脂膜
の表面の一部を遮蔽した遮蔽マスクを通して紫外線を再
度露光し、露光後前記基板の現像を行い、紫外線が照射
されなかった部分に生成された第2のビィアホールを有
した第2絶縁層を形成する第三の工程、を含む多層配線
基板の製造方法において、前記第二の工程と第三の工程
との間に、(D)前記第1のビィアホールに溶解速度の
速い感光性樹脂膜を埋め込む工程、を含むことを特徴と
する多層配線基板の製造方法。
1. (A) a first step of forming a wiring pattern on a substrate, (B) applying the photosensitive resin film over the entire surface of the substrate, and applying the photosensitive resin film to the top of the substrate where the wiring pattern is formed; A first insulator having a first via hole formed in a portion not irradiated with ultraviolet rays by exposing ultraviolet rays through a shielding mask that shields a part of the surface of the photosensitive resin film, and developing the substrate after exposure. The second step of forming a layer, (C
) Re-applying a photosensitive resin film over the entire surface of the substrate,
Ultraviolet rays are exposed again through a shielding mask that shields a part of the surface of the photosensitive resin film on which the wiring pattern is formed, and after exposure, the substrate is developed, so that no ultraviolet rays are generated in the portions that were not irradiated with ultraviolet rays. a third step of forming a second insulating layer having a second via hole. 1. A method for manufacturing a multilayer wiring board, comprising the step of embedding a photosensitive resin film having a high dissolution rate into the via hole of No. 1.
【請求項2】  請求項1記載の多層配線基板の製造方
法において、前記感光性樹脂は感光性ポリイミド膜であ
ることを特徴とする多層配線基板の製造方法。
2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the photosensitive resin is a photosensitive polyimide film.
【請求項3】  請求項1及び請求項2記載の多層配線
基板の製造方法において、前記第1のビィアホールに前
記溶解速度の速い感光性樹脂膜をスクリーン印刷によっ
て埋め込むことを特徴とする多層配線基板の製造方法。
3. The method of manufacturing a multilayer wiring board according to claim 1 and claim 2, wherein the first via hole is filled with the photosensitive resin film having a high dissolution rate by screen printing. manufacturing method.
JP3496491A 1991-03-01 1991-03-01 Manufacture of multilayer wiring substrate Pending JPH04274345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3496491A JPH04274345A (en) 1991-03-01 1991-03-01 Manufacture of multilayer wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3496491A JPH04274345A (en) 1991-03-01 1991-03-01 Manufacture of multilayer wiring substrate

Publications (1)

Publication Number Publication Date
JPH04274345A true JPH04274345A (en) 1992-09-30

Family

ID=12428833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3496491A Pending JPH04274345A (en) 1991-03-01 1991-03-01 Manufacture of multilayer wiring substrate

Country Status (1)

Country Link
JP (1) JPH04274345A (en)

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