JPH04162643A - Manufacture of multi-layered wiring board - Google Patents
Manufacture of multi-layered wiring boardInfo
- Publication number
- JPH04162643A JPH04162643A JP28895990A JP28895990A JPH04162643A JP H04162643 A JPH04162643 A JP H04162643A JP 28895990 A JP28895990 A JP 28895990A JP 28895990 A JP28895990 A JP 28895990A JP H04162643 A JPH04162643 A JP H04162643A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide film
- filler
- containing polyimide
- via hole
- irradiated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920001721 polyimide Polymers 0.000 claims abstract description 46
- 239000000945 filler Substances 0.000 claims abstract description 36
- 239000011521 glass Substances 0.000 claims abstract description 6
- 230000001678 irradiating effect Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 7
- 238000001035 drying Methods 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 5
- 150000003949 imides Chemical class 0.000 abstract description 2
- 230000003287 optical effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線基板の製造方法に関し、特に上下の導
体層間をｌ接続するためのビィアホール形成工程を含む
多層配線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board that includes a step of forming via holes for connecting upper and lower conductor layers.
従来の多層配線基板の製造方法のうち、特に、コンピュ
ータ等の電子機器に使用するための大規模集積回路（Ｌ
Ｓ Ｉ ）装着用の高密度多層配線基板の製造方法にお
いて、上下の導体層間を接続するためのビィアホール形
成方法は、第２図（ａ）〜同図（ｄ）に示すように、基
板上に金属配線パターンを形成する第一の工程（第２図
（ａ）参照〉と、金属配線パターン２の上に前記基板の
全面に亘って感光性のフィラー入りポリイミド膜３をス
ピンコート法によって形成する第二の工程（第２図（ｂ
）参照）と、フィラー入りポリイミド１１！３をオーブ
ンによって低温乾燥する第三の工程（第２図（ｃ）参照
）と、フィラー入りポリイミド膜３に所定の部分を遮蔽
したガラスマスク５を介して紫外線を照射する第四の工
程（第２図（ｄ）参照）と、紫外線を照射したフィラー
入りポリイミド膜３を現像し、遮蔽した部分に対応する
部分のフィラー入りポリイミド膜３を除去してビィアホ
ール４を形成した後加熱し、フィラー入りポリイミド膜
３をイミド化する第五の工程と（第２図（ｅ）参照）と
によりなっていた。Among the conventional manufacturing methods of multilayer wiring boards, especially large-scale integrated circuits (L) for use in electronic devices such as computers
SI) In the method for manufacturing a high-density multilayer wiring board for mounting, the method for forming via holes for connecting upper and lower conductor layers is as shown in FIGS. 2(a) to 2(d). The first step is to form a metal wiring pattern (see FIG. 2(a)), and a photosensitive filler-containing polyimide film 3 is formed on the metal wiring pattern 2 over the entire surface of the substrate by spin coating. The second process (Fig. 2 (b)
)), a third step of drying the filler-containing polyimide 11!3 at a low temperature in an oven (see FIG. 2(c)), and a glass mask 5 that shields a predetermined portion of the filler-containing polyimide film 3. The fourth step is to irradiate ultraviolet rays (see Figure 2 (d)), develop the filled polyimide film 3 irradiated with ultraviolet rays, and remove the filled polyimide film 3 in the portions corresponding to the shielded portions to form via holes. After forming the filler-containing polyimide film 3, the filler-containing polyimide film 3 is heated to imidize the filler-containing polyimide film 3 (see FIG. 2(e)).
このような従来の多層配線基板の製造方法では、第２図
（ｂ）でスピンコートによる基板１内のフィラー入りポ
リイミド膜３の膜厚のばらつきと、低温乾燥による基板
１内の温度ばらつきとによる影響があり、また、第２図
（Ｃ）で紫外線Ｓの露光による基板１内の露光量のばら
つきの影響がある。そして、これらの悪影響が重なり、
第２図（ｄ）に示すように、現像すると基板１内でビィ
アホール４の側面が正テーパ形（穴の正面が広く、かつ
底面が狭くなる形状）と逆テーパ形（穴の上面が狭く、
かつ底面が広くなる形状）の両方のビィアホールか形成
される。この逆テーパ形のビィアホールが形成されると
、導体層を接続する工程において、逆テーパ形のビィア
ホールの側面と上層の配線パターンの切断が生じやすく
なり、いわゆるパターンオーブンが発生するという欠点
を有している。In such a conventional method for manufacturing a multilayer wiring board, as shown in FIG. 2(b), the difference in thickness of the filler-containing polyimide film 3 within the substrate 1 due to spin coating and the temperature variation within the substrate 1 due to low-temperature drying are In addition, as shown in FIG. 2(C), there is an effect of variations in the amount of exposure within the substrate 1 due to exposure to ultraviolet light S. And these negative effects overlap,
As shown in FIG. 2(d), when developed, the side surfaces of the via holes 4 in the substrate 1 have a normal taper shape (the front of the hole is wide and the bottom surface is narrow) and a reverse taper shape (the top surface of the hole is narrow and the bottom surface is narrow).
Both via holes (with a shape where the bottom surface becomes wider) are formed. When this inverted tapered via hole is formed, the side surface of the inverted tapered via hole and the upper layer wiring pattern are likely to be cut off in the process of connecting conductor layers, resulting in a so-called pattern oven. ing.
本発明の多層配線基板の製造方法は、基板上に金属配線
パターンを形成する第一の工程と、金属配線パターン上
に前記基板の全面に亘って感光性のフィラー入りポリイ
ミド膜をスピンコート法によって形成する第二の工程と
、フィラー入りポリイミド膜を低温乾燥する第三の工程
と、フィラー入りポリイミド膜に所定の部分を遮蔽した
ガラスマスクを介して紫外線を照射する第四の工程と、
前記紫外線を照射されていない箇所の前記フィラー入り
ポリイミド膜にマスクを介してエキシマレーザ−光を照
射し、前記フィラー入りポリイミド膜にビィアホールを
形成する直前まで穴を開ける第五の工程と、ビィアホー
ルを形成する直前まで穴を開けた前記フィラー入りポリ
イミド膜を現像してビィアホールを形成した後に加熱し
、フィラー入りポリイミド膜をイミド化する第六の工程
とを備えている。The method for manufacturing a multilayer wiring board of the present invention includes a first step of forming a metal wiring pattern on the board, and a step of applying a photosensitive filler-containing polyimide film over the entire surface of the board on the metal wiring pattern by spin coating. a second step of forming, a third step of drying the filled polyimide film at a low temperature, and a fourth step of irradiating the filled polyimide film with ultraviolet rays through a glass mask that shields a predetermined portion,
A fifth step of irradiating the filler-containing polyimide film in areas not irradiated with the ultraviolet rays with excimer laser light through a mask to make a hole in the filler-containing polyimide film until just before forming a via hole; and a sixth step of developing the filler-containing polyimide film in which holes have been made immediately before formation to form a via hole, and then heating the filler-containing polyimide film to imidize it.
次に、本発明の一実施例について、図面を参照して詳細
に説明する。Next, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜同図（ｄ）は本発明の一実施例によって
製造した多層配線基板を工程順に示した断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing a multilayer wiring board manufactured according to an embodiment of the present invention in the order of steps.
本実施例は、第１図（ａ）に示すように、腋ず基板１上
に下層の配線パターン２を形成する。次に、第１図（ｂ
）に示すように、この基板１の表面の全面にフィラー入
りポリイミド膜３をスピンコート法によって塗布してオ
ーブンで低温乾燥する。この状態では、フィラー入りポ
リイミド膜３の膜厚は２０μｍ〜３０＃ｌＩであり、ま
だイミド化していない。次に、第１図（ｃ）に示すよう
に、フィラー入りポリイミド膜３の表面の所望の部分に
のみに光エネルギーが照射するように一部を遮蔽したガ
ラスマスク５を通して紫外線Ｓを露光する。次に、第１
図（ｄ）に示すように、紫外線Ｓを照射されていない箇
所のフィラー入りポリイミド膜３にマスク６を介してエ
キシマレーザ−光Ｅを照射し、フィラー入りポリイミド
膜３にビィアホール４ａを形成する直前まで穴を開ける
。このとき、基板１内で配線パターン２上のフィラー入
りポリイミド膜厚のばらつきがあるため膜厚が厚い箇所
はエキシマレーザ−光Ｅの光量を増加して、配線パター
ン２上のビィアホール部のフィラー入りポリイミド膜厚
を均一にする。また、この状態でのビィアホール形状は
ほぼ垂直であり、かつビィアホールの開く直前４ａのフ
ィラー入りポリイミド膜面は荒れている。次に、第１図
（ｅ）に示すように、現像処理を行うと、ビィアホール
部のフィラー入りポリイミド膜面の荒れは現像液に溶解
され、荒れのない正テーパ形のビィアホール４が形成さ
れる。最後に、このようにしてパターン加工されたフィ
ラー入りポリイミド膜３を３００’Ｃ〜４００°Ｃで加
熱（キュア）してイミド化する。In this embodiment, as shown in FIG. 1(a), a lower layer wiring pattern 2 is formed on an armpit substrate 1. Next, Figure 1 (b
), a filler-containing polyimide film 3 is applied over the entire surface of the substrate 1 by spin coating and dried at a low temperature in an oven. In this state, the film thickness of the filler-containing polyimide film 3 is 20 μm to 30 #lI, and has not yet been imidized. Next, as shown in FIG. 1(c), ultraviolet light S is exposed through a partially shielded glass mask 5 so that the light energy irradiates only a desired portion of the surface of the filler-containing polyimide film 3. Next, the first
As shown in Figure (d), excimer laser light E is irradiated through a mask 6 to portions of the filler-containing polyimide film 3 that are not irradiated with ultraviolet rays S, and immediately before a via hole 4a is formed in the filler-containing polyimide film 3. Drill a hole until At this time, since there is variation in the thickness of the filler-containing polyimide film on the wiring pattern 2 within the substrate 1, the amount of excimer laser light E is increased in areas where the film thickness is thick, and filler is applied to the via hole portion on the wiring pattern 2. Make the polyimide film thickness uniform. Further, the shape of the via hole in this state is almost vertical, and the surface of the filler-containing polyimide film 4a immediately before the via hole opens is rough. Next, as shown in FIG. 1(e), when a development process is performed, the roughness on the surface of the filler-containing polyimide film in the via hole portion is dissolved in the developer, and a normally tapered via hole 4 without roughness is formed. . Finally, the filler-containing polyimide film 3 patterned in this manner is heated (cured) at 300'C to 400C to imide.
以上説明したように、本発明の多層配線基板の製造方法
は、フィラー入りポリイミド膜を露光した後に、未露光
部のフィラー入りポリイミド膜にエキシマレーザ−光を
照射した、ビィアホールを形成する直前まで穴を開けて
、最後に現像で基板内のビィアホールを正テーパ形にす
ることにより、上下の導体層間のビィアホールの接続性
を向上させる。これにより、パターンオーブンの発生を
防止できるという効果を有する。As explained above, the method for manufacturing a multilayer wiring board of the present invention involves exposing a filler-containing polyimide film to light, and then irradiating the unexposed portions of the filler-containing polyimide film with excimer laser light. By opening the via holes in the substrate and finally forming the via holes in the substrate into a regular tapered shape through development, the connectivity of the via holes between the upper and lower conductor layers is improved. This has the effect of preventing pattern ovens from occurring.
第１図（ａ）〜同図（ｅ）は本発明の一実施例によって
製造した多層配線基板を工程順に示した断面図。第２図
（ａ）〜同図（ｄ）は従来の製造方法によって製造した
多層配線基板を示す断面図である。
１・・・基板、２・・・配線パターン、３・・・フィラ
ー入りポリイミド膜、４・・・ビィアホール、４ａ・・
・ビィアホールの開く直前、５・・・ガラスマスク、６
・・・マスク、Ｓ・・・紫外線、Ｅ・・・エキシマレー
ザ−光。FIGS. 1(a) to 1(e) are cross-sectional views showing a multilayer wiring board manufactured according to an embodiment of the present invention in the order of steps. FIGS. 2(a) to 2(d) are cross-sectional views showing a multilayer wiring board manufactured by a conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring pattern, 3... Filler-containing polyimide film, 4... Via hole, 4a...
・Just before the beer hall opens, 5...Glass mask, 6
...mask, S...ultraviolet light, E...excimer laser light.
Claims (1)
多層配線基板製造方法であつて、（１）基板上に金属配
線パターンを形成する第一の工程 （２）前記金属配線パターン上に前記基板の全面に亘っ
て感光性のフィラー入りポリイミド膜をスピンコート法
によって形成する第二の工程 （３）前記フィラー入りポリイミド膜を低温乾燥する第
三の工程 （４）前記フィラー入りポリイミド膜に所定の部分を遮
蔽したガラスマスクを介して紫外線を照射する第四の工
程 （５）前記紫外線を照射されていない箇所の前記フィラ
ー入りポリイミド膜にマスクを介してエキシマレーザー
光を照射し、前記フィラー入りポリイミド膜にビィアホ
ールを形成する直前まで穴を開ける第五の工程 （６）前記ビィアホールを形成する直前まで穴を開けた
前記フィラー入りポリイミド膜を現像してビィアホール
を形成した後に加熱し、前記フィラー入りポリイミド膜
をイミド化する第六の工程 の各工程よりなることを特徴とする多層配線基板の製造
方法。[Scope of Claims] A method for manufacturing a high-density multilayer wiring board in which a metal wiring pattern is formed on a polyimide film, comprising: (1) a first step of forming a metal wiring pattern on the substrate; (2) the metal wiring pattern; a second step of forming a photosensitive filler-containing polyimide film over the entire surface of the substrate by spin coating (3) a third step of drying the filler-containing polyimide film at low temperature (4) drying the filler-containing polyimide film. A fourth step of irradiating ultraviolet rays through a glass mask that shields predetermined portions of the film (5) irradiating excimer laser light through the mask to the filler-containing polyimide film in areas that are not irradiated with the ultraviolet rays; A fifth step (6) of forming a hole in the filled polyimide film until immediately before forming a via hole; (6) heating the filled polyimide film after developing the filled polyimide film and forming a via hole until immediately before forming a via hole; A method for manufacturing a multilayer wiring board, comprising each step of the sixth step of imidizing the filler-containing polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28895990A JPH04162643A (en) | 1990-10-26 | 1990-10-26 | Manufacture of multi-layered wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28895990A JPH04162643A (en) | 1990-10-26 | 1990-10-26 | Manufacture of multi-layered wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162643A true JPH04162643A (en) | 1992-06-08 |
Family
ID=17737017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28895990A Pending JPH04162643A (en) | 1990-10-26 | 1990-10-26 | Manufacture of multi-layered wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162643A (en) |
-
1990
- 1990-10-26 JP JP28895990A patent/JPH04162643A/en active Pending
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