JPH0498891A - Manufacture of multilayer wiring board - Google Patents

Manufacture of multilayer wiring board

Info

Publication number
JPH0498891A
JPH0498891A JP21624890A JP21624890A JPH0498891A JP H0498891 A JPH0498891 A JP H0498891A JP 21624890 A JP21624890 A JP 21624890A JP 21624890 A JP21624890 A JP 21624890A JP H0498891 A JPH0498891 A JP H0498891A
Authority
JP
Japan
Prior art keywords
polyimide film
containing polyimide
filler
film
low temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21624890A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Tamura
田村 浩悦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21624890A priority Critical patent/JPH0498891A/en
Publication of JPH0498891A publication Critical patent/JPH0498891A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To protect a wiring pattern against disconnection by a method wherein the baking of a filler containing polyimide film is carried out in such a manner that 1/2-1/3 of the overall baking is performed before the film is exposed to light and the rest of the overall baking is carried out after the exposure of the film. CONSTITUTION:A lower wiring pattern 2 is formed on a board 1 (a). In succession, a filler containing polyimide film 3 is applied onto the whole surface of the board 1, which is dried up in an oven at a temperature (b). The film 3 is irradiated with ultraviolet rays S through a glass mask 6 which is partially shield so as to enable the film 3 to be irradiated with light energy (c). Then, the board 1 is dried up at a low temperature in an oven. By this low temperature drying of the board after exposure, a crosslinking reaction is accelerated inside the exposed part of the polyimide film 3 to be spread to the unexposed part. It is preferable that this low temperature drying is carried out two or three times as intense in baking as that performed before exposure (d). Then, when the board is developed, a positively tapered viahole 5 is formed through the effect of low temperature drying. Lastly, the, patterned filler containing polyimide film 3 is turned into the film 3 of imide by curing (e).

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層配線基板の製造方法に関し、特にコンピ
ュータ等の電子機器に使用するための大規模集積回路(
LSI)装着用の高密度多層配線基板において、上下の
導体層間を接続するためのビィアホール形成工程を含む
多層配線基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer wiring board, and in particular to a method for manufacturing a multilayer wiring board, particularly for large-scale integrated circuits (for use in electronic devices such as computers).
The present invention relates to a method for manufacturing a multilayer wiring board including a step of forming via holes for connecting upper and lower conductor layers in a high-density multilayer wiring board for mounting (LSI).

〔従来の技術〕[Conventional technology]

従来の多層配線基板の製造方法のうち、特にコンピュー
タ等の電子機器に使用するための大規模集積回路(LS
 I )装着用の高密度の多層配線基板の製造方法にお
いて、上下の導体層間を接続するためのビィアホール形
成方法について図面を用いて説明する。
Among conventional methods for manufacturing multilayer wiring boards, large-scale integrated circuits (LS) for use in electronic devices such as computers
I) In the method for manufacturing a high-density multilayer wiring board for mounting, a method for forming via holes for connecting upper and lower conductor layers will be described with reference to the drawings.

第2図(a)〜(d)は従来の多層配線基板の製造方法
によって製造される過程の多層配線基板の−例を示す断
面図である。
FIGS. 2(a) to 2(d) are cross-sectional views showing an example of a multilayer wiring board in the process of being manufactured by a conventional multilayer wiring board manufacturing method.

従来の多層配線基板の製造方法は、第2図(a)に示す
基板1上に金属の配線パターン2を形成する第1の工程
と、第2図(b)に示す配線パターン2の上に基板1の
全面に亘って感光性のフィラー入りポリイミド膜3をス
ピンコート法によって形成する第2の工程と、第2図(
c)に示すフィラー人りポリイミド膜3をオーブンによ
って低温乾燥する第3の工程と、フィラー入りポリイミ
ド膜3に所定の部分を遮蔽したガラスマスク6を介して
紫外線を照射する第4の工程と、第2図(d)に示す紫
外線を照射したフィラー入りポリイミド膜3を現像して
遮蔽した部分に対応する部分のフィラー入りポリイミド
膜3を除去して逆テーパーのビィアホール4を形成し、
フィラー入りポリイミド膜3をキュアしてイミド化する
第5の工程とを有した製造方法となっていた。
The conventional method for manufacturing a multilayer wiring board includes a first step of forming a metal wiring pattern 2 on a substrate 1 shown in FIG. 2(a), and a step of forming a metal wiring pattern 2 on the wiring pattern 2 shown in FIG. A second step of forming a photosensitive filler-containing polyimide film 3 over the entire surface of the substrate 1 by spin coating, and a step shown in FIG.
A third step of drying the filler-containing polyimide film 3 in an oven at a low temperature shown in c), and a fourth step of irradiating the filler-containing polyimide film 3 with ultraviolet rays through a glass mask 6 that shields a predetermined portion. The filler-containing polyimide film 3 irradiated with ultraviolet rays shown in FIG. 2(d) is developed and the filler-containing polyimide film 3 in the portion corresponding to the shielded portion is removed to form a reverse tapered via hole 4.
The manufacturing method included a fifth step of curing the filler-containing polyimide film 3 to imidize it.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多層配線基板の製造方法において、第2
図に示すようにフィラー入りポリイミド膜3の膜厚が2
0μm〜30μmと厚膜なため、第2図(c)に示すよ
うに露光時にフィラー入りポリイミド膜3の底面の方ま
で紫外線が透過しなく、次の現像工程を通すと、ビィア
ホール4の側面が逆テーパー形(穴の上面が狭く、底面
が広くなる形状)(参照符号4a)に形成されるので、
次工程の金属配線パターンの形成工程において、逆テー
パー形のビィアホール4の側面4aと上層の配線パター
ン2との切断が生じやすくなり、いわゆるパターンオー
ブンが発生するという欠点を有している。また、スピン
コートから現像までの放置時間が長いと吸湿により現像
時にクラックが発生しやすいという欠点もある。
In the conventional multilayer wiring board manufacturing method described above, the second
As shown in the figure, the film thickness of the filler-containing polyimide film 3 is 2
Because the film is thick, ranging from 0 μm to 30 μm, the ultraviolet rays do not pass through to the bottom of the filler-containing polyimide film 3 during exposure, as shown in FIG. Since it is formed in a reverse tapered shape (the top of the hole is narrow and the bottom is wide) (reference number 4a),
In the next step of forming a metal wiring pattern, the side surface 4a of the inversely tapered via hole 4 and the upper layer wiring pattern 2 are likely to be cut, resulting in a so-called pattern oven. Another drawback is that if the time from spin coating to development is long, cracks are likely to occur during development due to moisture absorption.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多層配線基板の製造方法は、基板上に金属配線
パターンを形成する第1の工程と、前記金属配線パター
ンの上に前記基板の全面に亘って感光性のフィラー入り
ポリイミド膜をスピンコート法によって形成する第2の
工程と、前記フィラー入りポリイミド膜をオーブンによ
って低温乾燥する第3の工程と、前記フィラー入りポリ
イミド膜に予め設定した所定の部分を遮蔽したガラスマ
スクを介して紫外線を照射する第4の工程と、前記フィ
ラー入りポリイミド膜を前記第3の工程より二〜三倍強
く低温乾燥する第5の工程と、前記紫外線を照射したフ
ィラー入りポリイミド膜を現像して前記遮蔽した部分に
対応する部分のフィラー入りポリイミド膜を除去してビ
ィアホールを形成し前記フィラー入りポリイミド膜をキ
ュアしてイミド化する第6の工程とを有している。
The method for manufacturing a multilayer wiring board of the present invention includes a first step of forming a metal wiring pattern on the board, and spin coating a photosensitive filler-containing polyimide film over the entire surface of the board on the metal wiring pattern. a second step of drying the filler-containing polyimide film at a low temperature in an oven, and irradiating ultraviolet rays through a glass mask that shields predetermined portions of the filler-containing polyimide film. a fifth step of drying the filler-containing polyimide film at a low temperature two to three times stronger than the third step, and developing the filler-containing polyimide film irradiated with ultraviolet rays to develop the shielded portion. and a sixth step of removing the filler-containing polyimide film in a corresponding portion to form a via hole, and curing the filler-containing polyimide film to imidize the filler-containing polyimide film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例によって製造
される多層配線基板の一例を工程順に示した断面図であ
る。
FIGS. 1(a) to 1(e) are cross-sectional views showing an example of a multilayer wiring board manufactured according to an embodiment of the present invention in the order of steps.

本実施例は、第1図(a)に示すように、まず基板1の
上に下層の配線パターン2を形成する。
In this embodiment, as shown in FIG. 1(a), first, a lower wiring pattern 2 is formed on a substrate 1.

次に、第1図(b)に示すように、この基板1の表面の
全面にフィラー入りポリイミド膜3をスピンコート法に
よって塗布してオーブンで低温で乾燥する。この状態で
は、フィラー入りポリイミド膜3の膜厚は20μm〜3
0Atmであり、まだイミド化していない、また低温乾
燥温度は70℃〜80℃で時間は40分〜60分とソフ
トベークの状態である。
Next, as shown in FIG. 1(b), a filler-containing polyimide film 3 is applied over the entire surface of the substrate 1 by spin coating and dried at a low temperature in an oven. In this state, the film thickness of the filler-containing polyimide film 3 is 20 μm to 3 μm.
0 Atm, it has not yet been imidized, and the low-temperature drying temperature is 70° C. to 80° C. and the time is 40 minutes to 60 minutes, which is a soft baking state.

次に、第1図(c)に示すように、フィラー入りポリイ
ミド膜3を表面の所望の部分のみに光エネルギーが照射
するように一部を遮蔽した(参照符号6a)ガラスマス
ク6を通して紫外線Sを露光する。この状態では紫外線
Sはフィラー入りポリイミドM3が20μm〜30μm
と厚いため、フィラー入りポリイミド膜3の底面の方ま
で紫外線が透過しない。
Next, as shown in FIG. 1(c), ultraviolet light S to expose. In this state, ultraviolet ray S is 20 μm to 30 μm for filler-containing polyimide M3.
Because of the thickness, ultraviolet rays do not penetrate to the bottom of the filler-containing polyimide film 3.

次に、第1図(d)に示すようにオーブンで低温乾燥す
る。この露光後の低温乾燥によって、フィラー入りポリ
イミド膜3の露光部の架橋反応が促進され未露光部まで
拡散される。この低温乾燥は露光前の低温乾燥よりも2
〜3倍強いベーキングで架橋反応が促進されやすく、7
0℃〜80℃で120分〜180分のベーキングが良い
Next, as shown in FIG. 1(d), it is dried at low temperature in an oven. By drying at a low temperature after this exposure, the crosslinking reaction in the exposed areas of the filler-containing polyimide film 3 is promoted and diffused to the unexposed areas. This low-temperature drying is 2 times higher than the low-temperature drying before exposure.
The cross-linking reaction is easily promoted by ~3 times stronger baking, and 7
Baking at 0°C to 80°C for 120 to 180 minutes is best.

次に、第1図(e)に示すように現像すると露光後の低
温乾燥の効果により、架橋反応が促進され、フィラー入
りポリイミド膜3の底面の方まで拡散されているので、
正テーパー(参照符号5a)を有する接続性の優れた正
テーパーのビィアホール5が形成される。最後に上述の
ようにしてパターン加工されたフィラー入りポリイミド
膜3を300℃〜400℃でキュアしてイミド化する。
Next, as shown in FIG. 1(e), when developed, the crosslinking reaction is promoted due to the effect of low-temperature drying after exposure and is diffused to the bottom of the filler-containing polyimide film 3.
A positively tapered via hole 5 having a positive taper (reference numeral 5a) with excellent connectivity is formed. Finally, the filler-containing polyimide film 3 patterned as described above is cured at 300° C. to 400° C. to imide.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の多層配線基板の製造方法は
、露光前後のフィラー入りポリイミド膜のベーキングの
割合を1= (2〜3)にすることにより、露光後の架
橋反応が促進され、現像工程を通して正テーパーのビィ
アホールを形成できるという効果があり、従ってパター
ンオープンの発生を防止できるという効果がある。また
露光後のベーキングによって吸湿対策となりクラックの
発生も防止できるという効果もある。
As explained above, in the method for manufacturing a multilayer wiring board of the present invention, by setting the baking ratio of the filler-containing polyimide film before and after exposure to 1=(2 to 3), the crosslinking reaction after exposure is promoted, and development There is an effect that a normally tapered via hole can be formed through the process, and therefore, it is possible to prevent the occurrence of a pattern open. Baking after exposure also has the effect of preventing moisture absorption and preventing the occurrence of cracks.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は本発明の一実施例によって製造
される多層配線基板の一例を工程順に示した断面図、第
2図(a)〜(d)は従来の多層配線基板の製造方法に
よって製造される過程の多層配線基板の一例を示す断面
図である。 1・・・基板、2・・・配線パターン、3・・・フィラ
ー入りポリイミド膜、4・・・逆テーパーのビィアホー
ル、5・・・正テーパーのビィアホール、6・・・ガラ
スマスク、7・・・紫外線の透過、8・・・架橋反応の
促進。
FIGS. 1(a) to (e) are cross-sectional views showing an example of a multilayer wiring board manufactured according to an embodiment of the present invention in the order of steps, and FIGS. 2(a) to (d) are cross-sectional views of a conventional multilayer wiring board. FIG. 3 is a cross-sectional view showing an example of a multilayer wiring board in the process of being manufactured by the manufacturing method of FIG. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring pattern, 3... Polyimide film containing filler, 4... Reverse taper via hole, 5... Positive taper via hole, 6... Glass mask, 7...・Transmission of ultraviolet rays, 8...Promotion of crosslinking reaction.

Claims (1)

【特許請求の範囲】[Claims]  基板上に金属配線パターンを形成する第1の工程と、
前記金属配線パターンの上に前記基板の全面に亘って感
光性のフィラー入りポリイミド膜をスピンコート法によ
って形成する第2の工程と、前記フィラー入りポリイミ
ド膜をオーブンによつて低温乾燥する第3の工程と、前
記フィラー入りポリイミド膜に予め設定した所定の部分
を遮蔽したガラスマスクを介して紫外線を照射する第4
の工程と、前記フィラー入りポリイミド膜を前記第3の
工程より二〜三倍強く低温乾燥する第5の工程と、前記
紫外線を照射したフィラー入りポリイミド膜を現像して
前記遮蔽した部分に対応する部分のフィラー入りポリイ
ミド膜を除去してビィアホールを形成し前記フィラー入
りポリイミド膜をキュアしてイミド化する第6の工程と
を有することを特徴とする多層配線基板の製造方法。
a first step of forming a metal wiring pattern on the substrate;
a second step of forming a photosensitive filler-containing polyimide film over the entire surface of the substrate on the metal wiring pattern by a spin coating method; and a third step of drying the filler-containing polyimide film at a low temperature in an oven. and a fourth step of irradiating ultraviolet rays through a glass mask that shields a predetermined portion of the filler-containing polyimide film.
a fifth step of drying the filler-containing polyimide film at a low temperature two to three times stronger than the third step, and developing the filler-containing polyimide film irradiated with the ultraviolet rays to correspond to the shielded portion. A method for manufacturing a multilayer wiring board, comprising the steps of: removing a portion of the filler-containing polyimide film to form a via hole; and curing the filler-containing polyimide film to imidize it.
JP21624890A 1990-08-16 1990-08-16 Manufacture of multilayer wiring board Pending JPH0498891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21624890A JPH0498891A (en) 1990-08-16 1990-08-16 Manufacture of multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21624890A JPH0498891A (en) 1990-08-16 1990-08-16 Manufacture of multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH0498891A true JPH0498891A (en) 1992-03-31

Family

ID=16685595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21624890A Pending JPH0498891A (en) 1990-08-16 1990-08-16 Manufacture of multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH0498891A (en)

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