JPH0499088A - Manufacture of multilayered printed wiring board - Google Patents
Manufacture of multilayered printed wiring boardInfo
- Publication number
- JPH0499088A JPH0499088A JP2208400A JP20840090A JPH0499088A JP H0499088 A JPH0499088 A JP H0499088A JP 2208400 A JP2208400 A JP 2208400A JP 20840090 A JP20840090 A JP 20840090A JP H0499088 A JPH0499088 A JP H0499088A
- Authority
- JP
- Japan
- Prior art keywords
- film
- solder resist
- printed wiring
- wiring board
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 abstract description 6
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 3
- 229920001225 polyester resin Polymers 0.000 abstract description 2
- 239000004645 polyester resin Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 238000010306 acid treatment Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013007 heat curing Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
多層プリント配線板の製造方法に関し、電子部品を挿入
しない小径のビアホールが確実にソルダーレジスト膜で
塗布されるような方法を有する多層プリント配線板の製
造方法を目的とし、ビアホール、並びにスルーホールを
形成したプリント配線板の両面に、ソルダーレジスト膜
を塗布した光透過フィルムを該レジスト膜が前記プリン
ト配線板に対向するように圧着し、
該光透過フィルム上にソルダーレジストパターンが形成
されたアートワークフィルムを設置して露光し、
前記光透過フィルムを除去後、露光後のソルダーレジス
ト膜を現像した後、該ソルダーレジスト膜を露光および
加熱硬化する工程を含むことで構成する。[Detailed Description of the Invention] [Summary] A method for manufacturing a multilayer printed wiring board, which includes a method in which a small diameter via hole in which no electronic component is inserted is reliably coated with a solder resist film. For the purpose of this, a light transmitting film coated with a solder resist film is pressure-bonded to both sides of a printed wiring board in which via holes and through holes are formed, so that the resist film faces the printed wiring board, and the light transmitting film is placed on the light transmitting film. The method includes a step of installing an artwork film on which a solder resist pattern is formed and exposing it to light, removing the light-transmitting film, developing the exposed solder resist film, and then exposing and heating the solder resist film to harden it. It consists of things.
本発明は多層プリント配線板の製造方法に関する。 The present invention relates to a method for manufacturing a multilayer printed wiring board.
エポキシ樹脂のような基材の両面に所定の銅箔パターン
を形成した中間層を、上記基材の片面に所定の銅箔パタ
ーンを形成した表面層の間に半硬化性のエポキシ樹脂よ
りなるプリプレグを挟んだ状態で加圧積層して第２図に
示すように多層プリント配線板５を形成する。A prepreg made of a semi-curing epoxy resin is formed between an intermediate layer with a predetermined copper foil pattern formed on both sides of a base material such as epoxy resin, and a surface layer with a predetermined copper foil pattern formed on one side of the base material. The multilayer printed wiring board 5 is formed as shown in FIG.
そしてこの多層プリント配線板に於いて、内部に導体層
を形成したスルーホール３やビアホール４を形成してい
る。このスルーホール３内には電子部品のビン等を挿入
してスルーホール３内の導体層と接続を採っているが、
ビアホールは電子部品を挿入せずに中間層に形成された
銅箔パターン９間を接続するために設けている。In this multilayer printed wiring board, through holes 3 and via holes 4 are formed with conductor layers formed inside. An electronic component bottle or the like is inserted into the through hole 3 and connected to the conductor layer inside the through hole 3.
The via holes are provided to connect the copper foil patterns 9 formed in the intermediate layer without inserting any electronic components.
このようなスルーホール３に電子部品のピン等を挿入し
て電子部品とスルーホールとを半田付けするために、上
記スルーホール３内に電解銅メツキ法で形成した銅の導
体層、並びに該スルーホール３の周囲に形成した銅のラ
ンドパターン上に更に半田メツキをする工程が必要とな
り、この半田メツキを行う工程で不要な箇所に半田メン
キされるのを防ぐために、前記鋼の導体層形成や、スル
ーホール、或いはビアホールの形成工程を終了した多層
プリント配線板にソルダーレジストパターンを形成する
工程が必要となる。In order to insert a pin or the like of an electronic component into such a through hole 3 and to solder the electronic component and the through hole, a copper conductive layer formed by an electrolytic copper plating method in the through hole 3 and the through hole 3 are used. An additional step of solder plating is required on the copper land pattern formed around the hole 3, and in order to prevent solder from being plated in unnecessary places during this solder plating step, the steel conductor layer is formed and It is necessary to form a solder resist pattern on the multilayer printed wiring board after completing the process of forming through holes or via holes.
そしてこのソルダーレジストパターンを形成する工程で
、前記電子部品を挿入しない小径のビアホール４上にレ
ジスト膜を被覆する工程が採られている。In the step of forming this solder resist pattern, a step of covering the small diameter via hole 4 into which the electronic component is not inserted is taken with a resist film.
この小径のビアホール４上にレジスト膜を形成するのは
、後の工程で該多層プリント配線板に電子部品を実装す
る際に、真空チャック等でこの多層プリント配線板を固
定する時、前記ビアホールより大気がリークして真空吸
着が確実に行い難くなるのを防ぐために行う。The purpose of forming a resist film on this small-diameter via hole 4 is that when electronic components are mounted on the multilayer printed wiring board in a later process, when the multilayer printed wiring board is fixed with a vacuum chuck or the like, the resist film is formed on the via hole 4. This is done to prevent air from leaking and making it difficult to perform vacuum suction reliably.
或いは、この小径のビアホール４に隣接されたスルーホ
ール３に表面実装型のフラントバソケージを実装する際
の溶融半田が、前記小径のビアホール４内に流れ込まな
いように前記ビアホール上をレジスト膜で被覆している
。Alternatively, the via hole is covered with a resist film so that molten solder when mounting a surface mount type flant bass cage in the through hole 3 adjacent to the small diameter via hole 4 does not flow into the small diameter via hole 4. are doing.
従来、このような小径のビアホール４上にレジスト膜を
形成するソルダーレジストパターンの形成方法として、
液状のレジスト液を噴射して塗布するスプレー法、回転
ロールにより塗布するロールコート法、或いはスクリー
ンを用いて塗布するスクリーンコート法等を用いて塗布
している。Conventionally, as a method for forming a solder resist pattern to form a resist film on such a small diameter via hole 4,
The coating is performed using a spray method in which a liquid resist solution is sprayed, a roll coating method in which the resist solution is applied using a rotating roll, a screen coating method in which the resist solution is applied using a screen, or the like.
然し、上記したいずれの方法でも、塗布した後のレジス
ト液を加熱して硬化させる段階で、ビアホール４内に残
留魁ている空気が膨張し、その膨張した空気が、塗布さ
れたレジスト膜を破って損傷させたり、或いはビアホー
ル上に形成されたレジスト膜にクラックやひびを発生さ
せたりする不都合がある。However, in any of the above methods, the air remaining in the via hole 4 expands at the stage of heating and curing the resist solution after coating, and the expanded air breaks the applied resist film. This has the disadvantage of causing damage to the via hole, or causing cracks in the resist film formed over the via hole.
このようにビアホール上にクランクやひびを有するレジ
スト膜を形成すると、例えば電子部品を実装する前に多
層プリント配線板の表面層の銅箔パターンを酸処理する
酸処理工程があり、この酸処理工程に用いた処理液が、
このビアホール４内に入り込む。If a resist film with cracks or cracks is formed on the via hole in this way, for example, before mounting electronic components, there is an acid treatment process in which the copper foil pattern on the surface layer of the multilayer printed wiring board is treated with acid. The processing liquid used for
It enters into this via hole 4.
そしてこのビアホールはクラックを発生したレジスト膜
で蓋をされた形であるので、酸処理後の水洗処理が行い
難く、そのためビアホール４内の導体層が残留した処理
液によって腐蝕される問題を生じる。Since this via hole is covered with a cracked resist film, it is difficult to wash with water after the acid treatment, resulting in the problem that the conductor layer in the via hole 4 is corroded by the remaining treatment liquid.
本発明は上記した問題点を解決するもので、上記ソルダ
ーレジストパターンの形成時に確実にビアホール上にレ
ジスト膜が形成されるようにした多層プリント配線板の
製造方法を提供することを目的とする。The present invention solves the above-mentioned problems, and aims to provide a method for manufacturing a multilayer printed wiring board in which a resist film is reliably formed on the via hole when forming the solder resist pattern.
上記した目的を達成する本発明の多層プリント配線板の
製造方法は、第１図（ａ）より第１図（ｄｌ迄に示すよ
うにビアホール４、並びにスルーホール３を形成した多
層プリント配線板５の両面に、ソルダーレジスト膜２を
塗布した光透過フィルムＩを該ソルダーレジスト膜が前
記多層プリント配線板に対向するように圧着し、
該光透過フィルム１上にソルダーレジストパターン６が
形成されたアートワークフィルム７を設置して露光し、
前記光透過フィルム１を除去後、露光後のソルダーレジ
スト膜２を現像した後、該ソルダーレジスト膜２を露光
および加熱硬化する工程を含むことを特徴としている。The method for manufacturing a multilayer printed wiring board of the present invention that achieves the above-mentioned object is directed to a multilayer printed wiring board 5 in which via holes 4 and through holes 3 are formed, as shown in FIG. 1(a) to FIG. 1(dl). A light transmitting film I coated with a solder resist film 2 is pressed onto both sides of the board so that the solder resist film faces the multilayer printed wiring board, and a solder resist pattern 6 is formed on the light transmitting film 1. The process is characterized by including the steps of: installing a work film 7 and exposing it to light; removing the light-transmitting film 1; developing the exposed solder resist film 2; and then exposing and heating the solder resist film 2. .
本発明の方法はポリエステル膜のような光透過フィルム
に分厚くソルダーレジスト膜を塗布形成し、このソルダ
ーレジスト膜が完全に硬化しない間に多層プリント配線
板の両面に対向するように真空圧着法を用いて固着して
おり、従来のようにソルダーレジスト膜を熱硬化させて
多層プリント配線板に固着していないため、ビアホール
上に熱硬化の際に発生しやすいクランクが生じない。The method of the present invention involves coating and forming a thick solder resist film on a light-transmitting film such as a polyester film, and using a vacuum pressure bonding method so that the solder resist film faces both sides of a multilayer printed wiring board while it is not completely cured. Since the solder resist film is not fixed to the multilayer printed wiring board by heat curing as in the conventional method, cranks that tend to occur during heat curing do not occur on the via holes.
また上記ソルダーレジスト膜は光透過フィルム上に分厚
く塗布形成しているので、最後の工程として行う加熱に
よる熱硬化の工程でも熱による影響を受は難く、ビアホ
ール上にクランクを発生しないソルダーレジスト膜が被
覆される。In addition, since the solder resist film mentioned above is thickly coated on the light-transmitting film, it is not easily affected by heat even in the final heat-curing process, and a solder resist film that does not cause cranking can be formed on the via hole. coated.
以下、図面を用いて本発明の一実施例につき詳細に説明
する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図（ａ）に示すようにポリエステル樹脂で形成した
光透過フィルムｌの表面に液状のレジスト液を塗布して
ソルダーレジスト膜２を７０〜８０μｍ程度の厚さに形
成する。As shown in FIG. 1(a), a liquid resist solution is applied to the surface of a light transmitting film 1 made of polyester resin to form a solder resist film 2 having a thickness of about 70 to 80 μm.
次いで第１図（ｂｌに示すように、上記ソルダーレジス
ト膜２が完全に硬化しないうちに、スルーホール３、お
よびビアホール４を形成した多層プリント配線板５の上
にソルダーレジスト膜を対向するようにして、上記ソル
ダーレジスト膜と多層プリント配線板の間を真空状態に
保ちながら真空プレス等を用いて圧着する。Next, as shown in FIG. 1 (bl), before the solder resist film 2 is completely cured, the solder resist film is placed so as to face the multilayer printed wiring board 5 on which the through holes 3 and via holes 4 have been formed. Then, while maintaining the space between the solder resist film and the multilayer printed wiring board in a vacuum state, the solder resist film and the multilayer printed wiring board are pressed together using a vacuum press or the like.
次いで第１図（Ｃ）に示すように、上記光透過フィルム
ｌ上に、ソルダーレジストパターン６が形成されたアー
トワークフィルム７を設置し、多層プリント配線板の両
面より矢印に示すように紫外線を照射して上記ソルダー
レジスト膜２を露光する。Next, as shown in FIG. 1(C), an artwork film 7 on which a solder resist pattern 6 is formed is placed on the light transmitting film 1, and ultraviolet rays are irradiated from both sides of the multilayer printed wiring board as shown by the arrows. The solder resist film 2 is exposed to light.
次いで第１図（ｄ）に示すように、上記光透過フィルム
ｌを剥離した後、現像処理を行って、未露光の箇所を除
去し、スルーホール３上にはソルダーレジスト膜が剥離
された半田パッド形成用パターン８を形成するとともに
、ビアホール４上にはソルダーレジスト膜２を被覆形成
する。Next, as shown in FIG. 1(d), after peeling off the light transmitting film 1, a development process is performed to remove the unexposed areas, and the solder resist film is peeled off and solder is placed on the through hole 3. A pad forming pattern 8 is formed, and a solder resist film 2 is formed on the via hole 4 to cover it.
そして、この後、ソルダーレジスト膜２の後露光を行い
、更に加熱処理して熱硬化処理を行う。Then, after this, the solder resist film 2 is subjected to post-exposure, and further heat treatment is performed to perform thermosetting treatment.
このようにすれば、上記光透過フィルム１に被着された
ソルダーレジスト膜２は真空圧着により多層プリント配
線板５に固着されるために、従来の熱硬化処理に於ける
クランク等の現象が発生せず、ビアホール上が確実にソ
ルダーレジスト膜で被覆され、後工程の酸処理の段階で
処理液がビアホール内に入り込まず、そのため、ビアホ
ール内の導体層が侵されず、高信幀度の多層プリント配
線板が得られる。In this way, the solder resist film 2 applied to the light transmitting film 1 is fixed to the multilayer printed wiring board 5 by vacuum pressure bonding, so that phenomena such as cranking occur in conventional thermosetting processing. The top of the via hole is reliably covered with a solder resist film, and the processing liquid does not enter the via hole during the acid treatment stage in the post-process, so the conductor layer inside the via hole is not attacked and a highly reliable multilayer structure is created. A printed wiring board is obtained.
以上の説明から明らかなように本発明によれば、多層プ
リント配線板の小径のビアホール上が、クラック等を生
じないソルダーレジスト膜で確実に被覆されるので、そ
の後の酸処理工程等でビアホール内の導体層が侵されな
い高信軌度の多層プリント配線板が得られる効果を生じ
る。As is clear from the above description, according to the present invention, the small diameter via holes of the multilayer printed wiring board are reliably covered with a solder resist film that does not cause cracks, etc. The effect is that a multilayer printed wiring board with high reliability can be obtained in which the conductor layer is not corroded.
第１図（ａ）より第１図Ｔｄｌ迄は、本発明の方法の工
程を示す断面図、
第２図は多層プリント配線板の説明図である。
図において、
１は光透過フィルム、２はソルダーレジスト膜、３はス
ルーホール、４はビアホール、５は多層プリント配線板
、６はソルダーレジストパターン、７はアートワークフ
ィルム、８は半田パッド形成用パターン、９は銅箔パタ
ーンを示す。FIG. 1(a) to FIG. 1Tdl are cross-sectional views showing the steps of the method of the present invention, and FIG. 2 is an explanatory diagram of a multilayer printed wiring board. In the figure, 1 is a light transmitting film, 2 is a solder resist film, 3 is a through hole, 4 is a via hole, 5 is a multilayer printed wiring board, 6 is a solder resist pattern, 7 is an artwork film, and 8 is a pattern for forming solder pads. , 9 indicates a copper foil pattern.
Claims (1)
した多層プリント配線板（５）の両面に、ソルダーレジ
スト膜（２）を塗布した光透過フィルム（１）を、該レ
ジスト膜が前記多層プリント配線板に対向するように圧
着し、該光透過フィルム（１）上にソルダーレジストパ
ターン（６）が形成されたアートワークフィルム（７）
を設置して露光し、前記光透過フィルム（１）を除去後
、露光後のソルダーレジスト膜（２）を現像した後、該
ソルダーレジスト膜（２）を露光、および加熱硬化する
工程を含むことを特徴とする多層プリント配線板の製造
方法。A light transmitting film (1) coated with a solder resist film (2) is applied to both sides of a multilayer printed wiring board (5) in which via holes (4) and through holes (3) are formed. An artwork film (7) that is crimped to face the board and has a solder resist pattern (6) formed on the light-transmitting film (1).
and exposing the solder resist film (2) to light, removing the light transmitting film (1), developing the exposed solder resist film (2), exposing the solder resist film (2) to light, and curing the solder resist film (2) by heating. A method for manufacturing a multilayer printed wiring board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2208400A JPH0499088A (en) | 1990-08-06 | 1990-08-06 | Manufacture of multilayered printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2208400A JPH0499088A (en) | 1990-08-06 | 1990-08-06 | Manufacture of multilayered printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0499088A true JPH0499088A (en) | 1992-03-31 |
Family
ID=16555627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2208400A Pending JPH0499088A (en) | 1990-08-06 | 1990-08-06 | Manufacture of multilayered printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0499088A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000001209A1 (en) * | 1998-06-26 | 2000-01-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and production method thereof |
| JP2000022334A (en) * | 1998-06-26 | 2000-01-21 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacture |
| KR20030033634A (en) * | 2001-10-24 | 2003-05-01 | 울트라테라 코포레이션 | Method for manufacturing solder mask of printed circuit board |
| KR100688094B1 (en) * | 2006-05-04 | 2007-03-02 | 삼성전기주식회사 | Exposure method and apparatus |
-
1990
- 1990-08-06 JP JP2208400A patent/JPH0499088A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000001209A1 (en) * | 1998-06-26 | 2000-01-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and production method thereof |
| JP2000022334A (en) * | 1998-06-26 | 2000-01-21 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacture |
| US6512186B1 (en) | 1998-06-26 | 2003-01-28 | Ibiden Co., Ltd. | Multilayer printed wiring board having a roughened inner conductor layer and production method thereof |
| KR20030033634A (en) * | 2001-10-24 | 2003-05-01 | 울트라테라 코포레이션 | Method for manufacturing solder mask of printed circuit board |
| KR100688094B1 (en) * | 2006-05-04 | 2007-03-02 | 삼성전기주식회사 | Exposure method and apparatus |
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