JP3890631B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

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Publication number
JP3890631B2
JP3890631B2 JP22775196A JP22775196A JP3890631B2 JP 3890631 B2 JP3890631 B2 JP 3890631B2 JP 22775196 A JP22775196 A JP 22775196A JP 22775196 A JP22775196 A JP 22775196A JP 3890631 B2 JP3890631 B2 JP 3890631B2
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Japan
Prior art keywords
plating layer
layer
opening hole
wiring board
printed wiring
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JP22775196A
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JPH1056262A (en
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義徳 高崎
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Ibiden Co Ltd
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Ibiden Co Ltd
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【０００１】
【技術分野】
本発明は，プリント配線板の製造方法に関し，特にブラインドビアホールと内層回路との接続に関する。
【０００２】
【従来技術】
従来，プリント配線板としては，例えば，図８に示すごとく，基板９５の表面に絶縁層９６を有し，両者の間に内層回路９３１を設けたものがある。内層回路９３１は，絶縁層９６に設けたブラインドビアホール９３２を介して，絶縁層９６の表面に設けた外層回路９３３と接続している。
【０００３】
上記プリント配線板９を製造するに当たっては，図９に示すごとく，基板９５の表面に内層回路９３１を形成する。次いで，この基板９５の表面に，感光性樹脂よりなる絶縁層９６を形成する。
次いで，フォトリソグラフィにより，絶縁層９５に開口穴９６１を空ける。即ち，絶縁層９５の表面に，ブラインドビアホール形成部分を覆う光遮断部４１と光透過部４２とからなるフォトマスク４を配置する。このフォトマスク４の上方から露光光を照射する。これにより，光透過部４２を通過した露光光により，ブラインドビアホール形成部分以外の絶縁層９６が硬化し，一方，光遮断部４１の下方に位置する絶縁層９６のブラインドビアホール形成部分は硬化しない。
【０００４】
次いで，フォトマスク４を取り去り，絶縁層９６を現像して，ブラインドビアホール形成部分の絶縁層９６を除去する。これにより，絶縁層９６にブラインドビアホール形成用の開口穴９６１が形成される。
【０００５】
次いで，図１０に示すごとく，フルアディティブ法により，ブラインドビアホール９３２及び外層回路９３３を形成する。即ち，絶縁層９６の表面における外層回路以外の部分に，レジスト膜９７を被覆する。次いで，無電解めっき処理を行い，絶縁層９６の表面及び開口穴９６１の内壁に表面めっき層９２を形成する。これにより，絶縁層９６の表面には外層回路９３３が形成されるとともに，開口穴９６１はその内壁が表面めっき層９２により被覆されてブラインドビアホール９３２が形成される。
以上により，上記プリント配線板９が得られる。
【０００６】
【解決しようとする課題】
しかしながら，上記従来のプリント配線板の製造方法においては，図９に示すごとく，絶縁層９６を露光する際に，絶縁層９６の内部で露光光が光遮断部４２から遠ざかるように回り込む。そのため，絶縁層９６には，上方から下方へと広がるテーパ形状の未露光部分が残る。この絶縁層９６を現像すると，テーパ状の未露光部分が除去されて，絶縁層９６にテーパ形状の開口穴９６１が形成される。
【０００７】
図１０に示すごとく，このテーパ形状の開口穴９６１の下方は，開口穴９６１の上方よりも広く開口して，開口穴の上方のテーパ角度よりも大きいテーパ角度を有するアンダーカット部９６２となる。この開口穴９６１に無電解めっき処理により表面めっき層９２を形成すると，表面めっき層９２がアンダーカット部９６２において局部的に薄くなってしまうことが多い。そのため，表面めっき層９２と内層回路９３１との接続不良が生じて，ブラインドビアホール９３２の接続信頼性が低い。
【０００８】
また，無電解めっき処理の代わりに，電気めっき処理を行った場合にも，無電解めっき処理を行った場合と同様に，表面めっき層９２がアンダーカット部９６２において局部的に薄くなる場合があり，ブラインドビアホール９３２の接続信頼性が低い。
【０００９】
本発明はかかる従来の問題点に鑑み，ブラインドビアホールと内層回路との接続信頼性に優れたプリント配線板の製造方法を提供しようとするものである。
【００１０】
【課題の解決手段】
請求項１の発明は，基板の表面に内層回路を形成し，次いで，上記基板の表面に，開口穴の下方に，上方のテーパ角度よりも大きいテーパ角度を有するアンダーカット部を有してなるブラインドビアホールを有する絶縁層を形成するプリント配線板の製造方法において，
上記絶縁層に対して上記内層回路から外方に向かう開口穴の底面に厚み３〜１０μｍの底面金属めっき層を施し，次いで，該底面金属めっき層及び開口穴の側壁に表面めっき層を施して上記ブラインドビアホールを形成することを特徴とするプリント配線板の製造方法である。
【００１１】
本発明において最も注目すべきことは，ブラインドビアホール形成用の開口穴の底面に露出した内層回路の表面に底面金属めっき層を形成し，その後，該底面金属めっき層の表面及び開口穴の側壁に表面めっき層を被覆することである。
【００１２】
本発明の作用及び効果について説明する。
本発明においては，内層回路が露出した開口穴の底面に，底面金属めっき層を形成する。そのため，開口穴の下方に，その上方のテーパ角度よりも大きいテーパ角度を有するアンダーカット部が形成されたとしても，底面金属めっき層が，アンダーカット部と内層回路との間を埋める。
【００１３】
それ故，上記底面金属めっき層の表面及び開口穴の側壁に表面めっき層を形成することにより，表面めっき層は，アンダーカット部よりも上方の開口穴の内壁に形成される。そのため，開口穴の側壁と底面金属めっき層の表面との切り返し部分にも十分に表面めっき層が形成される。
【００１４】
それ故，表面めっき層は，底面金属めっき層を介して内層回路と確実に接続される。従って，ブラインドビアホールと内層回路との接続信頼性に優れたプリント配線板を得ることができる。
以上のメカニズムは，感光性樹脂よりなる絶縁層に限ることなく，例えば熱硬化性樹脂よりなる絶縁層にも及ぶことは容易に理解される。
【００１５】
次に，請求項２の発明のように，上記底面金属めっき層を形成した後には，底面金属めっき層及び開口穴の側壁に触媒核を付着させ，その後上記表面めっき層を施すことが好ましい。これにより，開口穴の底面に底面金属めっき層を形成することができる。また，表面めっき層を均一に確実に形成できる。
【００１６】
次に，請求項３の発明のように，上記開口穴は，例えば，絶縁層の上方から下方への拡大するテーパ形状である。この場合にも，上記のごとく，内層回路との接続信頼性に優れたブラインドビアホールを形成できる。
【００１７】
【発明の実施の形態】
実施形態例１
本発明の実施形態例にかかるプリント配線板の製造方法について，図１〜図６を用いて説明する。
本例において製造されるプリント配線板８は，図１に示すごとく，基板５の表面に絶縁層６を有し，両者の間に内層回路３１を設けたものがある。内層回路３１は，絶縁層６に設けたブラインドビアホール３２を介して，絶縁層６の表面に設けた外層回路３３と接続している。
【００１８】
ブラインドビアホール３２は，絶縁層６に形成した開口穴６１の内壁に表面めっき層２を被覆したものである。表面めっき層２は，底面金属めっき層１を介して内層回路３１と接続している。
【００１９】
次に，上記プリント配線板の製造方法の概要について説明すると，まず，内層回路３１を含めて基板５の表面に絶縁層６を形成し，次いで，絶縁層６に対して内層回路３１から外方に向かう開口穴６１を形成する（図２）。
次いで，開口穴６１の底面に底面金属めっき層１を施す（図４）。次いで，フルアディティブ法により，底面金属めっき層１及び開口穴６１の側壁に表面めっき層２を施して絶縁層６にブラインドビアホール３２を形成する（図１）。
【００２０】
次に，上記プリント配線板の製造方法について詳細に説明する。
まず，出発原料として，樹脂製の基板の表面に，厚み３０〜４０μｍの銅箔をラミネートしてなる銅張積層板を準備する。次に，銅箔をパターン状にエッチングして，図２に示すごとく，基板５の表面に，内層回路３１を形成する。
次いで，上記基板５に黒化処理を行い，内層回路３１の表面に，厚み０．２〜３μｍの針状の黒化層を形成する（図示略）。
【００２１】
次に，感光性の絶縁性樹脂Ｖ１，Ｖ２を準備する。該絶縁性樹脂Ｖ１，Ｖ２はいずれもビスフェノールＡエポキシ樹脂とイミダゾール系硬化剤とを含み，絶縁性樹脂Ｖ１には更にシリカフィラーが，一方絶縁性樹脂Ｖ２には更にエポキシ樹脂フィラーが添加されている。これら絶縁性樹脂Ｖ１，Ｖ２を溶剤に溶解させた状態で，順に，ロールコータ法により基板５の表面に塗布し指触乾燥させる。
【００２２】
次いで，従来例で説明したフォトリソグラフィの手法（図９参照）に従って露光，現像を行うことにより，図２に示すごとく，絶縁層６の本硬化を行うと共に絶縁層６に開口穴６１を形成する。このとき，内層回路３１の上面の一部が絶縁層６から露出する。また，開口穴６１は，絶縁層６の上方から下方への拡大するテーパ形状であり，その裾部は開口穴６１の側壁において最もテーパ角度が大きいアンダーカット部６２となることが多い。
【００２３】
次に，上記基板５を，クロム酸等の粗化液で処理することによって，絶縁層６における樹脂フィラーを選択的に溶解する。これにより，図３に示すごとく，絶縁層６の表面及び開口穴６１の内壁に粗化面６５が形成される。
次に，図４に示すごとく，上記基板５に対して無電解銅めっき処理を行う。これにより，開口穴６１の底面から露出した内層回路３１に，厚み３〜１０μｍの底面金属めっき層１が形成される。なお，開口穴６１の側壁にはめっき用触媒核が付着していないため，底面金属めっき層は形成されない。
【００２４】
また，底面金属めっき層１の厚みが３μｍ未満の場合に，その底面金属めっき層の表面に表面めっき層を形成したとき開口穴のアンダーカット部における表面めっき層の膜厚が薄くなり，ブラインドビアホールと内層回路との電気接続信頼性が低くなるおそれがある。一方，１０μｍを越える場合には，電気接続信頼性に関しては問題がないが，無電解銅めっきのコストアップにつながるおそれがある。
【００２５】
次に，Ｐｄを含む触媒液に，上記基板を浸漬して，図５に示すごとく，上記粗化面６５にＰｄ系触媒核６６を付与する。次いで，図６に示すごとく，絶縁層６の表面における外層回路を形成しない部分にレジスト膜７を形成する。
【００２６】
次に，上記基板に対して無電解銅めっき処理を行い，図１に示すごとく，底面金属めっき層１及び開口穴６１の側壁に，厚み２０μｍの表面めっき層２を施して，絶縁層６にブラインドビアホール３２を形成する。
以上により，図１に示すプリント配線板８が得られる。
【００２７】
次に，本例の作用及び効果について説明する。
本例においては，図４に示すごとく，内層回路３１を露出させた開口穴６１の底面に，底面金属めっき層１を形成している。そのため，開口穴６１の下方に，その上方のテーパ角度よりも大きいテーパ角度を有するアンダーカット部６２が形成されたとしても，底面金属めっき層１が，アンダーカット部６２と内層回路３１との間を埋める。
【００２８】
それ故，図１に示すごとく，底面金属めっき層１の表面及び開口穴６１の側壁に表面めっき層２を形成することにより，表面めっき層２は，アンダーカット部よりも上方の開口穴６１の内壁に形成される。そのため，開口穴６１の側壁と底面金属めっき層１の表面との切り返し部分にも十分に表面めっき層２が形成される。
それ故，表面めっき層２は，底面金属めっき層１を介して内層回路３１と確実に接続される。従って，ブラインドビアホール３２と内層回路３１との接続信頼性に優れたプリント配線板８を得ることが出来る。
【００２９】
実施形態例２
本例においては，底面金属めっき層を電解銅めっき処理により形成した点が，無電解銅めっき処理により形成した実施形態例１の場合と相違する。
電解銅めっき処理を行うには，内層回路を電源リードと接続し，内層回路に通電しながら基板を電解液の中に浸漬することにより，底面金属めっき層を形成できる。
その他は，実施形態例１と同様である。
本例においても，実施形態例１と同様の効果を得ることができる。
【００３０】
実施形態例３
本例においては，表面めっき層を無電解銅めっき処理及び電解銅めっき処理により形成した点が，無電解銅めっき処理により形成した実施形態例１の場合と相違する。
即ち，表面めっき層を形成するに当たっては，図７に示すごとく，まず，実施形態例１と同様に無電解銅めっき処理を行い，厚み０．０５〜３．００μｍの無電解銅めっき層２１を形成する。
【００３１】
次いで，該無電解銅めっき層２１を電源リードと接続し，無電解銅めっき層２１に通電しながら基板５を電解液の中に浸漬することにより，電解銅めっき層２２を形成できる。これにより，無電解銅めっき層２１及び電解銅めっき層２２からなる表面めっき層２０が形成される。
本例のプリント配線板８１を製造するに当たって，その他の点については，実施形態例１と同様である。
本例においても，実施形態例１と同様の効果を得ることができる。
【００３２】
実施形態例４
本例においては，底面金属めっき層を電解銅めっき処理により形成した点が，無電解銅めっき処理により底面金属めっき層を形成した実施形態例３の場合と相違する。
電解銅めっき処理は，実施形態例２と同様の方法により行う。その他は，実施形態例３と同様である。
本例においても，実施形態例３と同様の効果を得ることができる。
【００３３】
【発明の効果】
本発明によれば，ブラインドビアホールと内層回路との接続信頼性に優れたプリント配線板の製造方法を提供することができる。
【図面の簡単な説明】
【図１】実施形態例１のプリント配線板の断面図。
【図２】実施形態例１のプリント配線板の製造方法における，絶縁層に開口穴を形成した基板の断面図。
【図３】図２に続く，絶縁層に粗化面を形成した基板の断面図。
【図４】図３に続く，開口穴の底面に底面金属めっき層を形成した基板の断面図。
【図５】図４に続く，絶縁層の粗化面に触媒核を付着させた基板の断面図。
【図６】図５に続く，外層回路未形成部分にレジスト膜を形成した基板の断面図。
【図７】実施形態例３のプリント配線板の断面図。
【図８】従来例におけるプリント配線板の断面図。
【図９】従来例におけるプリント配線板の製造方法において，フォトリソブラフィにより開口穴を形成する方法を示すための基板の断面図。
【図１０】従来例の問題点を示すためのプリント配線板の断面図。
【符号の説明】
１．．．底面金属めっき層，
２．．．表面めっき層，
３１．．．内層回路，
３２．．．ブラインドビアホール，
３３．．．外層回路，
５．．．基板，
６．．．絶縁層，
６１．．．開口穴，
６２．．．アンダーカット部，
７．．．レジスト膜，
８，８１．．．プリント配線板，[0001]
【Technical field】
The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a connection between a blind via hole and an inner layer circuit.
[0002]
[Prior art]
Conventionally, as a printed wiring board, for example, as shown in FIG. 8, there is one in which an insulating layer 96 is provided on the surface of a substrate 95 and an inner layer circuit 931 is provided therebetween. The inner layer circuit 931 is connected to an outer layer circuit 933 provided on the surface of the insulating layer 96 through a blind via hole 932 provided in the insulating layer 96.
[0003]
In manufacturing the printed wiring board 9, an inner layer circuit 931 is formed on the surface of the substrate 95 as shown in FIG. Next, an insulating layer 96 made of a photosensitive resin is formed on the surface of the substrate 95.
Next, an opening hole 961 is formed in the insulating layer 95 by photolithography. That is, on the surface of the insulating layer 95, the photomask 4 including the light blocking portion 41 and the light transmitting portion 42 that covers the blind via hole forming portion is disposed. Exposure light is irradiated from above the photomask 4. Thereby, the insulating layer 96 other than the blind via hole forming portion is cured by the exposure light passing through the light transmitting portion 42, while the blind via hole forming portion of the insulating layer 96 located below the light blocking portion 41 is not cured.
[0004]
Next, the photomask 4 is removed, the insulating layer 96 is developed, and the insulating layer 96 in the blind via hole forming portion is removed. As a result, an opening hole 961 for forming a blind via hole is formed in the insulating layer 96.
[0005]
Next, as shown in FIG. 10, a blind via hole 932 and an outer layer circuit 933 are formed by a full additive method. That is, the resist film 97 is coated on the surface of the insulating layer 96 other than the outer layer circuit. Next, an electroless plating process is performed to form a surface plating layer 92 on the surface of the insulating layer 96 and the inner wall of the opening hole 961. As a result, an outer layer circuit 933 is formed on the surface of the insulating layer 96 and the inner wall of the opening hole 961 is covered with the surface plating layer 92 to form a blind via hole 932.
The printed wiring board 9 is obtained as described above.
[0006]
[Problems to be solved]
However, in the conventional method for manufacturing a printed wiring board, as shown in FIG. 9, when the insulating layer 96 is exposed, exposure light wraps around the insulating layer 96 so as to move away from the light blocking portion 42. Therefore, the insulating layer 96 has a tapered unexposed portion extending from the top to the bottom. When the insulating layer 96 is developed, the tapered unexposed portion is removed, and a tapered opening hole 961 is formed in the insulating layer 96.
[0007]
As shown in FIG. 10, the lower portion of the tapered opening hole 961 is wider than the upper portion of the opening hole 961 and becomes an undercut portion 962 having a taper angle larger than the taper angle above the opening hole. When the surface plating layer 92 is formed in the opening hole 961 by electroless plating, the surface plating layer 92 often becomes locally thin at the undercut portion 962. Therefore, connection failure between the surface plating layer 92 and the inner layer circuit 931 occurs, and the connection reliability of the blind via hole 932 is low.
[0008]
Further, when electroplating is performed instead of electroless plating, the surface plating layer 92 may be locally thinned at the undercut portion 962 as in the case of performing electroless plating. The connection reliability of the blind via hole 932 is low.
[0009]
SUMMARY OF THE INVENTION In view of the conventional problems, the present invention is intended to provide a method for manufacturing a printed wiring board excellent in connection reliability between a blind via hole and an inner layer circuit.
[0010]
[Means for solving problems]
According to the first aspect of the present invention, an inner layer circuit is formed on the surface of the substrate, and an undercut portion having a taper angle larger than the upper taper angle is formed below the opening hole on the surface of the substrate. In a method of manufacturing a printed wiring board for forming an insulating layer having a blind via hole,
A bottom metal plating layer having a thickness of 3 to 10 μm is applied to the bottom surface of the opening hole outward from the inner layer circuit to the insulating layer, and then a surface plating layer is applied to the side wall of the bottom metal plating layer and the opening hole. is a manufacturing method of the printed wiring board you and forming the blind via hole.
[0011]
The most notable point in the present invention is that a bottom metal plating layer is formed on the surface of the inner layer circuit exposed at the bottom surface of the opening hole for forming the blind via hole, and then the surface of the bottom metal plating layer and the side wall of the opening hole. It is to coat the surface plating layer.
[0012]
The operation and effect of the present invention will be described.
In the present invention, the bottom metal plating layer is formed on the bottom surface of the opening hole where the inner layer circuit is exposed. Therefore, even if an undercut portion having a taper angle larger than the taper angle above the opening hole is formed, the bottom metal plating layer fills the space between the undercut portion and the inner layer circuit.
[0013]
Therefore, by forming a surface plating layer on the surface of the bottom metal plating layer and the side wall of the opening hole, the surface plating layer is formed on the inner wall of the opening hole above the undercut portion. For this reason, the surface plating layer is sufficiently formed also at the cut-back portion between the side wall of the opening hole and the surface of the bottom metal plating layer.
[0014]
Therefore, the surface plating layer is securely connected to the inner layer circuit through the bottom metal plating layer. Therefore, a printed wiring board having excellent connection reliability between the blind via hole and the inner layer circuit can be obtained.
It is easily understood that the above mechanism extends not only to the insulating layer made of a photosensitive resin but also to an insulating layer made of, for example, a thermosetting resin.
[0015]
Next, as in the invention of claim 2, after the bottom metal plating layer is formed, it is preferable to attach catalyst nuclei to the bottom metal plating layer and the side wall of the opening hole, and then apply the surface plating layer. Thereby, a bottom metal plating layer can be formed on the bottom surface of the opening hole. In addition, the surface plating layer can be uniformly and reliably formed.
[0016]
Next, as in the invention of claim 3, the opening hole has, for example, a tapered shape that expands from the upper side to the lower side of the insulating layer. Also in this case, as described above, a blind via hole excellent in connection reliability with the inner layer circuit can be formed.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
A method for manufacturing a printed wiring board according to an embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, the printed wiring board 8 manufactured in this example has an insulating layer 6 on the surface of a substrate 5 and an inner layer circuit 31 provided therebetween. The inner layer circuit 31 is connected to an outer layer circuit 33 provided on the surface of the insulating layer 6 through a blind via hole 32 provided in the insulating layer 6.
[0018]
The blind via hole 32 is obtained by covering the inner wall of the opening hole 61 formed in the insulating layer 6 with the surface plating layer 2. The surface plating layer 2 is connected to the inner layer circuit 31 through the bottom metal plating layer 1.
[0019]
Next, the outline of the method for manufacturing the printed wiring board will be described. First, the insulating layer 6 is formed on the surface of the substrate 5 including the inner layer circuit 31, and then the outer layer circuit 31 is formed outward from the inner layer circuit 31. An opening hole 61 is formed (FIG. 2).
Next, the bottom metal plating layer 1 is applied to the bottom surface of the opening hole 61 (FIG. 4). Next, the surface plating layer 2 is applied to the side wall of the bottom metal plating layer 1 and the opening hole 61 by the full additive method to form the blind via hole 32 in the insulating layer 6 (FIG. 1).
[0020]
Next, a method for manufacturing the printed wiring board will be described in detail.
First, as a starting material, a copper clad laminate is prepared by laminating a copper foil having a thickness of 30 to 40 μm on the surface of a resin substrate. Next, the copper foil is etched into a pattern to form an inner layer circuit 31 on the surface of the substrate 5 as shown in FIG.
Next, the substrate 5 is blackened, and a needle-like blackened layer having a thickness of 0.2 to 3 μm is formed on the surface of the inner layer circuit 31 (not shown).
[0021]
Next, photosensitive insulating resins V1 and V2 are prepared. Each of the insulating resins V1 and V2 contains a bisphenol A epoxy resin and an imidazole-based curing agent, and a silica filler is further added to the insulating resin V1, while an epoxy resin filler is further added to the insulating resin V2. . In a state where these insulating resins V1 and V2 are dissolved in a solvent, they are sequentially applied to the surface of the substrate 5 by a roll coater method and dried by touch.
[0022]
Next, exposure and development are performed according to the photolithography technique described in the conventional example (see FIG. 9), thereby performing the main curing of the insulating layer 6 and forming an opening hole 61 in the insulating layer 6 as shown in FIG. . At this time, a part of the upper surface of the inner layer circuit 31 is exposed from the insulating layer 6. In addition, the opening hole 61 has a tapered shape that expands from the upper side to the lower side of the insulating layer 6, and the bottom part thereof is often an undercut part 62 having the largest taper angle on the side wall of the opening hole 61.
[0023]
Next, the resin filler in the insulating layer 6 is selectively dissolved by treating the substrate 5 with a roughening solution such as chromic acid. Thereby, as shown in FIG. 3, the roughened surface 65 is formed on the surface of the insulating layer 6 and the inner wall of the opening hole 61.
Next, as shown in FIG. 4, the substrate 5 is subjected to electroless copper plating. Thereby, the bottom metal plating layer 1 having a thickness of 3 to 10 μm is formed on the inner layer circuit 31 exposed from the bottom surface of the opening hole 61. In addition, since the catalyst core for plating does not adhere to the side wall of the opening hole 61, the bottom metal plating layer is not formed.
[0024]
In addition, when the thickness of the bottom metal plating layer 1 is less than 3 μm, when the surface plating layer is formed on the surface of the bottom metal plating layer, the thickness of the surface plating layer at the undercut portion of the opening hole becomes thin, and the blind via hole There is a risk that the reliability of electrical connection between the inner layer circuit and the inner layer circuit is lowered. On the other hand, when the thickness exceeds 10 μm, there is no problem in terms of electrical connection reliability, but there is a possibility that the cost of electroless copper plating may be increased.
[0025]
Next, the substrate is immersed in a catalyst solution containing Pd, and Pd-based catalyst nuclei 66 are imparted to the roughened surface 65 as shown in FIG. Next, as shown in FIG. 6, a resist film 7 is formed on the surface of the insulating layer 6 where the outer layer circuit is not formed.
[0026]
Next, an electroless copper plating process is performed on the substrate. As shown in FIG. 1, a surface plating layer 2 having a thickness of 20 μm is applied to the side wall of the bottom metal plating layer 1 and the opening hole 61, and the insulating layer 6 is formed. Blind via holes 32 are formed.
Thus, the printed wiring board 8 shown in FIG. 1 is obtained.
[0027]
Next, the operation and effect of this example will be described.
In this example, as shown in FIG. 4, the bottom metal plating layer 1 is formed on the bottom surface of the opening hole 61 exposing the inner layer circuit 31. Therefore, even if the undercut portion 62 having a taper angle larger than the upper taper angle is formed below the opening hole 61, the bottom metal plating layer 1 is located between the undercut portion 62 and the inner layer circuit 31. Fill.
[0028]
Therefore, as shown in FIG. 1, by forming the surface plating layer 2 on the surface of the bottom metal plating layer 1 and the side wall of the opening hole 61, the surface plating layer 2 is formed in the opening hole 61 above the undercut portion. Formed on the inner wall. For this reason, the surface plating layer 2 is sufficiently formed also at the turned-back portion between the side wall of the opening hole 61 and the surface of the bottom metal plating layer 1.
Therefore, the surface plating layer 2 is reliably connected to the inner layer circuit 31 via the bottom metal plating layer 1. Therefore, the printed wiring board 8 having excellent connection reliability between the blind via hole 32 and the inner layer circuit 31 can be obtained.
[0029]
Embodiment 2
In this example, the point that the bottom metal plating layer is formed by the electrolytic copper plating process is different from the case of the embodiment 1 formed by the electroless copper plating process.
To perform the electrolytic copper plating process, the bottom metal plating layer can be formed by connecting the inner layer circuit to the power supply lead and immersing the substrate in the electrolyte while energizing the inner layer circuit.
Others are the same as in the first embodiment.
Also in this example, the same effects as those of the first embodiment can be obtained.
[0030]
Embodiment 3
In this example, the point which formed the surface plating layer by the electroless copper plating process and the electrolytic copper plating process is different from the case of Embodiment 1 formed by the electroless copper plating process.
That is, in forming the surface plating layer, as shown in FIG. 7, first, an electroless copper plating process is performed in the same manner as in Embodiment 1 to form an electroless copper plating layer 21 having a thickness of 0.05 to 3.00 μm. Form.
[0031]
Subsequently, the electroless copper plating layer 21 is formed by connecting the electroless copper plating layer 21 to the power supply lead and immersing the substrate 5 in the electrolytic solution while energizing the electroless copper plating layer 21. Thereby, the surface plating layer 20 which consists of the electroless copper plating layer 21 and the electrolytic copper plating layer 22 is formed.
In manufacturing the printed wiring board 81 of this example, the other points are the same as those of the first embodiment.
Also in this example, the same effects as those of the first embodiment can be obtained.
[0032]
Embodiment 4
In this example, the point that the bottom metal plating layer is formed by electrolytic copper plating is different from the third embodiment in which the bottom metal plating layer is formed by electroless copper plating.
The electrolytic copper plating process is performed by the same method as in the second embodiment. Others are the same as the third embodiment.
Also in this example, the same effect as in the third embodiment can be obtained.
[0033]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the printed wiring board excellent in the connection reliability of a blind via hole and an inner layer circuit can be provided.
[Brief description of the drawings]
1 is a cross-sectional view of a printed wiring board according to Embodiment 1;
2 is a cross-sectional view of a substrate in which an opening hole is formed in an insulating layer in the method for manufacturing a printed wiring board according to Embodiment 1. FIG.
3 is a cross-sectional view of a substrate having a roughened surface formed on an insulating layer, continued from FIG. 2;
4 is a cross-sectional view of a substrate on which a bottom metal plating layer is formed on the bottom surface of the opening hole, following FIG. 3;
FIG. 5 is a cross-sectional view of a substrate with catalyst nuclei attached to the roughened surface of the insulating layer, following FIG. 4;
6 is a cross-sectional view of a substrate on which a resist film is formed in a portion where an outer layer circuit is not formed, continued from FIG. 5;
7 is a cross-sectional view of a printed wiring board according to Embodiment 3. FIG.
FIG. 8 is a cross-sectional view of a printed wiring board in a conventional example.
FIG. 9 is a cross-sectional view of a substrate for illustrating a method of forming an opening hole by photolithography in a method for manufacturing a printed wiring board in a conventional example.
FIG. 10 is a cross-sectional view of a printed wiring board for illustrating problems of a conventional example.
[Explanation of symbols]
1. . . Bottom metal plating layer,
2. . . Surface plating layer,
31. . . Inner layer circuit,
32. . . Blind via hole,
33. . . Outer layer circuit,
5). . . substrate,
6). . . Insulation layer,
61. . . Opening hole,
62. . . Undercut,
7). . . Resist film,
8,81. . . Printed wiring board,

Claims (3)

基板の表面に内層回路を形成し，次いで，上記基板の表面に，開口穴の下方に，上方のテーパ角度よりも大きいテーパ角度を有するアンダーカット部を有してなるブラインドビアホールを有する絶縁層を形成するプリント配線板の製造方法において，
上記絶縁層に対して上記内層回路から外方に向かう開口穴の底面に厚み３〜１０μｍの底面金属めっき層を施し，次いで，該底面金属めっき層及び開口穴の側壁に表面めっき層を施して上記ブラインドビアホールを形成することを特徴とするプリント配線板の製造方法。An inner layer circuit is formed on the surface of the substrate, and then an insulating layer having a blind via hole having an undercut portion having a taper angle larger than the upper taper angle below the opening hole is formed on the surface of the substrate. In the manufacturing method of the printed wiring board to be formed,
A bottom metal plating layer having a thickness of 3 to 10 μm is applied to the bottom surface of the opening hole outward from the inner layer circuit to the insulating layer, and then a surface plating layer is applied to the side wall of the bottom metal plating layer and the opening hole. A method of manufacturing a printed wiring board, wherein the blind via hole is formed. 請求項１において，上記底面金属めっき層を形成した後には，底面金属めっき層及び開口穴の側壁に触媒核を付着させ，その後上記表面めっき層を施すことを特徴とするプリント配線板の製造方法。  2. The method of manufacturing a printed wiring board according to claim 1, wherein after the bottom metal plating layer is formed, catalyst nuclei are attached to the bottom metal plating layer and the side wall of the opening hole, and then the surface plating layer is applied. . 請求項１又は２において，上記開口穴は，絶縁層の下方に向かうに従って，その径が拡大していることを特徴とするプリント配線板の製造方法。  3. The method of manufacturing a printed wiring board according to claim 1, wherein the diameter of the opening hole increases toward the lower side of the insulating layer.
JP22775196A 1996-08-08 1996-08-08 Method for manufacturing printed wiring board Expired - Lifetime JP3890631B2 (en)

Priority Applications (1)

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US7776199B2 (en) 2003-08-12 2010-08-17 Fujikura Ltd. Printed wiring board and production method thereof
JP2006202980A (en) * 2005-01-20 2006-08-03 Hitachi Chem Co Ltd Multilayer interconnection board and its manufacturing method
CN102045939B (en) * 2009-10-19 2014-04-30 巨擘科技股份有限公司 Metal layer structure of flexible multilayer base plate and preparation method thereof
CN103298251B (en) * 2013-05-23 2016-05-25 华为技术有限公司 A kind of printed circuit board (PCB) and preparation method thereof
CN104684279A (en) * 2013-11-27 2015-06-03 深圳崇达多层线路板有限公司 Processing method of blind hole in printed wiring board
CN107580426A (en) * 2016-07-04 2018-01-12 北大方正集团有限公司 The preparation method and PCB interconnected between PCB layer

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