JP2984625B2 - Multilayer printed wiring board manufacturing method - Google Patents
Multilayer printed wiring board manufacturing methodInfo
- Publication number
- JP2984625B2 JP2984625B2 JP9151106A JP15110697A JP2984625B2 JP 2984625 B2 JP2984625 B2 JP 2984625B2 JP 9151106 A JP9151106 A JP 9151106A JP 15110697 A JP15110697 A JP 15110697A JP 2984625 B2 JP2984625 B2 JP 2984625B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- insulating
- conductive circuit
- opening
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は多層プリント配線板
製造方法に関し、特にビルドアップ工法を用いた多層プ
リント配線板製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board using a build-up method.
【0002】[0002]
【従来の技術】電子機器の小型化・高性能化が進展する
中で電子部品を実装する多層プリント配線板の高密度配
線が要求されており、その高密度配線を形成する方法と
して絶縁基板上に絶縁樹脂と導電回路を交互に形成し、
バイアホールで層間接続するビルドアップ工法の多層プ
リント配線板の製造方法が開示されている。この多層プ
リント配線板の電子部品の薄型高密度実装を達成するた
めに、多層プリント配線板の表面に開口部を設け、この
開口部に電子部品をボンデイング実装することも行われ
ている。2. Description of the Related Art As electronic devices have become smaller and have higher performance, high-density wiring of multilayer printed wiring boards on which electronic components are mounted has been demanded. Insulating resin and conductive circuit are alternately formed on
A method of manufacturing a multilayer printed wiring board of a build-up method in which interlayer connection is performed by via holes is disclosed. In order to achieve thin and high-density mounting of electronic components on the multilayer printed wiring board, an opening is provided on the surface of the multilayer printed wiring board, and the electronic component is bonded and mounted in the opening.
【0003】この従来の開口部を有する多層プリント配
線板の製造方法について、図3を参照して説明する。導
電回路2が形成されたエポキシガラス材料等の絶縁基板
1上(図3(a))の開ロ部になる部分のパッド3上の
みに金めっきを施し、ボンデイングパッド部4を形成す
る(図3(b))。この金めっきは後工程のエッチング
時の金属レジストと実装時のパッド3のボンデイング用
表面処理の二つの目的で行う。金めっきはホウ化水素塩
を還元剤とする無電解金めっき浴を使用して約0.3μ
m程度の厚さの金めっき膜がボンデイングパッド部4に
被覆される。A conventional method for manufacturing a multilayer printed wiring board having openings will be described with reference to FIG. Gold plating is performed only on the pad 3 that is to be the open portion on the insulating substrate 1 such as an epoxy glass material on which the conductive circuit 2 is formed (FIG. 3A) to form a bonding pad portion 4 (FIG. 3 (b)). This gold plating is performed for two purposes: a metal resist at the time of etching in a later step and a surface treatment for bonding of the pad 3 at the time of mounting. Gold plating is about 0.3μ using an electroless gold plating bath using borohydride as a reducing agent.
A gold plating film having a thickness of about m is coated on the bonding pad portion 4.
【0004】次に、酸性塩化第二銅水溶液で導電回路2
表面を粗面後、アルカリ性過硫酸カリウム水溶液等で導
電回路表面を酸化し、酸化銅5を形成する(図3
(c))。この酸化銅形成は導電回路とその上にビルド
アップする絶縁樹脂との密着を向上させるため使用され
る。Next, a conductive circuit 2 is formed using an aqueous cupric acid chloride solution.
After roughening the surface, the conductive circuit surface is oxidized with an alkaline potassium persulfate aqueous solution or the like to form copper oxide 5 (FIG. 3).
(C)). This copper oxide formation is used to improve the adhesion between the conductive circuit and the insulating resin built up thereon.
【0005】次に、図3(d)の如く絶縁基板1上に感
光性液状樹脂(光硬化性と熱硬化性の両成分を含む)を
数十μm厚さに塗布して乾燥し、絶縁層13を形成す
る。次いでマスクフィルムを使用して紫外線を照射し、
開口部7及びバイアホール部8以外の絶縁層13表面を
光硬化後現像し、開口部7およびバイアホール8を形成
する(図3(e))。Next, as shown in FIG. 3D, a photosensitive liquid resin (including both photo-curable and thermo-curable components) is applied to the insulating substrate 1 to a thickness of several tens μm and dried. The layer 13 is formed. Then irradiate with ultraviolet light using a mask film,
The surface of the insulating layer 13 other than the opening 7 and the via hole 8 is photo-cured and then developed to form the opening 7 and the via hole 8 (FIG. 3E).
【0006】次に熱硬化(130℃、2H)後、絶縁層1
3表面を機械研磨し、過マンガン酸塩水溶液で粗化後、
銅めっきを行った後エッチングし、導電回路11を形成
し開口部7およびバイアホール8を有する多層プリント
配線板12が完成する(図3(f))。なお、開口部7
は座繰り部とも呼ばれる。Next, after heat curing (130 ° C., 2H), the insulating layer 1
3 After mechanical polishing the surface and roughening with permanganate aqueous solution,
After copper plating, etching is performed to form a conductive circuit 11, and a multilayer printed wiring board 12 having openings 7 and via holes 8 is completed (FIG. 3F). The opening 7
Is also called a counterbore.
【0007】[0007]
【発明が解決しようとする課題】上記従来技術の問題点
は、絶縁層13に開口部7を形成し、熱硬化後、絶縁層
13の表面を銅めっきの絶縁層13との密着力を向上さ
せるために機械研磨する際に、ボンデイングパッド部4
が機械研磨のバフ等で研磨され欠損される不具合が生じ
やすいことである。このために、ボンデイングパッド部
4にボンデイングできないことがしばしば起こってい
た。The problem with the prior art described above is that the opening 7 is formed in the insulating layer 13 and, after thermosetting, the surface of the insulating layer 13 is improved in adhesion to the copper-plated insulating layer 13. When mechanical polishing is performed to prevent the bonding pad portion 4
Is liable to be polished by a mechanical polishing buff or the like, resulting in a defect. For this reason, it often happens that the bonding pad portion 4 cannot be bonded.
【0008】[0008]
【課題を解決するための手段】本発明の目的は、上記従
来技術の問題点を解決した多層プリント配線板の製造方
法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a multilayer printed wiring board which solves the above-mentioned problems of the prior art.
【0009】本発明の多層プリント配線板の製造方法
は、絶縁基板上に導電回路を形成する工程と、前記導電
回路の所望回路に部分的に金めっきしてボンデイングパ
ッド部を形成する工程と、前記導電回路のボンデイング
パッド部を除く表面を粗面化する工程と、前記絶縁基板
上に感光性絶縁樹脂を塗布し第1の絶縁層を形成する工
程と、前記第1の絶縁層表面を露光・現像し、前記絶縁
層のボンデイングパッド部表面が露出するように開口部
と前記導電回路の所望回路上にバイアホールとを形成す
る工程と、前記開口部に感光性絶縁樹脂を充填塗布し第
2の絶縁層を形成し露光する工程と、前記第1の絶縁層
および第2の絶縁層表面を機械研磨後化学粗化する工程
と、めっき・エッチングにより前記第1の絶縁層上と前
記バイアホールに導電回路を形成する工程と、前記第2
の絶縁層を除去する工程とを有する構成からなる。The method of manufacturing a multilayer printed wiring board according to the present invention comprises the steps of forming a conductive circuit on an insulating substrate; forming a bonding pad portion by partially plating a desired circuit of the conductive circuit with gold; Roughening the surface of the conductive circuit excluding the bonding pad portion, applying a photosensitive insulating resin on the insulating substrate to form a first insulating layer, and exposing the surface of the first insulating layer Developing and forming an opening and a via hole on a desired circuit of the conductive circuit so that the surface of the bonding pad portion of the insulating layer is exposed; and filling and coating the opening with a photosensitive insulating resin. Forming a second insulating layer and exposing; a step of mechanically polishing and chemically roughening the surfaces of the first insulating layer and the second insulating layer; and a step of plating and etching on the first insulating layer and the via. Led to the hall Forming a circuit, the second
Removing the insulating layer.
【0010】本発明ではボンデイングパッド部の形成さ
れる開口部に感光性絶縁樹脂からなる第2の絶縁層を形
成して研磨を行うためボンデイングバッドが機械的研磨
から保護される。しかも第1の絶縁層が均―に研磨でき
る効果がある。また、第2の絶縁層の光硬化した表面層
は、第1の絶縁層の化学粗化の際、ボンデイングパッド
を保護する作用がある。In the present invention, since the second insulating layer made of a photosensitive insulating resin is formed in the opening where the bonding pad portion is formed and the polishing is performed, the bonding pad is protected from mechanical polishing. In addition, there is an effect that the first insulating layer can be uniformly polished. The photocured surface layer of the second insulating layer has an effect of protecting the bonding pad when the first insulating layer is chemically roughened.
【0011】[0011]
【発明の実施の形態】本発明の実施の形態について、図
1および2を参照して説明する。図1は、本発明の実施
の形態の絶縁基板上の導電回路の形成から第1の絶縁層
に開口部とバイアホールを形成するまでの工程順を説明
する基板要部の拡大断面図である。図2は、本発明の実
施の形態の第1の絶縁層開口部の第2の絶縁層形成から
第1の絶縁層上とバイアホールに導電回路を形成後第2
の絶縁層を除去するまで工程順を説明するための基板要
部の拡大断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an enlarged cross-sectional view of a main part of a substrate, illustrating a process sequence from formation of a conductive circuit on an insulating substrate to formation of an opening and a via hole in a first insulating layer according to an embodiment of the present invention. . FIG. 2 is a cross-sectional view of the first embodiment after forming a conductive circuit on the first insulating layer and the via hole from the formation of the second insulating layer in the opening of the first insulating layer according to the embodiment of the present invention.
FIG. 4 is an enlarged cross-sectional view of a main part of a substrate for explaining a process order until an insulating layer is removed.
【0012】まず、エポキシガラス材料等の絶縁基板1
上に導電回路2を従来の印刷エッチング技術を使用して
形成する(図1(a))。導電回路2でボンデイングす
る回路をパッド3で示す。なお、絶縁基板1の導電回路
の銅箔は、18μmや35μmの厚さのものを使用でき
る。次いで、パッド3のボンデイングする部分に金めっ
きしてボンデイングパッド部4を形成する(図1
(b))。金めっきは無電解金めっき浴(KAu(C
N)2 :0.86g/l、KCN:6.5g/l、KO
H:11.2g/l、KBH4 :10.8g/l)に7
0℃で15分間浸漬し、約0.3μm厚さの金めっき膜
を形成する。First, an insulating substrate 1 made of an epoxy glass material or the like is used.
A conductive circuit 2 is formed thereon using a conventional print etching technique (FIG. 1A). A circuit to be bonded by the conductive circuit 2 is indicated by a pad 3. The copper foil of the conductive circuit of the insulating substrate 1 may have a thickness of 18 μm or 35 μm. Next, the bonding portion of the pad 3 is plated with gold to form a bonding pad portion 4 (FIG. 1).
(B)). Gold plating is electroless gold plating bath (KAu (C
N) 2 : 0.86 g / l, KCN: 6.5 g / l, KO
H: 11.2 g / l, KBH 4 : 10.8 g / l)
Immersion at 0 ° C. for 15 minutes to form a gold plating film having a thickness of about 0.3 μm.
【0013】次に、酸性塩化第二銅水溶液で金めっきし
たボンデイングパッド部4を除くパッド3とその他の導
電回路2表面を粗面後、アルカリ性過硫酸カリウム水溶
液で処理して酸化銅5を形成する。酸化銅5形成には、
アルカリ性亜塩素酸ナトリウムや硫化カリ−塩化アンモ
ニア水溶液等を使用してもよい。この酸化銅5の形成は
上記従来技術と同様に導電回路と絶縁層の密着を向上さ
せるために行う。Next, the surface of the pad 3 and the surface of the other conductive circuit 2 except for the bonding pad portion 4 plated with gold with an aqueous solution of acidic cupric chloride are roughened, and then treated with an aqueous solution of alkaline potassium persulfate to form copper oxide 5. I do. To form copper oxide 5,
Alkaline sodium chlorite, potassium sulfide-ammonia chloride aqueous solution or the like may be used. The formation of the copper oxide 5 is performed in order to improve the adhesion between the conductive circuit and the insulating layer as in the above-described conventional technique.
【0014】次に、カーテンコーターを使用し、エポキ
シ樹脂を主成分とする液状の感光性絶縁樹脂を絶縁基板
1上に塗布し、温度90℃で60分間指触乾燥して厚さ
約60μmの第1の絶縁層6を形成する(図1
(d))。この感光性絶縁樹脂は、光硬化性と熱硬化性
の両成分を含み、130℃で2時間程度熱硬化すると現
像できなくなる特性を持つ。感光性絶縁樹脂の塗布は、
ロールコーターやスクリーン印刷等の方法を使用しても
よい。Next, using a curtain coater, a liquid photosensitive insulating resin containing an epoxy resin as a main component is applied on the insulating substrate 1 and dried by touching at a temperature of 90 ° C. for 60 minutes to a thickness of about 60 μm. First insulating layer 6 is formed (FIG. 1
(D)). This photosensitive insulating resin contains both photo-curable and thermo-curable components, and has the property of being incapable of developing when thermally cured at 130 ° C. for about 2 hours. The application of photosensitive insulating resin
A method such as a roll coater or screen printing may be used.
【0015】次いで、マスクフイルムを使用して紫外線
を積算露光量で4000〜6000mJ/cm2選択的に
照射し、第1の絶縁層6に開口部7及びバイアホール8
を形成する以外の絶縁層6表面を光硬化後現像し、開口
部7及びバイアホール8を形成する(図1(e))。こ
の紫外線照射で絶縁層6表面は深さ約10μm硬化す
る。次いで、基板を温度130℃で約2時間熱硬化す
る。この熱硬化で絶縁層6は化学的にかなり安定する。Next, using a mask film, ultraviolet rays are selectively irradiated at an integrated exposure dose of 4000 to 6000 mJ / cm 2 , and the opening 7 and the via hole 8 are formed in the first insulating layer 6.
Then, the surface of the insulating layer 6 except for the formation of the photo-curing layer is developed after photo-curing to form an opening 7 and a via hole 8 (FIG. 1E). By this ultraviolet irradiation, the surface of the insulating layer 6 is cured at a depth of about 10 μm. Next, the substrate is thermally cured at a temperature of 130 ° C. for about 2 hours. By this heat curing, the insulating layer 6 is considerably stabilized chemically.
【0016】次に感光性絶縁樹脂をカーテンコーター、
ロールコーター、スクリーン印刷等の方法で基板上に感
光性絶縁樹脂を塗布し、開口部7に第2の絶縁層9を充
填形成する(図2(a))。この感光性絶縁樹脂はエポ
キシ樹脂を主成分とする樹脂で紫外線照射でその表面が
深さ10μm硬化する樹脂が適しており、第1の絶縁樹
脂層と同じ液状の感光性絶縁樹脂を使用してもよい。第
1の絶縁層の表面硬化深さと同じになるように第2の絶
縁層の表面硬化深さを調整することにより後工程の機械
研磨で第1の絶縁層の表面硬化膜を除去する際に、第2
の絶縁層の表面硬化膜を同時に有効に除去できる。な
お、第2の絶縁層を形成する際に感光性絶縁樹脂はバイ
アホール8に開口部と同様に充填してもよい。Next, the photosensitive insulating resin is coated with a curtain coater,
A photosensitive insulating resin is applied on the substrate by a method such as a roll coater or screen printing, and the opening 7 is filled with the second insulating layer 9 (FIG. 2A). As the photosensitive insulating resin, a resin whose main component is an epoxy resin and whose surface is hardened to a depth of 10 μm by ultraviolet irradiation is suitable, and the same liquid photosensitive insulating resin as the first insulating resin layer is used. Is also good. By adjusting the surface hardening depth of the second insulating layer so as to be the same as the surface hardening depth of the first insulating layer, when removing the surface hardened film of the first insulating layer by mechanical polishing in a later process. , Second
The surface hardened film of the insulating layer can be effectively removed at the same time. When forming the second insulating layer, the photosensitive insulating resin may be filled in the via hole 8 in the same manner as the opening.
【0017】次いで、開口部に充填形成した第2の絶縁
層を温度90℃で約60分間指触乾燥後、マスクフィル
ムを使用して紫外線を積算露光量で4000〜6000
mJ/cm2 照射し、第2の絶縁層9の表面を深さ約1
0μm光硬化する。この光硬化後に開口部以外に付着し
た第2の絶縁層形成用の感光性絶縁樹脂を除去を除去す
るために現像してもよい。Next, the second insulating layer filled in the opening is touch-dried at a temperature of 90 ° C. for about 60 minutes, and then irradiated with ultraviolet rays at a cumulative exposure amount of 4000 to 6000 using a mask film.
mJ / cm 2 and irradiate the surface of the second insulating layer 9 to a depth of about 1
Light cured at 0 μm. After the photo-curing, the photosensitive insulating resin for forming the second insulating layer attached to the portion other than the opening may be developed to remove it.
【0018】次にバフ、ベルトサンダー等の方法で、例
えばベルトサンダーで研磨し、第1の絶縁層6および第
2の絶縁層9の表面硬化膜を除去する。ベルトサンダー
で絶縁層を研磨する厚さは、少なくとも第1および第2
の絶縁層の光硬化厚さのどちらかの大きな方の値が必要
であるが、ここでは表面硬化膜を完全に除去するため
に、この機械研磨の樹脂研磨深さは約20μmに設定し
た。この機械研磨の際、パッド3は第2の絶縁層9によ
り保護されているため研磨されることはない。次にアル
カリ性過マンガン酸塩水溶液(KMnO4 :40〜60
g/l、アルカリ規定度:1.0〜1.2N、液温:60
〜80℃)で化学的に粗化し、硫酸酸性の還元剤で中和
する。第1の絶縁層6および第2の絶縁層9の表面に
は、粗化面10が形成される(図2(b))。Next, the surface hardened films of the first insulating layer 6 and the second insulating layer 9 are removed by polishing, for example, with a belt sander using a method such as a buff or a belt sander. The thickness at which the insulating layer is polished with the belt sander is at least the first and second.
In this case, the resin polishing depth of the mechanical polishing was set to about 20 μm in order to completely remove the surface cured film. During this mechanical polishing, the pad 3 is not polished because it is protected by the second insulating layer 9. Then an alkaline permanganate aqueous solution (KMnO 4: 40 to 60
g / l, alkali normality: 1.0 to 1.2 N, liquid temperature: 60
-80 ° C) and neutralized with a sulfuric acid reducing agent. A roughened surface 10 is formed on the surfaces of the first insulating layer 6 and the second insulating layer 9 (FIG. 2B).
【0019】次いで無電解めっきおよび電気銅めっきを
行い約20μmの導電層を形成後、塩化第二鉄等でエッ
チングし、導電回路11を形成する(図2(c))。更
に、現像して第2の絶縁層9を除去し、バッド3のボン
デイングパッド部4を露出させ、開口部(座繰り部)7
およびバイアホール8を有する多層プリント配線板12
を得る(図2(d))。Next, electroless plating and electrolytic copper plating are performed to form a conductive layer having a thickness of about 20 μm, followed by etching with ferric chloride or the like to form a conductive circuit 11 (FIG. 2C). Further, the second insulating layer 9 is removed by development to expose the bonding pad portion 4 of the pad 3, and the opening (counterbore portion) 7 is formed.
Printed wiring board 12 having via holes 8
Is obtained (FIG. 2D).
【0020】[0020]
【発明の効果】本発明の第1の効果は、ボンデイングパ
ッド部の形成される開口部に感光性絶縁樹脂からなる第
2の絶縁層を形成して研磨を行うためボンデイングバッ
ドが機械的研磨から保護されるためボンデイングの信頼
性を向上できることである。A first effect of the present invention is that a second insulating layer made of a photosensitive insulating resin is formed in an opening where a bonding pad portion is formed, and polishing is performed. Because it is protected, the reliability of the bonding can be improved.
【0021】本発明の第2の効果は、開口部が第2の絶
縁層で充填され基板表面が平坦化するため第1の絶縁層
が均―に研磨できる効果がある。The second effect of the present invention is that the opening is filled with the second insulating layer and the substrate surface is flattened, so that the first insulating layer can be uniformly polished.
【図1】本発明の実施の形態の絶縁基板上の導電回路の
形成から第1の絶縁層に開口部とバイアホールを形成す
るまでの工程を説明する基板要部の拡大断面図であるFIG. 1 is an enlarged cross-sectional view of a main part of a substrate, illustrating a process from forming a conductive circuit on an insulating substrate to forming an opening and a via hole in a first insulating layer according to an embodiment of the present invention.
【図2】本発明の実施の形態の第1の絶縁層開口部に第
2の絶縁層充填形成から第1の絶縁層上とバイアホール
に導電回路を形成後第2の絶縁層を除去するまで工程順
を説明するための基板要部の拡大断面図である。FIG. 2 is a diagram showing an embodiment of the present invention, in which a second insulating layer is filled in a first insulating layer opening, a conductive circuit is formed on the first insulating layer and a via hole, and then the second insulating layer is removed. It is an expanded sectional view of the important section of a substrate for explaining a process order until.
【図3】従来の開口部を有する多層プリント配線板の製
造方法の工程順を説明するための基板要部の断面図であ
る。FIG. 3 is a cross-sectional view of a main part of a substrate for describing a process sequence of a conventional method for manufacturing a multilayer printed wiring board having openings.
1 絶縁基板 2 導電回路 3 パッド 4 ボンデイングパッド部 5 酸化銅 6 第1の絶縁層 7 開口部 8 バイアホ―ル 9 第2の絶縁層 10 粗化面 11 導電回路 12 多層プリント配線板 13 絶縁層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Conductive circuit 3 Pad 4 Bonding pad part 5 Copper oxide 6 First insulating layer 7 Opening 8 Via hole 9 Second insulating layer 10 Roughened surface 11 Conductive circuit 12 Multilayer printed wiring board 13 Insulating layer
Claims (3)
と、前記導電回路の所望回路に部分的に金めっきしてボ
ンデイングパッド部を形成する工程と、前記導電回路の
ボンデイングパッド部を除く表面を粗面化する工程と、
前記絶縁基板上に感光性絶縁樹脂を塗布し第1の絶縁層
を形成する工程と、前記第1の絶縁層表面の所望の部分
を露光硬化後現像し、前記絶縁層のボンデイングパッド
部表面が露出するように開口部と前記導電回路の所望回
路上にバイアホールとを形成する工程と、前記開口部に
感光性絶縁樹脂を充填塗布し第2の絶縁層を形成し露光
硬化する工程と、前記第1の絶縁層および第2の絶縁層
表面を機械研磨後化学粗化する工程と、前記第1の絶縁
層上と前記バイアホールに導電回路を形成する工程と、
前記第2の絶縁層を除去する工程とを有することを特徴
とする多層プリント配線板製造方法。1. A step of forming a conductive circuit on an insulating substrate, a step of forming a bonding pad portion by partially plating a desired circuit of the conductive circuit with gold, and a surface excluding the bonding pad portion of the conductive circuit. Surface roughening;
Applying a photosensitive insulating resin on the insulating substrate to form a first insulating layer; and exposing and curing a desired portion of the surface of the first insulating layer and developing the exposed portion. Forming an opening so as to be exposed and a via hole on a desired circuit of the conductive circuit, filling and coating the opening with a photosensitive insulating resin to form a second insulating layer, and exposing and hardening; A step of chemically polishing and roughening the surfaces of the first and second insulating layers, and a step of forming a conductive circuit on the first insulating layer and in the via hole;
Removing the second insulating layer.
1の絶縁層の露光硬化深さと同一である請求項1記載の
多層プリント配線板製造方法。2. The method according to claim 1, wherein the exposure hardening depth of the second insulating layer is the same as the exposure hardening depth of the first insulating layer.
厚さが少なくとも前記第1及び第2の絶縁層の露光硬化
の深さのどちらか大きな方の値である請求項1記載の多
層プリント配線板製造方法。3. The mechanical polishing thickness of the first and second insulating layers is at least the greater of the exposure hardening depths of the first and second insulating layers. Production method of multilayer printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9151106A JP2984625B2 (en) | 1997-06-09 | 1997-06-09 | Multilayer printed wiring board manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9151106A JP2984625B2 (en) | 1997-06-09 | 1997-06-09 | Multilayer printed wiring board manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10341081A JPH10341081A (en) | 1998-12-22 |
JP2984625B2 true JP2984625B2 (en) | 1999-11-29 |
Family
ID=15511489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9151106A Expired - Fee Related JP2984625B2 (en) | 1997-06-09 | 1997-06-09 | Multilayer printed wiring board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2984625B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4028863B2 (en) | 2004-09-10 | 2007-12-26 | 富士通株式会社 | Substrate manufacturing method |
US7772501B2 (en) | 2006-04-25 | 2010-08-10 | Molex Incorporated | Flexible printed circuit board |
-
1997
- 1997-06-09 JP JP9151106A patent/JP2984625B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH10341081A (en) | 1998-12-22 |
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