JPH07297547A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH07297547A
JPH07297547A JP8159194A JP8159194A JPH07297547A JP H07297547 A JPH07297547 A JP H07297547A JP 8159194 A JP8159194 A JP 8159194A JP 8159194 A JP8159194 A JP 8159194A JP H07297547 A JPH07297547 A JP H07297547A
Authority
JP
Japan
Prior art keywords
insulating layer
printed wiring
wiring board
plating
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8159194A
Other languages
Japanese (ja)
Inventor
Masahiro Ikeda
正弘 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8159194A priority Critical patent/JPH07297547A/en
Publication of JPH07297547A publication Critical patent/JPH07297547A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To prevent generation of a haloing phenomenon by conducting selective chemical plating without performing pretreatment on the printed wiring board where a conductive layer is formed by plating. CONSTITUTION:The circuit 2 on a board 1 is made of copper oxide, liquid insulating resin is coated on the substrate 1, the resin is cured, and a via hole 5 is formed. Then, the substrate is dipped into a chemical plating solution without having a pretreatment, a metal film is selectively formed on the via hole part, and the dissolution (haloing phenomenon) of the copper oxide caused by acid can be prevented by forming a mask for a heat treatment to be performed later.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は絶縁層の上にめっきによ
り付加的に導電回路を順次形成する多層印刷配線板の製
造方法に関し、特にバイアホールを有する多層印刷配線
板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board in which conductive circuits are additionally formed sequentially by plating on an insulating layer, and more particularly to a method for manufacturing a multilayer printed wiring board having via holes. is there.

【0002】[0002]

【従来の技術】従来、絶縁層の上にめっきにより付加的
に導電回路を形成し、バイアホールを形成する多層印刷
配線板の製造技術を図3を使用して説明する。
2. Description of the Related Art Conventionally, a manufacturing technique of a multilayer printed wiring board in which a conductive circuit is additionally formed on an insulating layer by plating to form a via hole will be described with reference to FIG.

【0003】エポキシガラス材料等の基板1上に塩化第
二鉄水溶液等で銅箔をエッチングし、導電回路2を形成
する(図3(a))。次いで酸性塩化第二銅水溶液で導
電回路2表面を粗面化後、アルカリ性過硫酸カリウム水
溶液等で導電回路表面を酸化し酸化銅3を形成する(図
3(b)),(b’))。この酸化銅形成は導電回路と
絶縁層の密着を構造させるために印刷配線板に広く使用
されている技術である。
A copper foil is etched with a ferric chloride aqueous solution or the like on a substrate 1 made of an epoxy glass material or the like to form a conductive circuit 2 (FIG. 3 (a)). Then, the surface of the conductive circuit 2 is roughened with an acidic cupric chloride aqueous solution, and then the conductive circuit surface is oxidized with an alkaline potassium persulfate aqueous solution or the like to form copper oxide 3 (FIG. 3 (b)), (b ')). . This copper oxide formation is a technique widely used in printed wiring boards to structure the adhesion between the conductive circuit and the insulating layer.

【0004】次に、図3(c)の如く基板1上に感光性
液状絶縁樹脂等を数十μm厚さに塗布、乾燥し絶縁層4
を形成する。次いで紫外線を照射し、バイアホール形成
以外の絶縁層4表面を硬化後現像し、バイアホール5を
形成する(図3((d))。なお、感光性液状絶縁樹脂
の代わりに熱硬化絶縁樹脂を使用する場合にはバイアホ
ールはレーザ光線を使用して形成することができる。次
に、熱硬化後、過マンガン酸塩水溶液で絶縁樹脂4表面
を化学的に粗化した後、硫酸水溶液等で中和処理する。
絶縁層表面には図3(e)の如く粗化面7が形成され
る。次いで無電解銅めっきと電気銅めっきで導電層8を
形成する(図4)。このような工程を繰り返し多層印刷
配線板が製造される。
Next, as shown in FIG. 3C, a photosensitive liquid insulating resin or the like is applied on the substrate 1 to a thickness of several tens of μm and dried to form an insulating layer 4.
To form. Then, the surface of the insulating layer 4 other than the via hole is cured and developed by ultraviolet irradiation to form a via hole 5 (FIG. 3 (d)). Incidentally, the thermosetting insulating resin is used instead of the photosensitive liquid insulating resin. The via hole can be formed by using a laser beam when used, then, after thermal curing, the surface of the insulating resin 4 is chemically roughened with an aqueous solution of permanganate, and then an aqueous solution of sulfuric acid, etc. Neutralize with.
A roughened surface 7 is formed on the surface of the insulating layer as shown in FIG. Next, the conductive layer 8 is formed by electroless copper plating and electrolytic copper plating (FIG. 4). By repeating such steps, a multilayer printed wiring board is manufactured.

【0005】[0005]

【発明が解決しようとする課題】上述の従来技術におい
ては次のような欠点がある。即ち、バイアホール形成
後、過マンガン酸塩水溶液で絶縁層を処理し硫酸水溶液
で中和する際、バイアホール5下部の導電回路2と絶縁
層4の界面9(図4)において硫酸水溶液の浸入により
導電回路表面の酸化銅3が溶解する現象(ハローイング
現象と呼ばれる)が生ずる。このハローイング現象によ
り絶縁層4がバイアホール下部の導電回路2から剥離す
る問題があった。
The above-mentioned prior art has the following drawbacks. That is, after the via hole is formed, when the insulating layer is treated with a permanganate aqueous solution and neutralized with a sulfuric acid aqueous solution, the sulfuric acid aqueous solution penetrates at the interface 9 (FIG. 4) between the conductive circuit 2 and the insulating layer 4 below the via hole 5. This causes a phenomenon in which the copper oxide 3 on the surface of the conductive circuit is dissolved (called a haloing phenomenon). Due to this haloing phenomenon, there is a problem that the insulating layer 4 is separated from the conductive circuit 2 below the via hole.

【0006】このハローイング現象を防止する方法とし
て導電回路上に酸化銅を形成後その酸化銅全表面を化学
的に還元し、耐酸性を向上させる方法が特公昭64−8
479号公報に述べられている。この方法ではハローイ
ング現象は抑制されるが、特殊な薬品や装置が必要であ
り、導電回路全面を還元処理するために薬品代の増加の
問題があった。本発明の目的はかかる従来の技術の欠点
を解決した多層印刷配線板の製造方法を提供するもので
ある。
As a method for preventing this haloing phenomenon, a method of forming a copper oxide on a conductive circuit and then chemically reducing the entire surface of the copper oxide to improve the acid resistance is disclosed in JP-B-64-8.
No. 479, gazette. Although the haloing phenomenon is suppressed by this method, special chemicals and equipment are required, and the reduction of the entire surface of the conductive circuit causes an increase in the chemical cost. An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board, which solves the drawbacks of the prior art.

【0007】[0007]

【課題を解決するための手段】本発明は基板上に形成さ
れた導電回路表面に酸化銅を形成後、絶縁層を形成する
工程と絶縁層に所望の導電回路に貫通するバイアホール
を形成する工程とバイアホール下部の導電回路表面に無
電解めっきする工程と絶縁層表面をアルカリ性過マンガ
ン酸塩水溶液で処理する工程と前記絶縁層表面にめっき
により銅電層を形成する工程を含む多層印刷配線板の製
造方法を提供する。
According to the present invention, after forming copper oxide on the surface of a conductive circuit formed on a substrate, a step of forming an insulating layer and forming a via hole penetrating a desired conductive circuit in the insulating layer. Multi-layer printed wiring including a step, electroless plating on the surface of the conductive circuit under the via hole, a step of treating the insulating layer surface with an aqueous alkaline permanganate solution, and a step of forming a copper electrolytic layer on the insulating layer surface by plating A method for manufacturing a plate is provided.

【0008】[0008]

【実施例】【Example】

(A)エポキシガラス材料等の基板1上に塩化第二鉄水
溶液等で銅箔をエッチングし、導電回路2を形成する
(図1(a))。次いで酸性塩化第二銅水溶液で導電回
路2表面を粗面化後、アルカリ性過硫酸カリウム水溶
液、アルカリ性亜鉛素酸ナトリウム、硫化カリー塩化ア
ンモニア水溶液等例えばアルカリ性過硫酸カリウム水溶
液で導電回路表面を酸化し酸化銅3を形成する(図1
(b),(b’))。
(A) A copper foil is etched with a ferric chloride aqueous solution or the like on a substrate 1 made of an epoxy glass material or the like to form a conductive circuit 2 (FIG. 1A). Then, after roughening the surface of the conductive circuit 2 with an acidic cupric chloride aqueous solution, the conductive circuit surface is oxidized by oxidizing with an alkaline potassium persulfate aqueous solution, an alkaline sodium zincate solution, an aqueous solution of ammonium sulfide ammonium chloride, etc. Copper 3 is formed (Fig. 1
(B), (b ')).

【0009】(B)次に感光性液状絶縁樹脂をカーテン
コーター、ロールコーター、スクリーン印刷等の方法で
上記基板1上に数十μm厚に塗布す。例えばカーテンコ
ーターで70μm厚に塗布し、指触乾燥(90℃、1時
間)して絶縁層4を形成する(図1(c))。
(B) Next, a photosensitive liquid insulating resin is applied to the substrate 1 in a thickness of several tens of μm by a method such as a curtain coater, a roll coater or screen printing. For example, it is applied with a curtain coater to a thickness of 70 μm and dried by touch with the finger (90 ° C., 1 hour) to form the insulating layer 4 (FIG. 1C).

【0010】(C)次いで紫外線(積算露光量4000
〜6000mJ)を照射して光硬化させ、バイアホール
形成以外の絶縁層4表面を硬化後現像し、バイアホール
5(ビア径0.1mm以上)を形成し(図1(d))、
熱硬化(140℃、1時間)を行う。
(C) Next, ultraviolet rays (integrated exposure amount 4000
˜6000 mJ) to be photo-cured, and the surface of the insulating layer 4 other than the formation of via holes is cured and then developed to form via holes 5 (via diameter 0.1 mm or more) (FIG. 1 (d)).
Heat cure (140 ° C., 1 hour).

【0011】(D)次に、無電解めっき液中(Cu:2
〜3g/l、NaOH:9〜12g/lホルムアルデヒ
ド、(HCHO):3〜6g/l、pH:12〜14)
に約20分浸漬し、バイアホール部に選択的に約0.3
〜0.6μm厚さに銅めっき6を形成する(図1
(e))。この処理において酸化銅3の表面がHCHO
により銅に還元されると同時にめっきが付く。
(D) Next, in an electroless plating solution (Cu: 2
~ 3 g / l, NaOH: 9-12 g / l formaldehyde, (HCHO): 3-6 g / l, pH: 12-14)
Soak for about 20 minutes in the via hole to selectively remove about 0.3
Copper plating 6 is formed to a thickness of 0.6 μm (see FIG. 1).
(E)). In this treatment, the surface of the copper oxide 3 is HCHO.
As a result, it is reduced to copper and plated at the same time.

【0012】(E)ベルトサンダー、ジェットスクラ
ブ、バフ等、例えばベルトサンダーにより絶縁層4の表
面を約20μm研磨し、アルカリ性過マンガン酸塩水溶
液(KMnO4 :40〜60g/l、規定度:1.0〜
1.2N、60〜80℃)で化学的に粗化し、硫酸
(0.3〜0.4N、40〜50℃)で中和することに
より(図2(a))の如く絶縁層4表面に粗化面7が形
成される。
(E) The surface of the insulating layer 4 is polished by about 20 μm with a belt sander, jet scrub, buff or the like, for example, a belt sander, and an alkaline permanganate aqueous solution (KMnO 4 : 40-60 g / l, normality: 1) is used. .0 to
As shown in FIG. 2 (a), the surface of the insulating layer 4 is chemically roughened with 1.2 N, 60 to 80 ° C. and neutralized with sulfuric acid (0.3 to 0.4 N, 40 to 50 ° C.). A roughened surface 7 is formed on the surface.

【0013】(F)次いで、無電解銅めっき、電気銅め
っきを行い数十μmの導通層、例えば約20μmの導通
層を形成する(図2(b))。また、無電解銅めっきの
みで導通層を形成しても良い。
(F) Next, electroless copper plating and electrolytic copper plating are performed to form a conductive layer of several tens of μm, for example, a conductive layer of about 20 μm (FIG. 2 (b)). Further, the conductive layer may be formed only by electroless copper plating.

【0014】(G)このような工程を繰り返して多層印
刷配線板が製造される。
(G) By repeating the above steps, a multilayer printed wiring board is manufactured.

【0015】本実施例は基本的には実施例1と同じであ
るが、絶縁層に光硬化性のない熱硬化性樹脂を用い、バ
イアホールをレーザーで形成したものである。
This embodiment is basically the same as the first embodiment, except that a thermosetting resin having no photo-curing property is used for the insulating layer and the via holes are formed by laser.

【0016】(B’)実施例1の(A)で製造した基板
1上に熱硬化性液状樹脂をカーテンコーター、ロールコ
ーター、スクリーン印刷等の方法で数十μm厚に塗布す
る。例えばロールコーターで70μm厚に塗布し、指触
乾燥(90℃、1時間)、熱硬化(170℃、1時間)
して絶縁層4を形成する。
(B ') A thermosetting liquid resin is applied on the substrate 1 manufactured in (A) of Example 1 to a thickness of several tens of μm by a method such as a curtain coater, a roll coater, or screen printing. For example, apply 70 μm thick with a roll coater, dry to the touch (90 ° C, 1 hour), heat cure (170 ° C, 1 hour).
Then, the insulating layer 4 is formed.

【0017】(C’)次いで、エキシマレーザー、YA
Gレーザ、CO2 レーザー等によりレーザー光線を照射
し、数十μmのバイアホールを形成する。例えば、エキ
シマレーザーにて紫外光(200〜300nm)を照射
して径100μmのバイアホールを形成する(図1
(d))。
(C ') Next, excimer laser, YA
A laser beam is irradiated by a G laser, a CO 2 laser or the like to form a via hole of several tens μm. For example, an excimer laser is irradiated with ultraviolet light (200 to 300 nm) to form a via hole having a diameter of 100 μm (FIG. 1).
(D)).

【0018】以下の工程は実施例1の(D)〜(G)工
程と同様である。
The following steps are the same as the steps (D) to (G) of the first embodiment.

【0019】[0019]

【発明の効果】以上説明したように、本発明はめっきの
前処理である酸処理なしにバイアホール部に選択的にめ
っきを付け、マスクを形成するため、後工程の酸処理に
よっても回路の酸化銅が溶解する現象(ハローイング現
象)がないという結果を有する。また、前述した特許出
願公告公報のハローイング現象を防止する方法で必要と
された特殊な薬品や装置が不必要となり本発明では現状
ラインで行えるというコスト的優位も有する。
As described above, according to the present invention, since the via hole portion is selectively plated without forming acid treatment which is a pretreatment for plating to form a mask, the circuit treatment can be performed by the acid treatment in the subsequent step. It has the result that there is no phenomenon of dissolving copper oxide (haloing phenomenon). In addition, since the special chemicals and devices required for the method of preventing the haloing phenomenon of the above-mentioned patent application publication are unnecessary, the present invention has a cost advantage that it can be performed on the present line.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の製造工程を説明する断面図。FIG. 1 is a sectional view illustrating a manufacturing process according to an embodiment of the present invention.

【図2】本発明の実施例の製造工程を説明する断面図。FIG. 2 is a cross-sectional view illustrating the manufacturing process of the embodiment of the present invention.

【図3】従来技術の製造工程を説明する断面図。FIG. 3 is a cross-sectional view illustrating a conventional manufacturing process.

【図4】従来技術の製造工程を説明する断面図。FIG. 4 is a cross-sectional view illustrating a conventional manufacturing process.

【符号の説明】[Explanation of symbols]

1 基板 2 回路 3 酸化銅 4 絶縁層 5 バイアホール 6 選択的銅めっき 7 粗化面 8 導通層 9 ハローイング現象 10 プリプレグ 11 銅箔 1 substrate 2 circuit 3 copper oxide 4 insulating layer 5 via hole 6 selective copper plating 7 roughened surface 8 conductive layer 9 haloing phenomenon 10 prepreg 11 copper foil

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された導電回路表面に酸化
銅を形成後、絶縁層を形成する工程と、前記絶縁層に所
望の導電回路に貫通するバイアホールを形成する工程
と、前記バイアホール下部の導電回路表面に無電解めっ
きをする工程と、前記絶縁層表面を粗化する工程と前記
絶縁層表面にめっきにより導電層を形成する工程とを含
むことを特徴とする多層印刷配線板の製造方法。
1. A step of forming an insulating layer after forming copper oxide on a surface of a conductive circuit formed on a substrate, a step of forming a via hole penetrating a desired conductive circuit in the insulating layer, and the via. A multilayer printed wiring board comprising: a step of electrolessly plating a surface of a conductive circuit below a hole; a step of roughening the surface of the insulating layer; and a step of forming a conductive layer on the surface of the insulating layer by plating. Manufacturing method.
【請求項2】 前記粗化工程が前記絶縁層表面をアルカ
リ性過マンガン酸塩水溶液で処理する工程であることを
特徴とする請求項1記載の多層印刷配線板の製造方法。
2. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the roughening step is a step of treating the surface of the insulating layer with an aqueous alkaline permanganate solution.
【請求項3】 前記無電解めっきが無電解銅めっきであ
り、かつ電気銅めっきにより前記導電層を形成する工程
を含むことを特徴とする請求項1記載の多層印刷配線板
の製造方法。
3. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the electroless plating is electroless copper plating, and the method further comprises the step of forming the conductive layer by electrolytic copper plating.
JP8159194A 1994-04-20 1994-04-20 Manufacture of multilayer printed wiring board Pending JPH07297547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8159194A JPH07297547A (en) 1994-04-20 1994-04-20 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8159194A JPH07297547A (en) 1994-04-20 1994-04-20 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH07297547A true JPH07297547A (en) 1995-11-10

Family

ID=13750567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8159194A Pending JPH07297547A (en) 1994-04-20 1994-04-20 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH07297547A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242079B1 (en) 1997-07-08 2001-06-05 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63153893A (en) * 1986-12-18 1988-06-27 伊勢電子工業株式会社 Multilayer printed interconnection board
JPH033298A (en) * 1989-05-31 1991-01-09 Ibiden Co Ltd Multilayer printed circuit board and manufacture thereof
JPH05218343A (en) * 1992-01-31 1993-08-27 Sony Corp Semiconductor device and manufacture thereof
JPH05304367A (en) * 1992-04-28 1993-11-16 Murata Mfg Co Ltd Manufacture of multilayer wiring board
JPH05343854A (en) * 1993-02-17 1993-12-24 Ibiden Co Ltd Multilayer printed wiring board and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63153893A (en) * 1986-12-18 1988-06-27 伊勢電子工業株式会社 Multilayer printed interconnection board
JPH033298A (en) * 1989-05-31 1991-01-09 Ibiden Co Ltd Multilayer printed circuit board and manufacture thereof
JPH05218343A (en) * 1992-01-31 1993-08-27 Sony Corp Semiconductor device and manufacture thereof
JPH05304367A (en) * 1992-04-28 1993-11-16 Murata Mfg Co Ltd Manufacture of multilayer wiring board
JPH05343854A (en) * 1993-02-17 1993-12-24 Ibiden Co Ltd Multilayer printed wiring board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242079B1 (en) 1997-07-08 2001-06-05 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same

Similar Documents

Publication Publication Date Title
JP4212006B2 (en) Manufacturing method of multilayer printed wiring board
KR100327705B1 (en) Method of producing a multi-layer printed-circuit board
JP2790956B2 (en) Manufacturing method of multilayer wiring board
JP2776886B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP3012590B2 (en) Method for manufacturing multilayer printed wiring board
JP2699920B2 (en) Method for manufacturing multilayer printed wiring board
EP0837623A1 (en) Method for the manufacture of printed circuit boards with plated resistors
JPH033297A (en) Multilayer printed circuit board and manufacture thereof
JPH07297547A (en) Manufacture of multilayer printed wiring board
JP2001015928A (en) Multilayer printed wiring board and its manufacture
JPH06260763A (en) Manufacture of multilayer wiring board
JPH02143492A (en) Manufacture of high-density multilayered printed-wiring board
JP2004158521A (en) Multilayer printed wiring board and its manufacturing method and semiconductor device
JP2003115662A (en) Method of manufacturing semiconductor device substrate
JP3143408B2 (en) Manufacturing method of printed wiring board
JP2003204138A (en) Manufacturing method for printed wiring board
JPH0964538A (en) Production of printed wiring board
JP2984625B2 (en) Multilayer printed wiring board manufacturing method
JP2919181B2 (en) Printed circuit board manufacturing method
JP3071733B2 (en) Method for manufacturing multilayer printed wiring board
JPH0964543A (en) Production of multilayered flexible printed wiring board
JPH1187924A (en) Multilayered printed circuit board with non-penetrating via hole
JP2951923B2 (en) Multilayer printed wiring board
JP3773567B2 (en) Method for manufacturing printed wiring board
JPH05102656A (en) Multilayer printed wiring board and copper foil for its internal layer electric circuit

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19961112