JP3143389B2 - Printed wiring board having via holes and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for coating a photosensitive interlayer insulating layer on an insulating substrate on which a predetermined circuit pattern including a metal area having a large area such as a power supply layer and a ground layer is formed. The printed wiring board provided with via holes corresponding to the conductor pads or lands by developing after exposing the insulating layer through the mask film, particularly, the conductor pad by exposing the interlayer insulating layer through the mask film, When forming a via hole corresponding to a land, light scattered by a metal region which is a power supply layer or a ground layer is prevented from entering into an interlayer insulating layer existing below a mask region of a mask film. The present invention relates to a printed wiring board capable of forming a via hole while reliably exposing a metal region by using the same, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Various types of printed wiring boards having via holes have been proposed. FIG. 6 shows a method of manufacturing a printed wiring board of this type.
Referring to FIG. FIG. 6 is a sectional view of the insulating substrate, and FIG. 7 is a plan view of the insulating substrate.

In order to manufacture a printed wiring board 20 (see FIG. 10), first, an insulating substrate 2 as shown in FIGS.
Create 1. The insulative substrate 21 is a copper clad laminate having copper foil laminated on one or both sides, a metal region 22 having a large area such as a power supply layer and a ground layer, a connection pad 23 having a normal area, and a predetermined circuit pattern 24. Is formed by coating a copper foil portion to be etched with an etching resist and then performing a predetermined etching process.

Thereafter, a metal region 22, a connection pad 23,
By coating a photosensitive resin on the insulating substrate 21 together with the circuit pattern 24, the interlayer insulating layer 25 (see FIG. 8 and the like)
To form Further, after exposing the mask film 27 to the predetermined region 28 (see FIG. 9 and the like) formed on the mask film 27 while keeping the mask film 27 in close contact with the interlayer insulating layer 25 while corresponding to the metal region 22 and the connection pad 23. Then, by performing a developing process on the insulating substrate 21, via holes 26 are formed corresponding to the metal regions 22 and the connection pads 23.
Thereafter, a circuit pattern 29 continuous from the inside of the via hole 26 of each metal region 22 and the connection pad 23 and from the via hole 26 is formed on the interlayer insulating layer 25 by electroless plating to form the printed wiring board 20. Is done.

[0005]

However, when the printed wiring board 20 is formed by the above-described procedure, the metal region 22 is not completely exposed inside the via hole 26 formed in the metal region 22, There is a possibility that the circuit pattern 29 formed inside the via hole and the metal region 22 will not be connected. Such a mechanism will be described with reference to FIGS. FIG. 8 is a cross-sectional view schematically showing a state in which the interlayer insulating layer 25 is formed on the insulating substrate 21. FIG. 9 shows a state in which the interlayer insulating layer 25 is exposed to the metal region 22 by the mask film 27. FIG. 10 is a sectional view of the printed wiring board 20 showing a state in which a via hole 26 is formed in the metal region 22 and the connection pad 23.

In FIG. 8, when a photosensitive resin is applied on an insulating substrate 21 to form an interlayer insulating layer 25, the photosensitive resin is relatively uniform because the metal region 22 has a large area. On the region 22 is applied with a thickness L1,
On the other hand, since the photosensitive resin is filled between the connection pads 23 and the circuit patterns 24 and between the circuit patterns 24 in the vicinity of the connection pads 23 and the circuit patterns 24, the connection pads 23 and the circuit patterns 24 are not filled. The thickness of the interlayer insulating layer 25 formed on the layer 24 is to be applied with a thickness L2 smaller than the thickness L1. Accordingly, the interlayer insulating layer 25 is formed thick (thickness L1) on the metal region 22 as shown in FIG. 8, while thinly formed (thickness L2) on the connection pad 23 and each circuit pattern 24. .

The interlayer insulating layer 25 corresponding to the metal region 22 and the connection pad 23 on the insulating substrate 21 as described above.
When the via hole 26 is formed in the mask film 2
7 is exposed by irradiating light from above the mask film 27 in a state where the mask region 28 of FIG. 7 (see FIG. 9) corresponds to each metal region 22 and the connection pad 23.
5 is different on the metal region 22 and on the connection pad 23, the thickness of the interlayer insulating layer 2 on the metal region 22 is different.
Exposure state 5 and interlayer insulating layer 2 on connection pad 23
This is inevitably different from the exposure state of No. 5. That is, since the interlayer insulating layer 25 on the connection pad 23 is formed so as to be thin, it is not sufficiently hardened by being shielded from light through the mask region 28, and therefore, the connection pad 25 is formed in the via hole 26 formed at the time of development. 23 is completely exposed. On the other hand, since the interlayer insulating layer 25 on the metal region 22 is formed to be thick, the exposure resolution becomes insufficient, so that the metal region 22 is not completely exposed in the via hole 26 formed during development. Become.

When the mask region 28 of the mask film 27 is arranged corresponding to the metal region 22 and the interlayer insulating layer 25 is exposed so as to form the via hole 26 in the interlayer insulating layer 25, light is emitted as shown in FIG. As shown, the light is irradiated from above the mask film 27. Thereby, the mask film 27
The interlayer insulating layer 25 irradiated with light from the transparent portion is cured by performing a photo-curing reaction, while the interlayer insulating layer 2 corresponding to the portion shielded by the mask region 28 of the mask film 27 is formed.
5 retains an uncured state without being cured because it is not irradiated with light.

However, since the metal region 22 has a large area forming a power supply pattern and a ground pattern, light transmitted through the mask film 27 passes through the interlayer insulating layer 25 as shown in FIG. The light will be scattered on the rear metal region 22. In particular, light transmitted through the mask film 27 and the interlayer insulating layer 25 at a position near the mask region 28 is also scattered on the metal region 22, and the scattered light is present under the mask region 28. As a result, the interlayer insulating layer 25 covered via the mask region 28 that should not be cured is cured. In such a case, after the exposure process as described above, the interlayer insulating layer 25 cured even after the development process is performed.
Film remains on the metal region 22. Therefore, FIG.
As shown in FIG. 0, the cured interlayer insulating layer 25 remains in the via hole 26 formed corresponding to the metal region 22, and the connection pad surface is not completely exposed in the via hole 26. Thereby, even if the circuit pattern 29 is formed on the interlayer insulating layer 25 together with the inside of the via hole 26 by electroless plating, the circuit pattern 29
Has a problem that it is not connected to the metal region 22.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. A photosensitive interlayer insulating layer is formed on a substrate on which a metal region acting as a power supply layer or a ground layer is formed. A conductor circuit is formed on the interlayer insulating layer, and the conductor circuit is a multilayer printed wiring board connected to the metal region via a via hole formed in the interlayer insulating layer. A pad connected to the via hole is formed, a blank portion is provided around the pad to be separated from the metal region, and the pad is electrically connected to the metal region at one or more places. By being connected, the thickness of the interlayer insulating layer on the metal region and the conductor pattern is made uniform, and the exposure resolution of the interlayer insulating layer on the metal region is prevented from varying, and The light scattered by the metal region is prevented from entering the interlayer insulating layer existing below the mask region of the mask film on which the pattern for forming the via hole is drawn, and the via hole is reliably exposed while the metal region is exposed. It is an object of the present invention to provide a printed wiring board capable of forming the same and a method for manufacturing the same.

[0011]

According to a first aspect of the present invention, there is provided a printed wiring board comprising a photosensitive interlayer insulating layer formed on a substrate having a metal region acting as a power supply layer or a ground layer. Is formed, and a conductive circuit is formed on the interlayer insulating layer, and the conductive circuit is connected to the metal region via a via hole formed in the interlayer insulating layer. A pad connected to the via hole is formed in the metal region, and a blank portion is provided around the pad so as to be separated from the metal region. Ri in Na electrically connected, said Blanc
Filled resin layer or plating resist layer is formed
And the upper surface of the pad and the filling resin layer or plating
The feature is that it is flush with the top surface of the resist layer
I do.

In the printed wiring board according to the first aspect of the present invention, light is irradiated from the outside of the mask film in a state where the mask film is overlaid on the interlayer insulating layer so as to form via holes corresponding to the metal regions. When performing the exposure of the interlayer insulating layer as described above, the interlayer insulating layer irradiated with light through the mask film is cured by performing a photo-curing reaction, while the portion corresponding to the light-shielded portion in the mask region of the mask film Since the interlayer insulating layer is not irradiated with light, it is kept uncured without being cured.

At this time, in a metal region constituting a power supply pattern or a ground pattern, a state in which a mask film is superimposed on an interlayer insulating layer and a filled resin layer or a conductor having no conductor on the outside covered by the mask region of the mask film. Since the blank portion having the plating resist layer is formed, light transmitted through the mask film and the interlayer insulating layer near the mask region is irradiated to the blank portion, and the light is scattered at a position near the mask region. It will not be done. Accordingly, light is efficiently prevented from entering the interlayer insulating layer existing below the mask region, and the interlayer insulating layer below the mask region is kept in an uncured state without being cured. You. Thus, if a development process is performed after the exposure process, the cured film of the interlayer insulating layer does not remain on the metal region, and it is possible to form a via hole that reliably exposes the metal region.

In the printed wiring board, a filling resin layer or a plating resist layer is formed between the blank portion and the circuit pattern so as to be substantially flush with the upper surface of the metal region. When forming the photosensitive interlayer insulating layer on the filling resin layer, it is possible to form the photosensitive interlayer insulating layer to have a substantially uniform thickness over the entire surface of the insulating substrate. Therefore, when forming the via hole corresponding to the connection pad by exposing the interlayer insulating layer through the mask film, it is possible to prevent a variation in the exposure resolution from occurring and to form the interlayer insulating layer under the same exposure condition. Exposure becomes possible. As a result, a via hole in which the metal region is completely exposed may be formed. The metal region is connected to at least one portion with a portion (connection pad) connected to the via hole in the metal region.
Therefore, even if there is a blank portion, the functions of the power supply layer and the ground layer are not impaired.

Production of the multilayer printed wiring board according to claim 2
The method is to create a power or ground layer on the board.
Photosensitive interlayer insulation on the substrate with the metal area used
Layer and then a via hole pattern
Place the formed mask film and expose and develop.
Form holes for via holes, and add conductor circuits and holes.
For manufacturing method of multilayer printed wiring board with ear holes
Pad that connects to the via hole in the metal area
A blank around the pad
And separate the pad from the metal area.
At one or more locations and electrically connected to the
The resin is filled in the link portion and the upper surface of the pad is
Characterized in that the upper surface of the filling resin is flush with the upper surface
, And the according to this manufacturing method, it is possible to manufacture a printed wiring board according to claim 1, therefore, the same effect as that described in above can be obtained.

Further, according to the invention of claim 3 , according to claim 2,
In the method for manufacturing a printed wiring board, the blank portion
Is formed by etching a metal area, and the pad
And the top surface of the filling resin are polished to the same surface.
It is characterized by doing. The blank part is filled with resin.
Since the upper surface and the upper surface of the filling resin are made the same surface, even when an interlayer insulating layer is formed thereon, the thickness can be made uniform, resulting in insufficient development and excessive development due to thickness variation. The problem is eliminated, and a good via hole can be formed.

Furthermore, according to the invention of claim 4 , according to claim
In the method of manufacturing a printed wiring board according to 2 above, in forming a pad connected to a via hole in the metal region,
After forming a plating resist layer corresponding to a blank portion around the pad so that the pad and the metal region can be electrically connected at one or more locations, an electroless plating process is performed to form the metal region and the pad. , A blank portion is provided around the pad and is separated from the metal region. In the blank part,
Since the plating resist is present, the upper surfaces of the conductor circuits can be flush with each other.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a printed wiring board according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings based on an embodiment embodying the present invention. First, the structure of the printed wiring board according to the present embodiment will be described with reference to FIGS. 1 (a), 1 (b) and 2. FIG. FIG. 1 is a sectional view of a printed wiring board, and FIG. 2 is a plan view of the printed wiring board.

In FIG. 1 and FIG.
Nucleus includes a metal region 2 having a large area like a power supply layer or a ground layer, a connection pad 3 having a normal area smaller than the metal region 2, and an insulating substrate 5 on which a predetermined circuit pattern 4 is formed. Is configured as Here, a copper-clad laminate in which copper foil is laminated on one side or both sides is used as the insulating substrate 5, and the metal region 2, the connection pads 3, and the circuit pattern 4 are formed on the copper-clad laminate by a predetermined method. It is formed on one side or both sides by performing an etching process. still,
The insulating substrate 5 is a glass epoxy substrate, a polyimide substrate,
After forming an adhesive layer for electroless plating on a ceramic substrate, a metal substrate, etc., this is roughened to form a roughened surface, which is then subjected to electroless plating to form a copper circuit pattern. Is also good.

As shown in FIG. 2, blank portions 6 are formed at a plurality of locations in the metal region 2. The blank portion 6 is formed by an etching process at the same time as the formation of the metal region 2. After forming the interlayer insulating layer 9 as described later, the mask film 11 is superimposed on the interlayer insulating layer 9 and adhered thereto. In the state where the conductor (copper foil) is not present in the metal region 2 on the outside covered with the mask region 12 of the mask film 11 when the exposure processing is performed in this state. By forming the blank portion 6 in this manner, when performing the exposure treatment of the interlayer insulating layer 9 through the mask film 11, the mask film 11 irradiates the interlayer insulating layer 9 at a position near the mask region 12. Light is applied to the blank part 6
Through the mask region 12, thereby preventing light from entering the interlayer insulating layer 9 existing below the mask region 12 and exposing the interlayer insulating layer 9 by the mask region 12. Processing can be performed reliably. This point will be described later.

Here, the shape of the blank portion 6 is shown in FIG.
This will be described in detail based on FIG. In FIG.
Is composed of an arc-shaped window portion 6A obtained by dividing a circular window having a predetermined width into four. A conductor portion 7 defined by an inner circle and separated from the metal region 2 by a blank portion 6
Is formed wider than the area of the mask region 12 of the mask film 11, and the center of the conductor 7 is
With the mask film 11 superimposed thereon, the mask region 1
2 coated. As a specific example of the blank portion 6, it is preferable that the diameter of the inner circle is 125 μm to 350 μm, the diameter of the outer circle is 225 μm to 800 μm, and the gap between the window portions 6A is about 50 μm to 250 μm. Further, regarding the shape of the blank portion 6, various variations of the shape can be further considered. Variations of the blank section 6 will be described with reference to FIG. FIG. 4 is an explanatory diagram showing a variation of the blank section 6. As shown in FIG.

For example, as shown in FIG. 4A, an example in which a circular window is basically constituted by a circular window is constituted by a window 6A obtained by dividing a circular window into two around a conductor 7. (A blank part 6 at the upper left in FIG. 4 (A)) and a single arc-shaped window part 6A around the conductor part 7 (FIG. 4 (A)).
The middle and upper right blank portions 6), and a window portion 6A obtained by dividing a circular window around the conductor portion 7 into three parts (FIG. 4A).
The middle and lower left blank portions 6), and a window portion 6A in which a circular window is divided into five around the conductor portion 7 (FIG. 4A)
A middle and lower right blank section 6) is conceivable.

As shown in FIG. 4 (B), an example of a rectangular window basically comprises a rectangular window 6A around a rectangular conductor 7 as shown in FIG. (A blank part 6 at the upper left in FIG. 4B), a window part 6A obtained by dividing a square window into four parts around a square conductor part 7
(The upper right blank portion 6 in FIG. 4 (B)), and a window portion 6A obtained by dividing a rectangular window into two around the rectangular conductor portion 7 (FIG. 4 (B)). , A lower left blank portion 6), and a window portion 6A obtained by unequally dividing a rectangular window into three around the rectangular conductor portion 7 (lower right blank portion 6 in FIG. 4B). Etc. are considered.

Further, as an example which is basically composed of a hexagonal window, as shown in FIG. 4C, one hexagonal window 6A is formed around a hexagonal conductor 7. 4 (C in FIG. 4 (C)), and a window 6A obtained by unequally dividing a hexagonal window into three around a hexagonal conductor 7 (FIG. 4 (C)). , Upper right blank portion 6), and a window portion 6A obtained by dividing a hexagonal window into three around the hexagonal conductor portion 7 (FIG. 4C).
The middle, lower left blank section 6) and the like are conceivable.

In the insulating substrate 5, each blank portion 6, the space between the metal region 2 and the circuit pattern 4, the space between the circuit patterns 4, and the space between the connection pad 3 and the circuit pattern 4 are filled. And a filling resin layer 8 is formed. The filling resin layer 8 is formed so as to be substantially flush with the upper surfaces of the metal region 2, the connection pad 3, and the circuit pattern 4. The filling resin layer 8, the metal region 2, the connection pad 3, and the circuit pattern 4 Are flush with each other. Based on this, the interlayer insulating layer 9 (described later) can be applied and formed with a uniform thickness.

Here, as the filling resin, a solventless resin is desirable, and an epoxy resin is preferred. The reason for using no solvent is to consider that if a solvent remains in the filling resin layer 8, the filling resin layer 8 may be peeled off when heat treatment is performed. When the filling resin contains inorganic particles such as silica, the curing shrinkage of the filling resin layer 8 is reduced, and the warpage of the insulating substrate 5 can be prevented.

When the metal region 2, the connection pad 3, the circuit pattern 4 and the like are formed on the interlayer agent, the metal region 2, the connection pad 3, and the circuit pattern 4
A plating resist will be formed. Metal area 2,
The upper surfaces of the connection pads 3 and the circuit pattern 4 are flush with the upper surface of the plating resist. Therefore, the interlayer insulating layer 9 can be formed with a uniform thickness. In addition, the metal region 2, the connection pad 3,
In order to make the upper surface of the circuit pattern 4 and the upper surface of the plating resist flush, the surface may be polished with a belt sander or the like.

As described above, an interlayer insulating layer 9 is formed on the upper surfaces of the metal regions 2, the connection pads 3, the circuit patterns 4, the filling resin layer 6 and the plating resist layer 8 'formed on the same surface. . When the interlayer insulating layer 9 is formed by coating, as described above, each blank portion 6, between the metal region 2 and the circuit pattern 4, between the circuit patterns 4, and between the connection pad 3 and the circuit pattern 4. Since the filling resin layer 8 or the plating resist layer 8 'is formed and the upper surfaces thereof are flush with each other, the interlayer insulating layer 9 can be applied and formed with a uniform thickness. In addition, the interlayer insulating layer 9 can be formed by coating using various photosensitive resins. For example, as a resin material for forming the interlayer insulating layer 9, an adhesive for electroless plating is suitable. . As an adhesive for electroless plating, in a heat-resistant resin that is hardly soluble in acid or oxidizing agent,
An adhesive obtained by dispersing heat-resistant resin particles soluble in an acid or an oxidizing agent can be used. In addition, the electroless adhesive is disclosed in Japanese Patent Publication No. 4-55555, Japanese Patent Publication No. 5-18476,
It has the same composition as the adhesive described in JP-B-7-34505.

As the adhesive for electroless plating, an adhesive obtained by dispersing heat-resistant resin particles soluble in an acid or an oxidizing agent in a heat-resistant resin hardly soluble in an acid or an oxidizing agent is optimal. This is because by roughening and removing the heat-resistant resin particles soluble in an acid or an oxidizing agent, an octopus-shaped anchor can be formed on the surface and the adhesion to the conductor circuit can be improved. As the heat-resistant resin hardly soluble in an acid or an oxidizing agent, a photosensitive thermosetting resin or a composite of a photosensitive thermosetting resin and a thermoplastic resin is desirable. By sensitizing, via holes can be easily formed by exposure and development. Further, by forming a composite with a thermoplastic resin, the toughness can be improved, the peel strength of the conductor circuit can be improved, and the occurrence of cracks in the via holes due to the heat cycle can be prevented.

Specifically, epoxy acrylate obtained by reacting an epoxy resin with acrylic acid or methacrylic acid, or a composite of epoxy acrylate and polyether sulfone is preferred. Epoxy acrylate has two of all epoxy groups.
It is desirable that 0 to 80% react with acrylic acid or methacrylic acid.

Further, the heat-resistant resin particles include:
Heat-resistant resin powder having an average particle size of 10 μm or less, agglomerated particles having an average particle size of at least 3 times the particle size of the particles obtained by aggregating the heat-resistant resin powder having an average particle size of 2 μm or less,
A mixture of a heat-resistant resin powder having an average particle diameter of 10 μm or less and a heat-resistant resin powder having an average particle diameter of 1/5 or less and 2 μm or less of the particles, the average particle diameter being 2 μm to 10 μm
m on the surface of the heat-resistant resin powder, at least one of the heat-resistant resin powder or the inorganic powder having an average particle size of 2 μm or less
Desirably, it is selected from pseudo particles obtained by attaching seeds. These are because they can form complex anchors.

As the heat-resistant resin particles, epoxy resin, amino resin (melamine resin, urea resin, guanamine resin) and the like are preferable. The solubility of the epoxy resin in an acid or an oxidizing agent can be arbitrarily changed by changing the type of the oligomer, the type of the curing agent, and the crosslink density. For example, a bisphenol A-type epoxy resin oligomer cured with an amine-based curing agent is easily dissolved in an oxidizing agent. However, the novolak epoxy resin oligomer cured with an imidazole-based curing agent is hardly dissolved in the oxidizing agent.

The acids used in the present invention include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and organic acids are particularly preferable. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.
The oxidizing agent is preferably chromic acid or permanganate (such as potassium permanganate). In particular, in the case of dissolving and removing the amino resin, it is preferable to perform a roughening treatment alternately with an acid and an oxidizing agent.

In the present invention, the interlayer insulating agent may have a plurality of layers. In the case of using a plurality of layers, there are the following modes. 1) In the interlayer insulating layer provided between the upper conductor circuit and the lower conductor circuit, the side closer to the upper conductor circuit is made of a heat-resistant resin which is hardly soluble in an acid or an oxidizing agent and which is soluble in an acid or an oxidizing agent. An adhesive for electroless plating in which heat-resistant resin particles are dispersed, and a two-layer structure in which a side near the lower conductive circuit is made of a heat-resistant resin that is hardly soluble in an acid or an oxidizing agent. With this configuration, even if the adhesive layer for electroless plating is roughened, the layer is not excessively roughened and short-circuits between the layers.

2) In the interlayer insulating layer provided between the upper conductor circuit and the lower conductor circuit, a filling resin material is embedded between the lower conductor circuits, and the surface of the lower resin circuit and the filling resin material are flush with each other. To form a heat-resistant resin layer hardly soluble in an acid or an oxidizing agent thereon, and further heat-resistant resin particles soluble in an acid or an oxidizing agent in a heat-resistant resin hardly soluble in an acid or an oxidizing agent. Having a three-layer structure in which an adhesive for electroless plating in which is dispersed is formed.

Further, via holes 10 are formed in the interlayer insulating layer 9 so as to correspond to the conductors 7 and the connection pads 3 surrounded by the windows 6 A of the blank 6. The via hole 10 is formed by a light source with the mask film 11 being closely adhered to the interlayer insulating layer 9 so that the mask region 12 of the mask film 11 corresponds to the conductor portion 7 and the connection pad 3. It is formed by irradiating light from above and exposing, and then performing a predetermined developing process. Since the developing process is performed by a known method, a detailed description is omitted here.

Here, the operation of the blank portion 6 when exposing the interlayer insulating layer 9 will be described with reference to FIG. FIG. 3 is an enlarged partial sectional view schematically showing a state where the interlayer insulating layer 9 on the metal region is exposed. Interlayer insulating layer 9
In order to expose the mask film 11, first, the mask region 11 of the mask film 11 corresponds to the conductor 7 surrounded by each window 6 A of the blank portion 6 formed in the metal region 2. On the interlayer insulating layer 9 in close contact with each other. In this state, as shown in FIG. 3, light is irradiated from above the mask film 11 to expose the interlayer insulating layer 9. At the time of such exposure, the mask film 11 is formed transparent except for the black mask region 12, so that the irradiation light is blocked by the mask region 12 and the mask film 11 is The light penetrates into the interlayer insulating layer 9. As a result, the mask region 12
The portion of the interlayer insulating layer 9 covered by the masking is kept in an uncured state without being cured, while the other portion of the interlayer insulating layer 9 not covered by the mask region 12 is photocured.

At this time, the interlayer insulating layer 9 is formed on the metal region 2,
Since the upper surface of the filling resin layer 8 and the like are coated and formed to have a uniform thickness, the interlayer insulating layer 9 can be exposed with a good exposure resolution at the boundary of the mask region 12 of the mask film 11 and the like. Further, a blank portion 6 having no conductor formed of each window portion 6A is formed around the conductor portion 7 corresponding to the mask region 12, and each window portion 6A is filled with a filling resin layer 8 or plated. Resist layer 8 '
Is formed, most of the light irradiated near the outside of the inner mask region 12 of the light irradiated as described above is not absorbed by the filling resin layer 8 and scattered. In addition, light scattered on the metal region 2 outside the blank portion 6 hardly enters the interlayer insulating layer 9 existing below the mask region 12. As a result, the interlayer insulating layer 9 existing below the mask region 12 is scattered from the metal region 2 in combination with the fact that the interlayer insulating layer 9 can be exposed with good resolution at the boundary of the mask region 12 as described above. Curing due to scattered light can be efficiently suppressed. As a result, by developing the printed wiring board 1 after the exposure as described above, the interlayer insulating layer 9 existing in an uncured state on the conductor portion 7 can be completely removed. The via hole 10 in which the conductor portion 7 is completely exposed can be formed without leaving the coating of the interlayer insulating layer 9.

Further, a circuit pattern 13 is formed continuously on the interlayer insulating layer 9 and inside each via hole 10. The circuit pattern 13 includes the via hole 10
Is formed by performing a roughening treatment and a plating catalyst nucleus treatment of the insulating substrate 5 after the formation of the plating film, and then immersing it in an electroless plating bath to form a plating film. A known method is used for the electroless plating method, and therefore, detailed description thereof is omitted here.

Next, a method of manufacturing the printed wiring board 1 configured as described above will be described with reference to FIG. FIG. 5 is a process chart showing a manufacturing process of the printed wiring board 1.
In FIG. 5, first, a predetermined etching process is performed on the copper-clad laminate to form a metal region 2 having a large area such as a power supply pattern or a ground pattern on the upper surface, and the presence of conductors at a plurality of locations in the metal region 2. No blank part 6
(Consisting of four arc-shaped window portions 6A, a conductor portion 7 is present at the center of each window portion 6A), a connection pad 3, and an insulating substrate on which the circuit pattern 4 is formed (FIG. 5).
(A)).

Next, a filling resin is applied to the upper surface of the insulating substrate 5, and the window 6A of each blank portion 6, between the metal region 2 and the circuit pattern 4, between the circuit patterns 4, and between the connection pads 3 are formed. A filling resin layer 8 is formed by filling a filling resin between the substrate and the circuit pattern 4 (see FIG. 5B). Further, in this state, since the filling resin has irregularities on the upper surface of the insulating substrate 5, the upper surface of the insulating substrate 5 is polished by a known polishing method. Thus, the upper surfaces of the filling resin layer 8, the metal region 2, the connection pad 3, and the circuit pattern 4 are flush with each other (see FIG. 5C).

Subsequently, a photosensitive resin is applied to the upper surfaces of the metal region 2, the connection pad 3, the circuit pattern 4, and the filling resin layer 8 formed on the same surface in the above-described process, whereby the interlayer insulating layer 9 is formed. It is formed by application (see FIG. 5D). At this time, the interlayer insulating layer 9 can be applied and formed with a uniform thickness based on the fact that the upper surfaces of the filling resin layer 8, the metal region 2, the connection pad 3, and the circuit pattern 4 are flush. .

Further, the mask area 1 of the mask film 11
The mask film 11 is closely adhered onto the interlayer insulating layer 9 so that 2 corresponds to the conductor portion 7 and the connection pad 3 in the metal region 2. Thereafter, light is irradiated from above the mask film 11 from a light source to expose the interlayer insulating layer 9 (FIG. 5).
(E)). At this time, as described above, since the interlayer insulating layer 9 is formed by applying a uniform thickness on the upper surfaces of the metal region 2, the filling resin layer 8, and the like, the interlayer insulating layer 9 is formed at the boundary of the mask region 12 of the mask film 11 or the like. The interlayer insulating layer 9 can be exposed with a good exposure resolution. Further, a blank portion 6 having no conductor formed of each window portion 6A is formed around the conductor portion 7 corresponding to the mask region 12, and each window portion 6A is filled with the filling resin layer 8. Most of the light irradiated near the outer side of the inner mask region 12 of the light irradiated as described above is not absorbed and scattered by the filling resin layer 8, and The light scattered on the metal region 2 on the outside hardly enters the interlayer insulating layer 9 existing below the mask region 12. As a result, the interlayer insulating layer 9 existing below the mask region 12 is scattered from the metal region 2 in combination with the fact that the interlayer insulating layer 9 can be exposed with good resolution at the boundary of the mask region 12 as described above. Curing due to scattered light can be efficiently suppressed.

As a result, by performing the exposure as described above, the portion of the interlayer insulating layer 9 on the conductor portion 7 covered with the mask region 12 is maintained in a completely uncured state. The interlayer insulating layer 9 other than the portion covered with 12 is completely cured by a photocuring reaction.

After the exposure as described above, by developing the printed wiring board 1, the interlayer insulating layer 9 existing in an uncured state on the conductor portion 7 can be completely removed. The via hole 10 in which the conductor portion 7 is completely exposed can be formed without leaving the coating of the interlayer insulating layer 9 on the substrate. Thereafter, as described above, a continuous circuit pattern 13 is formed on the interlayer insulating layer 9 and inside the via hole 10 by the electroless plating method. Thus, the printed wiring board 1 is manufactured (see FIG. 5F). The interlayer insulating layer 9 cured by the exposure process remains on the insulating substrate 5 as it is.

As described in detail above, in the printed wiring board 1 according to the present embodiment, the mask film 11 is superposed on the interlayer insulating layer 9 so as to form the via holes 10 corresponding to the metal regions 2. When the interlayer insulating layer 9 is exposed by irradiating light from above the region 12, the interlayer insulating layer 9 is exposed.
Are metal region 2, filling resin layer 8, plating resist layer 8 '
Can be exposed to the interlayer insulating layer 9 with good exposure resolution at the boundary of the mask region 12 of the mask film 11 and the like.

The conductor portion 7 corresponding to the mask region 12
A blank portion 6 having no conductor formed of each window portion 6A is formed around (this functions as a connection pad), and a filling resin layer 8 is filled in each window portion 6A or a plating resist layer 8 'is formed. Since it is formed, most of the light irradiated near the outside of the inner mask region 12 of the light irradiated as described above is not absorbed by the filling resin layer 8 and scattered. Light scattered on the metal region 2 outside the blank portion 6 is transmitted to the mask region 1.
There is almost no penetration into the interlayer insulating layer 9 existing below the layer 2. As a result, the interlayer insulating layer 9 existing below the mask region 12 is scattered from the metal region 2 in combination with the fact that the interlayer insulating layer 9 can be exposed with good resolution at the boundary of the mask region 12 as described above. Curing due to scattered light can be efficiently suppressed. As a result, by developing the printed wiring board 1 after the exposure as described above, the interlayer insulating layer 9 existing in an uncured state on the conductor portion 7 can be completely removed. The via hole 10 in which the conductor portion 7 is completely exposed can be formed without leaving the coating of the interlayer insulating layer 9.

Further, a blank portion 6 is provided around the conductor portion 7 which is a connection pad. The blank portion 6 is filled with a filling resin 8 and a plating resist layer 8 'is formed. As compared with the case where the portion is not formed, the adhesiveness with the interlayer insulating layer formed thereon is excellent. Even if the interlayer insulating layer is formed on the metal area as it is,
Since resin and metal are not well-known, they are easily separated. Furthermore, since a via hole is connected to the metal region, if a stress is generated due to a heat cycle or the like, separation between the metal region and the interlayer insulating layer is likely to occur near the via hole.

According to the present invention, a filling resin 8 and a plating resist layer 8 ′ are surrounded by a blank portion 6 around a conductor portion 7 which is a connection pad connected to a via hole in a metal region.
And has a better affinity with the interlayer insulating layer than metal, so that peeling of the interlayer insulating layer can be prevented. It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications can be made without departing from the spirit of the present invention. For example, in the printed wiring board 1 in the above-described embodiment, the metal region 2 and the like are formed on one surface of the insulating substrate 5, but may be formed on both surfaces of the insulating substrate 5 and in a multilayer structure.

[0050]

As described above, according to the present invention, when a via hole is formed by exposing an interlayer insulating layer through a mask film, the via hole is formed on a circuit pattern including a metal region acting as a power supply or ground layer. The exposure resolution of the interlayer insulating layer on the connection pads and the like can be prevented from being varied by equalizing the thickness of the interlayer insulating layer to be formed, and light scattered by the metal region can be reduced in the mask region of the mask film. It is possible to provide a printed wiring board capable of forming a via hole while reliably exposing a connection pad by preventing entry into a lower interlayer insulating layer, and a method of manufacturing the same. Further, in the present invention, a filling resin 8 and a plating resist layer 8 ′ are formed in the blank portion 6 around the conductor portion 7, which is a connection pad connected to the via hole, in the metal region. Because of good compatibility with the interlayer insulating layer, peeling of the interlayer insulating layer can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a printed wiring board.

FIG. 2 is a plan view of a printed wiring board.

FIG. 3 is an enlarged partial cross-sectional view schematically showing a state where an interlayer insulating layer on a metal region is exposed.

FIG. 4 is an explanatory view showing variations of a blank portion.

FIG. 5 is a process chart showing a manufacturing process of the printed wiring board.

FIG. 6 is a sectional view of a conventional insulating substrate.

FIG. 7 is a plan view of a conventional insulating substrate.

FIG. 8 is a cross-sectional view schematically showing a state where an interlayer insulating layer is formed on a conventional insulating substrate.

FIG. 9 is a cross-sectional view showing a state in which an interlayer insulating layer is conventionally exposed with a mask film.

FIG. 10 is a cross-sectional view of a printed wiring board showing a state where a via hole is formed in a metal region and a connection pad in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Metal area 3 Connection pad 4 Circuit pattern 5 Insulating substrate 6 Blank part 6A Window 7 Conductor part 8 Filling resin layer 8 'Plating resist layer 9 Interlayer insulating layer 10 Via hole 11 Mask film 12 Mask area 13 Circuit pattern

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H05K 3/36

Claims (4)

(57) [Claims] 1. A photosensitive interlayer insulating layer is formed on a substrate on which a metal region serving as a power supply layer or a ground layer is formed, and a conductive circuit is formed on the interlayer insulating layer. Is a multilayer printed wiring board connected to the metal region via a via hole formed in an interlayer insulating layer, wherein a pad connected to the via hole is formed in the metal region, and a pad is formed around the pad. together formed by spaced and are blank portion is provided a metal region, the pad is Ri Na electrically connected by metal regions and one or more points, the blank portion is filled resin layer or a plating resist layer
Is formed, and the upper surface of the pad and the filling resin layer are formed.
Alternatively , the multilayer printed wiring board is formed on the same surface as the upper surface of the plating resist layer . 2. A power supply layer or a ground layer on a substrate.
Layer on the substrate on which the working metal areas are formed
Inter-layer insulation layer and then a via hole formation pattern
After placing the mask film on which the pattern is formed,
Holes for via holes, and
Of multilayer printed wiring board forming via holes and via holes
Forming a pad that connects to a via hole in a metal region.
A blank area around the pad to
Area and separate the pad from the metal area.
The blank portion is filled with resin, and the pad is
A method for manufacturing a multilayer printed wiring board, wherein the upper surface of the resin is made flush with the upper surface of the filling resin . 3. The method according to claim 1, wherein the blank portion is formed by etching a metal region.
Formed by processing, the upper surface of the pad and the filling resin
The upper surface is made to be the same surface by polishing.
The method for producing a multilayer printed wiring board according to claim 2. 4. A connection with a via hole in said metal region.
Pad and metal area in one place
Bras around the pads so that they can be connected electrically.
After forming the plating resist layer corresponding to the ink
Perform a deplating process to form metal areas and pads.
Provide a blank around the pad and separate it from the metal area.
The method for producing a multilayer printed wiring board according to claim 2.