JPH06314859A - Substrate for mounting electronic parts and its manufacture - Google Patents

Abstract

PURPOSE:To improve the reliability on mounting and materialize high-density mounting and cost reduction by forming a metallic layer for mounting electronic components on the surface of a substrate, and forming an insulating layer made of photosensitive resin on the metallic surface, and forming such an opening that at least one part of the metallic layer is exposed, in the insulating layer. CONSTITUTION:A wiring pattern 3a as an inner layer conductor circuit and a die pad 3b as a metallic layer for mounting electronic components are formed all over the surface of the insulating base material 2 constituting a substrate 1. An insulating layer 4 made of photosensitive resin is made on the wiring pattern 3a and the die pad 3b, and a cavity 6 as such an opening as to expose one part of the die pad 3b is made in the insulating layer 4. An IC chip 7 is mounted inside the cavity 6, and bonding pads 8b are disposed regularly around the cavity 6. On the other hand, also on the side of the IC chip 7 are formed a plurality of bonding pads 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component mounting substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, various electronic component mounting substrates have been proposed as substrates for mounting electronic components such as IC chips.

As the electronic component mounting substrate, one having a structure as shown in, for example, FIGS. 9 and 10 is known. A cavity 52 is formed as a recess for mounting an electronic component on the surface of an insulating base material 51 that constitutes the substrate 50. A metal plating layer 52a is formed on the inner wall surface of the cavity 52.
And the IC chip 53 is mounted on the metal plating layer 52a. A plurality of bonding pads 55 are provided around the cavity 52, and the bonding pad 55 side and the IC chip 53 side are electrically connected via wire bonding 54.

As a method of forming the cavity 52 in the insulating base material 51, conventionally, a counterboring process using a rotary cutting tool such as a cutting tool has been generally performed.

[0005]

By the way, as the outer shape of the IC chip 53, a rectangular shape such as a rectangular shape or a rectangular shape is generally used at present. Therefore, the IC of the above shape
In order to mount the chip 53, it is only necessary to form a cavity 52 that is substantially equal to the outer shape of the IC chip 53 and slightly larger than it.

However, according to the above-mentioned counterbore processing, there is a drawback that a perfectly rectangular cavity 52 cannot be obtained because the four corners of the cavity 52 to be formed inevitably have Rs according to the bite used. . Therefore, as shown in FIG. 10, in order to mount the rectangular IC chip 53, it is necessary to make the cavity 52 much larger than the size of the IC chip 53.

However, in such a case, the IC chip 5
A gap 56 is formed between the side surface of the substrate 3 and the inner wall surface of the cavity 52, which causes a problem of increasing the bonding distance between the substrate and the IC chip. Therefore, it becomes difficult to surely perform wire bonding 54 between them, and high mounting reliability cannot be obtained. Further, if there is such a gap 56, the space where components can be mounted on the substrate 50 is relatively reduced, so that high-density mounting cannot be performed.

[0008] Further, the above-mentioned counterbore processing not only has the drawback that precise position control is difficult,
There is a drawback that it takes a lot of time and manufacturing cost to perform processing on a plurality of locations. Therefore, even if an attempt is made to manufacture a recent electronic component mounting board (so-called multi-chip module) having a large number of cavities 52, it is difficult to reduce the cost and improve the quality.

Further, in the case where the electronic component mounting board is a multilayer board 57 as shown in FIG. 11, if the depth of the counterbore processing is not properly controlled, a part of the inner layer conductor circuit 58 may be damaged. For this reason, conventionally, measures such as providing the inner conductor circuit 58 while avoiding the lower surface of the cavity 52 are taken. However, in such a case, the wiring flexibility of the inner layer conductor circuit 58 is impaired, and as a result, it becomes difficult to achieve high-density mounting.

The present invention has been made in view of the above circumstances, and an object of the present invention is to mount an electronic component on which mounting reliability can be improved and high density mounting and cost reduction can be achieved. It is to provide a substrate and a manufacturing method thereof.

[0011]

In order to solve the above-mentioned problems, according to a first aspect of the present invention, a metal layer for mounting electronic parts is formed on a surface of a substrate, and the metal layer is mounted on the metal layer. The gist of the invention is an electronic component mounting substrate in which an insulating layer made of a photosensitive resin is formed and an opening for exposing at least a part of the metal layer is formed in the insulating layer.

According to a second aspect of the present invention, an insulating layer made of a photosensitive resin is formed on the surface of the substrate, and a recess or opening for mounting electronic parts is formed at a predetermined portion of the insulating layer. The gist of the present invention is an electronic component mounting substrate having a metal layer formed on the inner wall surface of the recess or opening.

In this case, the inner layer conductor circuit may be formed on the substrate, or the outer layer conductor circuit for bonding may be provided on the surface of the insulating layer in the vicinity of the recess or opening for mounting the electronic component. Further, an insulating layer may be formed on the outer layer conductor circuit so that at least a part of the outer layer conductor circuit for bonding is exposed, and the outer layer conductor circuit for bonding may be formed on the insulating layer.

According to a third aspect of the present invention, an insulating layer made of a photosensitive resin is formed on the surface of the substrate, and then a predetermined portion of the insulating layer is exposed and developed, so that the insulating layer is exposed to electrons. The gist of the invention is to form a metal layer by electroless plating after forming a recess or opening for mounting components.

According to a fourth aspect of the present invention, a metal layer for mounting electronic parts is formed on the surface of the substrate, an insulating layer made of a photosensitive resin is formed on the metal layer, and the insulating layer is formed. The gist is to form an opening in the insulating layer so that at least a part of the metal layer is exposed by exposing and developing a predetermined portion of the layer.

At this time, electroless metal plating may be applied to form a metal plating layer on the inner wall surface of the recess or opening and an outer layer conductor circuit on the surface of the insulating layer.

[0017]

According to the present invention, the opening or recess is formed by an optical method such as exposure and development for the insulating layer made of a photosensitive resin. It is not formed by a physical method. For this reason, unlike the conventional case, there is no case in which R corresponding to the diameter of the rotary cutting tool is attached to the processed portion. Therefore, according to the present invention, it becomes easy to match the outer shape and size of the opening or the like with that of the electronic component to be mounted in the opening or the like.

[0018]

EXAMPLES Each example embodying the present invention will be described in detail below. [Embodiment 1] First, an electronic component mounting substrate 1 of Embodiment 1 will be described with reference to FIGS. 1 and 2.

A wiring pattern 3a as an inner layer conductor circuit is formed on the surface of the insulating base material 2 constituting the substrate 1 of this embodiment.
Are formed. Further, a die pad 3b as a metal layer for mounting electronic components is formed in a solid shape on the same surface.

An insulating layer 4 made of a photosensitive resin is formed on the wiring pattern 3a and the die pad 3b. An interstitial via hole (hereinafter referred to as “IVH”) forming hole 5 is formed in a predetermined portion of the insulating layer 4 as an opening for exposing a part of the wiring pattern 3a.
Are formed.

The insulating layer 4 has a die pad 3b.
Of the cavity 6 as an opening for exposing a part of
Are formed. On the inner wall surface of the cavity 6, an electroless copper plating layer 8c is formed as a metal layer for mounting electronic components.

An IC chip 7 as an electronic component is mounted in the cavity 6. Bonding pads (hereinafter referred to as "second pads") 8b as outer layer conductor circuits for bonding are regularly arranged around the cavity 6 on the insulating layer 4. On the other hand, I
A plurality of bonding pads (hereinafter referred to as “first pads”) 9 are also formed on the C chip 7 side. Each second pad 8b and each first pad 9 are electrically connected by wire bonding 10.

On the surface of the insulating layer 4, a wiring pattern 8a as an outer conductor circuit is formed in a region around the cavity 6 and the second pad 8b. The outer layer wiring pattern 8a and the inner layer wiring pattern 3a are
I composed of the IVH forming hole 5 and the electroless copper plating layer 8d
It is electrically connected via VH11.

In this embodiment, the cavity 6, which is a portion for mounting the square IC chip 7, has a cross section substantially equal to the outer shape of the IC chip 7 and has R at four corners.
There is no such thing (see Fig. 2).

Next, a procedure for producing the electronic component mounting substrate 1 will be described with reference to FIGS. 1 (a) to 1 (d). A wiring pattern 3a and a die pad 3b are formed according to a usual subtractive method using a glass-triazine copper clad laminate in which a copper foil is attached to the insulating base material 2 as a starting material.

Next, after degreasing, pickling, buffing, washing and drying, a photosensitive adhesive is applied to the surface of the insulating substrate 2 by screen printing or the like (see FIG. 1 (a)). . In this case, a so-called additive adhesive in which a resin filler is dispersed in a resin matrix is used. At this time, it is desirable to use a photosensitive resin as the resin matrix.

As the resin filler, a heat-resistant resin powder having an average particle diameter of 10 μm or less and a heat-resistant resin powder having an average particle diameter of 2 μm or less are aggregated to have an average particle diameter of 2 μm to 1
Aggregated particles with a size of 0 μm, average particle size of 2 μm
Mixture of heat-resistant resin powder having an average particle diameter of 2 μm or less and heat-resistant resin powder having an average particle diameter of 2 μm to 10 μm
It is preferable to select from pseudo particles formed by adhering at least one of a heat-resistant resin powder having an average particle diameter of 2 μm or less and an inorganic powder on the surface of the heat-resistant resin powder of μm.

Regarding the shape and depth of the anchor formed in such an adhesive layer, it is desirable that the surface roughness be within the range of 1 μm to 20 μm with fillers having different particle diameters. In this case, sufficient adhesion strength can be obtained for the conductor.

In this embodiment, the photosensitive adhesive is prepared by the following procedure. First, 60 parts by weight of a 50% acrylate of phenol novolac type epoxy resin (manufactured by Nippon Kayaku) and 40 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell, E-1001) were added to a butyl cellosolve acetate solution. Dissolve and then 5 parts by weight of 2-phenylimidazole (2PZ, manufactured by Shikoku Kasei) as a curing agent and 10 parts by weight of epoxy resin particles (manufactured by Toray, Trepal EP-B average particle size 3.9 μm).
And 20 parts by weight of epoxy resin particles (Toray, Trepal EP-B average particle size 0.5 μm) are mixed. The viscosity is adjusted to 120 cps by adding a dimethylformamide solution to the mixture and kneading the mixture with a homodisper disperser. As a result, the desired photosensitive adhesive is obtained.

Next, a photomask is arranged on the adhesive layer 12 and exposure and development are carried out, whereby the adhesive layer 1 is formed.
Part 2 is partially cured. By performing such photolithography, the insulating layer 4 is formed on the surface of the insulating base material 2.
Is formed. In addition, a cavity 6 having a square cross section and an IVH forming hole 5 as shown in FIG. 1B are formed in predetermined portions of the obtained insulating layer 4.

After the surface of the insulating layer 4 is roughened by chromic acid treatment, catalyst nuclei for depositing electroless copper plating are provided on the roughened surface 4a thus obtained. Further, a plating resin 13 is formed by applying a photosensitive resin on the insulating layer 4 and exposing and developing it.

After activating the catalyst nuclei, plating is performed using an electroless copper plating bath to deposit plated copper on the portions where the plating resist 13 is not formed. Through this process, the surface of the insulating layer 4 has a wiring pattern 8a and a second pad 8 as shown in FIG. 1 (c).
b is formed. At the same time, the inner wall surface of the cavity 6 and IV
Electroless copper plating layers 8c and 8d are formed on the inner wall surfaces of the H forming holes 5, respectively. After that, the plating resist 13 that is no longer needed is peeled off.

After mounting the IC chip 7 in the cavity 6, wire bonding 10 is performed to finally obtain the electronic component mounting substrate 1 as shown in FIGS. 1D and 2.

The electronic component mounting substrate 1 of this embodiment is characterized in that the cavity 6 is formed by an optical method called photolithography. Therefore, unlike a cavity formed by a conventional physical method such as a counterbore process, R corresponding to a bite is not attached to the four corners. Moreover, according to this method, it is possible to perform the processing with higher precision as compared with the spot facing processing or the like.

Therefore, in this embodiment, it is easy to obtain the cavity 6 having substantially the same outer shape and size as the IC chip 7. Then, there is almost no gap between the side surface of the IC chip 7 and the inner wall surface of the cavity 6.

As a result, the distance between the first pad 9 and the second pad 8b, that is, the bonding distance is shortened, and the mounting reliability is improved. Further, the elimination of the gap increases the space in which components can be mounted on the board 1,
It is convenient for achieving high-density packaging.

Further, in the case of this embodiment, there is an advantage that the cavity 6 is formed at the same time when the build-up layer forming process is performed. Therefore, no special process or tool is required to form the cavity 6. Therefore, problems such as an increase in the number of steps and a high cost can be avoided. [Embodiment 2] Next, the electronic component mounting substrate 21 of Embodiment 2 will be described.
Will be described with reference to FIG.

In the substrate 21 of this embodiment, unlike the case of the first embodiment, the insulating layer 4 made of a photosensitive resin is directly formed on the surface of the insulating base material 2. A cavity 22 as an opening for mounting an electronic component is provided at a predetermined portion of the insulating layer 4.
Are formed. On the inner wall surface of the cavity 22,
An electroless copper plating layer 8e as a metal layer is formed.

The IC chip 7 is mounted in the cavity 22 as in the first embodiment.
A plurality of second pads 8b are regularly arranged around the cavity 6 on the insulating layer 4. On the other hand, a plurality of first pads 9 are formed on the IC chip 7 side. Each second pad 8b and each first pad 9 are electrically connected by wire bonding 10.

On the surface of the insulating layer 4, a wiring pattern 8a as an outer conductor circuit is formed in a region around the cavity 22 and the second pad 8b. The cavity 22 in the present embodiment also has a cross section that is substantially the same as the outer shape of the IC chip 7 and has no R at the four corners as in the first embodiment (see FIG. 3).

Next, a procedure for manufacturing the electronic component mounting board 21 will be described. First, the resin insulating base material 2 is degreased, pickled, buffed, washed with water and dried, and then a photosensitive adhesive is applied to the surface by screen printing or the like. In this example, the same adhesive for additive as in Example 1 is used.

Next, a photomask is placed on the adhesive layer, and exposure and development are performed to partially cure the adhesive layer. By performing such photolithography, the insulating layer 4 including the cavity 22 having a square cross section is formed.

Then, the surface of the insulating layer 4 is roughened by the chromic acid treatment and the catalyst nuclei are applied in the same procedure as in Example 1, and then a photosensitive resin is applied onto the insulating layer 4. Further, by exposing and developing, a plating resist is formed on a predetermined portion on the insulating layer 4.

Here, after activating the catalyst nuclei, electroless copper plating is performed to deposit plated copper on the portions where the plating resist is not formed. Through this process, the wiring pattern 8a and the second pad 8b are formed on the surface of the insulating layer 4. At the same time, an electroless copper plating layer 8e is formed on the inner wall surface of the cavity 22. After this, the plating resist that is no longer needed is removed.

Then, the IC chip 7 is placed in the cavity 22.
After mounting the electronic component, wire bonding 10 is performed, and finally the electronic component mounting substrate 2 in the state as shown in FIG.
Set to 1.

Now, the cavity 2 of the substrate 21 of the present embodiment.
2 is also characterized by being formed by an optical method called photolithography as in the first embodiment. Therefore, the cavities 22 each having a square cross-section with no R at the four corners are accurately formed, and the same operation and effect as in the first embodiment can be obtained. Therefore, even in the case of such a configuration, it is possible to surely improve the mounting reliability of the substrate 21, high density mounting, and cost reduction. [Embodiment 3] Next, the electronic component mounting substrate 31 of Embodiment 3 will be described.
Will be described with reference to FIGS. 4 and 5.

On the surface of the insulating base material 2 which constitutes the substrate 31 of this embodiment, the wiring pattern 3 as an inner layer conductor circuit is formed.
a is formed. Further, a die pad 3b as a metal layer for mounting electronic components is formed in a solid shape on the same surface.

On the wiring pattern 3a and the die pad 3b, there is formed a so-called build-up layer in which insulating layers 32 and 33 made of a photosensitive resin and conductor layers are alternately laminated.

The IVH forming hole 5 as an opening for exposing a part of the wiring pattern 3a is formed in a predetermined portion of the insulating layer (hereinafter referred to as "inner insulating layer") 32 on the inner side of the buildup layer. Are formed.

The inner insulating layer 32 has a die pad 3b.
Of the cavity 6 as an opening for exposing a part of
Are formed. On the inner wall surface of the cavity 6, an electroless copper plating layer 8c is formed as a metal layer for mounting electronic components. The IC chip 7 is placed in the cavity 6.
Is installed. A second pad 8b as an outer conductor circuit for bonding is regularly arranged around the cavity 6 on the inner insulating layer 32.

In the area around the second pad 8b, a wiring pattern 8a is formed as an outer conductor circuit. The wiring patterns 3a and 8a are electrically connected to each other through an IVH 11 including an IVH forming hole 5 and an electroless copper plating layer 8d.

On the wiring pattern 8a and the second pad 8b on the surface of the inner insulating layer 32, an insulating layer (hereinafter referred to as "outer insulating layer") 33 on the outer side of the buildup layer is further formed. A large opening 34 is provided at a predetermined portion of the outer insulating layer 33 so as to expose a part of the second pad 8b and the cavity 6 together.

A second pad 35b as an outer conductor circuit for bonding is regularly arranged around the opening 34 on the outer insulating layer 33. Further, a wiring pattern 35a as an outer conductor circuit is formed in a region around the second pad 35b.

Further, in the outer insulating layer 33, an IVH forming hole 36 is formed as an opening for exposing a part of the wiring pattern 8a on the inner insulating layer 32.
The wiring patterns 35a and 8a are connected to each other by the IVH.
IV consisting of formation hole 36 and electroless copper plating layer 35c
It is electrically connected via H37.

Also in the substrate 31 of this embodiment, as in the case of the first and second embodiments, the cavity 6 has substantially the same outer shape as that of the IC chip 7 having a square cross section and has no R at the four corners. (See FIG. 5). The opening 34 exposing the cavity 6 is slightly larger than the cavity 6. Further, the cross-sectional shape of the large opening 34 is also the same as that of the cavity 6, and there is no R at the four corners.

That is, it can be said that the substrate 31 of the present embodiment has a cavity having a two tier structure including the cavity 6 and the opening 34. Also,
In the cavity of the two-tier structure, the lower second pad 8b and the upper second pad 35b are arranged in a staggered manner as shown in FIG. Each of the second pads 8b and 35b and the first pad 9 are electrically connected by wire bonding 10.

Next, a procedure for manufacturing the electronic component mounting substrate 31 will be described with reference to FIGS. 4 (a) to 4 (d).
First, similar to the manufacturing procedure in the first embodiment, the wiring pattern 3a and the die pad 3b are formed on the insulating base material 2 by the process of the subtractive method.

Next, after degreasing and the like, a photosensitive adhesive is applied to the surface of the insulating base material 2 and exposed and developed. By performing such photolithography, the inner insulating layer 32 including the cavity 6 having a square cross section and the IVH forming hole 5 is formed on the insulating base material 2.

Then, as in the case of Example 1, the inner insulating layer 32 is subjected to surface roughening treatment, catalyst nucleus application, plating resist formation and catalyst nucleus activation treatment. Thereafter, plating is performed using an electroless copper plating bath to form the wiring pattern 8a, the second pad 8b, and the electroless copper plating layers 8c and 8d on predetermined portions. The lower half of the buildup layer is formed by the process described above. After this, the plating resist that is no longer needed is removed.

Subsequently, the basic process of the build-up method described above is repeatedly performed to form the upper half of the build-up layer. First, the adhesive is applied to the surface of the inner insulating layer 32 on which the wiring pattern 8a and the like are formed (see FIG. 4A). Further, a photomask is arranged on the adhesive layer 38, and exposure and development are performed to partially cure the adhesive layer 38.

By performing such photolithography, the outer insulating layer 33 having the opening 34 having a square cross section and the IVH forming hole 36 is formed (see FIG. 4B).

Then, after performing a surface roughening treatment on the outer insulating layer 33, catalyst nuclei are applied to the obtained roughened surface 33a. Further, the photosensitive resin for the plating resist is applied and exposed and developed to form the plating resist 39 on a predetermined portion of the surface of the outer insulating layer 33.

Further, a photosensitive resin different from the photosensitive resin for the plating resist is applied, exposed and developed to form a mask 40 for covering the opening 34. The mask 40 is provisionally arranged for the purpose of avoiding a short circuit between the second pads 8b due to the deposition of plating metal. Here, after activating the catalyst nuclei, electroless copper plating is performed to deposit plated copper on the exposed portion.

Through this treatment, the outer insulating layer 3
The wiring pattern 35a and the second pad 35 on the surface of
b is formed, and at the same time, an electroless copper plating layer 35c is formed on the inner wall surface of the IVH forming hole 36 (see FIG. 4 (d)).
After this, the plating resist 39 and the mask 4 which are no longer needed
Peel 0.

After mounting the IC chips 7 in the cavities 6, wire bonding 10 is performed in a staggered manner, and finally the electronic component mounting substrate 31 as shown in FIGS. 4D and 5 is obtained. To do.

The substrate 31 of this embodiment is characterized in that both the cavity 6 and the large opening 34 are formed by the optical technique of photolithography as in the first and second embodiments. Therefore, it becomes possible to accurately process these into a square cross section with no R at the four corners, and the same effects and advantages as in the first and second embodiments can be obtained. Therefore, even with such a configuration, it is possible to surely improve the mounting reliability of the substrate 31, the high-density mounting and the cost reduction.

Further, in the case of the substrate 31 of this embodiment having the cavity of the two-tier structure, the second pads 8b and 35 are used.
Since it is possible to increase the number of arrangements of b, it is possible to realize higher density mounting. Even in this case,
Since the bonding distance is maintained to some extent,
There is an advantage that mounting reliability is not lowered.

The present invention is not limited to the first to third embodiments described above, but can be modified as follows. For example, (a) as in the substrate 41 of another example 1 shown in FIG.
The recess 42 for mounting electronic components may be provided in the above. According to this structure, the inner layer conductor circuit 3 such as the wiring pattern 3a can be routed to the region on the lower surface side of the recess 42, so that the degree of freedom of wiring is increased.

Further, according to this structure, unlike the conventional recess for mounting an electronic component by counterboring, it is possible to secure the adhesion strength of the plating layer formed in that portion. That is, in the present invention, the insulating layer 4 is formed by an additive adhesive, and a suitable anchor is formed by roughening the surface by the above method. This is because the counterbore processing causes the cut glass fibers to protrude into the recesses for mounting electronic components, which is not suitable as a surface for forming the plating layer.

In addition to such advantages, according to the present modification 1, even if the signal line (for example, the wiring pattern 3a) is present on the lower surface or the side surface of the recess 42, the signal line is provided due to the presence of the plating layer surrounding the signal line. There is also an advantage that no noise is mixed into the chip.

(B) It is of course possible to form a cavity having a three-tier structure like the substrate 43 of the second example shown in FIG. In this substrate 43, another insulating layer 44a is provided on the outer layer side of the outer insulating layer 33, and the insulating layer 44a is provided with another opening 44b for exposing the opening 34. A plurality of second pads 44c are provided around the opening 44b.

The structure is not limited to such a three-tier structure, and a higher-order structure such as a four-tier or a five-tier structure is also possible. (C) Further, as in another example 3 shown in FIG. 8, a substrate 45 having a 3-tier structure having an opening 46 having a complicated shape may be used. The advantage of the structure of the substrate 45 is that the bonding distance between the uppermost second pad 44c and the first pad 9 becomes shorter.

(D) The electronic components to be mounted on the board are
It may be an active component such as the IC chip 7 or a passive component such as a chip resistor or a chip capacitor. Further, it is of course possible to embody the present invention in a multi-chip module having a plurality of large and small cavities as an electronic component mounting portion for mounting an active component or a passive component. In this case, according to the present invention in which the cavity is formed by photolithography,
The cost can be surely reduced.

(E) In the case of manufacturing the above multi-chip module, an ordinary cavity,
It is also possible to mix two-tier structure cavities and three-tier structure cavities.

(F) By performing the photolithography as in the present invention, it is possible to form an opening or a recess for fitting a heat sink to a portion which will be the back side of an electronic component.

(G) As a method for forming the inner layer conductor circuit on the insulating base material, not only the subtractive process shown in Examples 1 and 3 but also the additive process can be adopted. is there.

(H) As the resin for forming the insulating layer, another resin different from the additive adhesive used in Examples 1 to 3 can be selected. (I) The insulating base material on which the build-up layer is formed is not limited to the one made of resin, and may be made of ceramics such as aluminum nitride.

[0078]

As described above in detail, according to the electronic component mounting substrate and the method of manufacturing the same of the present invention, it is possible to improve the mounting reliability and to achieve high density mounting and cost reduction. It has an excellent effect that

[Brief description of drawings]

1A to 1D are partial schematic cross-sectional views showing a manufacturing process of a substrate for mounting electronic components according to a first embodiment.

FIG. 2 is a partial schematic plan view showing the electronic component mounting substrate of the first embodiment.

FIG. 3 is a partial schematic cross-sectional view showing an electronic component mounting substrate of Example 2.

4A to 4D are partial schematic cross-sectional views showing a manufacturing process of an electronic component mounting substrate according to a third embodiment.

FIG. 5 is a partial schematic plan view showing an electronic component mounting substrate of Example 3;

FIG. 6 is a partial schematic cross-sectional view showing an electronic component mounting substrate of another example 1.

FIG. 7 is a partial schematic plan view showing an electronic component mounting substrate of Modification 2.

FIG. 8 is a partial schematic plan view showing an electronic component mounting board of Modification 3;

FIG. 9 is a partial schematic cross-sectional view showing a conventional electronic component mounting board.

FIG. 10 is a partial schematic plan view showing a conventional electronic component mounting substrate.

FIG. 11 is a partial schematic cross-sectional view for explaining a problem in a manufacturing process of a conventional electronic component mounting substrate.

[Explanation of symbols]

1, 21, 41, 43, 45 ... Electronic component mounting substrate, 3
a ... Wiring pattern as inner layer conductor circuit, 3b ... Metal layer for mounting electronic parts, 4, 22, 32, 33, 44a ... Insulating layer, 6 ... Cavity as opening, 8a ... Wiring pattern as outer layer conductor circuit , 8e ... Metal layer, 8b, 35
b, 44c ... Bonding pad as outer layer conductor circuit for bonding, 8c ... Metal plating layer, 22 ... Cavity as opening for mounting electronic parts, 42 ... Recess for mounting electronic parts.

Claims (8)

[Claims] 1. A metal layer (3b) for mounting an electronic component is formed on a surface of a substrate (1, 21, 43, 45), and an insulating layer (4) made of a photosensitive resin is formed on the metal layer (3b). 32) is formed, and an opening (6) for exposing at least a part of the metal layer (4, 32) is formed in the insulating layer (4, 32). 2. An insulating layer (4) made of a photosensitive resin is formed on the surface of a substrate (21, 41), and a recess (42) or an opening for mounting an electronic component is formed in a predetermined portion of the insulating layer (4). (2
2) is formed, and the recess (42) or the opening (2) is formed.
An electronic component mounting board having a metal layer (8e) formed on the inner wall surface of 2). 3. The electronic component mounting board according to claim 1, wherein an inner layer conductor circuit (3a) is formed on the board (1, 31, 41). 4. A recess (42) or opening (6, 2) for mounting the electronic component on the surface of the insulating layer (4, 33).
In the vicinity of 2), an outer layer conductor circuit (8b) for bonding
4. The method according to claim 1, further comprising:
The electronic component mounting substrate according to item. 5. An outer layer conductor circuit for bonding (8)
an insulating layer (33, 44a) is formed on the outer conductor circuit (8b) so that at least a part of b) is exposed;
The electronic component mounting board according to claim 4, further comprising outer layer conductor circuits (35b, 44c) for bonding formed on the insulating layers (33, 44a). 6. An insulating layer (4) made of a photosensitive resin is formed on the surface of a substrate (21, 41), and the insulating layer (4) is exposed and developed to expose the insulating layer (4). 4) A method for manufacturing a board for mounting electronic parts, which comprises forming a recess (42) or an opening (22) for mounting electronic parts in 4) and then forming a metal layer (8e) by electroless plating. 7. A metal layer (3b) for mounting electronic parts is formed on the surface of a substrate (1, 31, 43, 45), and an insulating layer (4) made of a photosensitive resin is formed on the metal layer (3b). , 32) is formed, and a predetermined portion of the insulating layer (4, 32) is exposed.
By developing, the opening (6) that exposes at least a part of the metal layer (3b) is formed in the insulating layer (4).
32) A method for manufacturing an electronic component mounting substrate, which is characterized in that 8. A metal plating layer (8c, 8e) is formed on the inner wall surface of the recess (42) or the opening (6, 22) by applying electroless metal plating, and the insulating layer (4) is formed. The method for manufacturing an electronic component mounting substrate according to claim 6 or 7, wherein outer layer conductor circuits (8a, 8b) are formed on the surface of the substrate.