KR100651320B1 - Board on chip ball grid array board and method for manufacturing the same - Google Patents

Abstract

The present invention removes the plating lead wire of the wire bonding pad and the solder ball pad, and then forms a window for wire bonding, thereby generating a metal burr in the window. The present invention relates to a board on chip ball grid array (BOC-BGA) substrate and a method of manufacturing the same, which prevents product defects caused by metal burrs.

BOC, BGA, BOC-BGA, Board-on-Chip, Plating Leads, Printed Circuit Boards

Description

Board on chip ball grid array board and method for manufacturing the same

1A and 1B are cross-sectional and top views of a conventional board-on-chip ball grid array package.

2A to 2E are cross-sectional views illustrating a flow of a method of manufacturing a conventional board-on-chip ball grid array substrate.

3 is a plan view illustrating a problem of the window forming process illustrated in FIG. 2E.

4A to 4H are cross-sectional views illustrating a flow of a method of manufacturing a board-on-chip ball grid array substrate according to a first embodiment of the present invention.

FIG. 5 is a plan view illustrating a window forming process illustrated in FIG. 4H.

6A to 6L are cross-sectional views illustrating a flow of a method of manufacturing a board-on-chip ball grid array substrate according to a second embodiment of the present invention.

FIG. 7 is a plan view illustrating a window forming process illustrated in FIG. 6L.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board on chip ball grid array (BOC-BGA) substrate and a method of manufacturing the same, and more particularly, to a wire bonding pad and a solder ball pad. BOC-BGA substrate to prevent the occurrence of metal burrs in the window and to prevent product defects caused by the metal burrs by forming a window for wire bonding after removing the plating lead wire It relates to a manufacturing method.

Recently, semiconductor technology is rapidly increasing in speed and density of integrated circuits. Accordingly, there is a need to shorten the overall signal transfer time between integrated circuits, and a technique for shortening the signal path between integrated circuits is required. As a solution to this need, the BOC-BGA package has been proposed.

1A and 1B are cross-sectional and top views of a conventional BOC-BGA package, disclosed in US Pat. No. 6,667,560.

As shown in FIGS. 1A and 1B, a conventional BOC-BGA package has solder balls 100 disposed in a length direction of a printed circuit board 122. In addition, a semiconductor die 114 is attached to the printed circuit board by adhesive means 116. A wire 118 emerges from the semiconductor die 114 and passes through a hole 120 of the printed circuit board 122 to be bonded to a trace (not shown). The sealing material 110 of the upper surface of the printed circuit board 122 covers the wire 118 and the hole 120 to protect the wire 118, and the sealing material 112 of the lower surface of the printed circuit board 122 It is formed between the printed circuit board 122 and the semiconductor die 114.

For the BOC-BGA package described above, a BOC-BGA substrate was fabricated by the method shown in FIGS. 2A-2E.

2A to 2E are cross-sectional views illustrating a flow of a conventional method for manufacturing a BOC-BGA substrate, and FIG. 3 is a plan view illustrating a problem of the window forming process illustrated in FIG. 2E.

As shown in FIG. 2A, a copper foil laminated plate 210 having copper foil layers 212 and 212 ′ coated on both surfaces of the insulating layer 211 is prepared.

As shown in FIG. 2B, a predetermined circuit pattern 213 is formed on the upper and lower copper foil layers 212 and 212 ′ using a photo-lithography process.

As shown in FIG. 2C, solder resist patterns 214 and 214 ′ are formed on upper and lower surfaces of the copper clad laminate 210 on which the circuit patterns 213 are formed.

As shown in FIG. 2D, the Ni / Au plating layer 215 is formed on the circuit pattern 213 on which the solder resist patterns 214 and 214 'are not formed. The circuit pattern 213 on which the Ni / Au plating layer 215 is formed includes a wire bonding pad 216 and a solder ball pad 217.

As shown in FIG. 2E, by using a router bit to form a window a for wire bonding in the center of the copper-clad laminate 210, while simultaneously cutting the plating lead wire 218, the BOC-BGA substrate ( 200) was prepared.

However, as shown in FIG. 3, the conventional BOC-BGA substrate 200 uses the router bit 250 to plate the lead wire 218 on the cutting surface due to the heating of the rotary cutting tool in the process of forming the window a. There was a problem that the metal burr (220) occurs.

The metal burr 220 has become a serious problem of connecting the adjacent wire bonding pads 216 of the BOC-BGA substrate 200 to cause product defects.

In order to remove the metal burr 220, there is a method of forming the window (a), and then removing it by water spraying, but the metal burr 220 is strongly attached to the cutting surface due to the heating of the rotary cutting tool. Therefore, there was a problem that it is difficult to completely remove even by a method such as water spray.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a board on chip ball grid array substrate in which a metal burr does not occur in a window and a method of manufacturing the same.

In order to solve the above technical problem, the board-on-chip ball grid array substrate according to the present invention comprises a disk having a first surface and a second surface, the window is formed in the center penetrating from the first surface to the second surface; And a wire bonding pad area formed around the window of the first surface, the wire bonding pad area having a distal end formed at a predetermined distance from the inner wall of the window.

In another preferred embodiment, the wire bonding pad region of the board-on-chip ball grid array substrate according to the present invention further includes a remaining plating lead wire, and the distal end of the remaining plating lead wire is formed at a predetermined distance from an inner wall of the window. It is characterized by that.

In order to solve the above technical problem, the method of manufacturing a board-on-chip ball grid array substrate according to the first aspect of the present invention (A) to form a circuit pattern including a wire bonding pad, a solder ball pad and a plating lead wire on the disc step; (B) forming a solder resist pattern on the disc including an opening corresponding to the wire bonding pad, the solder ball pad, and the plating lead wire; (C) forming a plating resist pattern including an opening corresponding to the wire bonding pad and the solder ball pad on the original plate on which the solder resist pattern is formed and the plating lead line; (D) forming a gold plating layer on the wire bonding pad and the solder ball pad by performing electrolytic gold plating using the plating lead wire; (E) removing the plating resist pattern; (F) etching the plating lead wire using the solder resist pattern and the gold plated layer as an etching resist; And (G) forming a window for wire bonding in the center of the disc.

In order to solve the above technical problem, a method of manufacturing a board-on-chip ball grid array substrate according to a second aspect of the present invention comprises the steps of: (A) forming a circuit pattern including a wire bonding pad and a solder ball pad on the disc; (B) forming a thin electroless copper plating layer on the disc; (C) forming an etching resist pattern on a portion of the electroless copper plating layer to be used as a plating lead wire; (D) etching to remove the electroless copper plating layer on which the etching resist pattern is not formed; (E) removing the etch resist pattern; (F) forming a plating resist pattern on the original plate including openings corresponding to the wire bonding pads and the solder ball pads; (G) forming a gold plating layer on the wire bonding pad and the solder ball pad by performing electrolytic gold plating using the electroless copper plating layer as a plating lead; (H) removing the plating resist pattern; (I) removing the electroless copper plating layer used as the plating lead wire; (J) forming a solder resist pattern comprising openings corresponding to the wire bonding pads and the solder ball pads; And (K) forming a window for wire bonding in the central portion of the disc.

Hereinafter, a board on chip ball grid array (BOC-BGA) and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

4A to 4H are cross-sectional views illustrating a flow of a method of manufacturing a BOC-BGA substrate according to a first embodiment of the present invention, and FIG. 5 is a plan view illustrating a window forming process illustrated in FIG. 4H.

As shown in FIG. 4A, the original plate 1100 is prepared from a copper-clad laminate in which copper foil layers 1120 and 1120 'are coated on both surfaces of the insulating layer 1110.

Here, the copper clad laminate used as the disc 1100 may be a glass / epoxy copper clad laminate, a heat resistant resin copper clad laminate, a paper / phenolic copper clad laminate, a high frequency copper clad laminate, a flexible copper clad laminate, a composite copper clad laminate. Laminates and the like can be used. However, in the production of the BOC-BGA substrate 1000 according to the present invention, it is preferable to use a glass / epoxy copper clad laminate using glass fibers and an epoxy resin or a heat-resistant resin copper clad laminate using a glass fiber and a BT resin (Bismaleimide Triazine resin). desirable.

In the embodiment, although the disc 1100 having a two-layer structure is shown, the disc having a multi-layer structure such as four layers, six layers, and eight layers in which a predetermined circuit pattern and via holes are formed in the inner layer according to the purpose or purpose of use. 1100 may also be used.

As shown in FIG. 4B, a circuit pattern 1130 including wire bonding pads, solder ball pads, and plating lead wires is formed on upper and lower copper foil layers 1120 and 1120 ′ of the original plate 1100. Form.

The process of forming the circuit pattern 1130 is preferably a photo-lithography process using a dry film or a liquid photosensitive material.

In this case, the dry film or the photosensitive material of a liquid state is apply | coated to the upper and lower copper foil layers 1120 and 1120 'of the original plate 1100. Next, by using a photo mask on which a predetermined pattern corresponding to the circuit pattern 1130 is formed, the dry film or the liquid photosensitive material is exposed and developed, thereby etching the dry film or the photosensitive material in the liquid state. Forming an etching resist pattern. Subsequently, the original plate 1100 is immersed in an etchant to remove the upper and lower copper foil layers 1120 and 1120 ′ where the dry film or the liquid photosensitive material is not applied, thereby forming the circuit pattern 1130. Next, the dry film or liquid photosensitive material is removed.

Among them, the method using the photosensitive material in the liquid state can be applied thinner than the dry film, there is an advantage that can form a finer circuit pattern. In addition, when there are irregularities on the surfaces of the upper and lower copper foil layers 1120 and 1120 ′, there is also an advantage that can form a uniform surface by filling them.

As shown in FIG. 4C, solder resist patterns 1140 and 1140 ′ are formed on the original plate 1100 on which the circuit patterns 1130 are formed.

The openings in which the solder resist patterns 1140 and 1140 ′ are not formed include a wire bonding pad 1131, a solder ball pad 1132, a plating lead line 1133, and the like.

In an embodiment, the method of forming the solder resist patterns 1140 and 1140 'removes fingerprints, oil, dust, and the like from the original plate 1100 on which the circuit patterns 1130 are formed, and gives roughness to the surface of the original plate 1100. Perform pretreatment. Next, after apply | coating a soldering resist to the upper and lower surfaces of the original plate 1100, it is temporarily dried. Next, the solder resist patterns 1140 and 1140 'are formed by exposing and developing the solder resist using a photomask having a predetermined pattern corresponding to the solder resist patterns 1140 and 1140'. Subsequently, ultraviolet rays are irradiated to cure the ultraviolet rays, and the solder resist is completely cured using a dryer or the like. Subsequently, residues, foreign matters and the like of the solder resist remaining in the portion where the solder resist is removed are removed using plasma or the like.

As shown in FIG. 4D, a plating resist pattern 1200 for gold plating is then formed on the original plate 1100 on which the solder resist patterns 1140 and 1140 'are formed. Here, the opening in which the plating resist pattern 1200 is not formed includes a wire bonding pad 1131 and a solder ball pad 1132, and the plating resist pattern 1200 is formed on the plating lead line 1131.

In an embodiment, the process of forming the plating resist pattern 1200 may be formed by applying a dry film or a photosensitive material in a liquid state, followed by exposure and development.

In a preferred embodiment, since the solder resist patterns 1140 and 1140 'may be used as the plating resist patterns, a separate plating resist pattern 1200 may be formed on the circuit pattern 1130 on which the solder resist patterns 1140 and 1140' are not formed. ) Can be formed.

As shown in FIG. 4E, the gold plating layer 1150 using the plating lead wire 1333 as a surface treatment on the wire bonding pad 1131 and the solder ball pad 1132 on which the plating resist pattern 1200 of the original plate 1100 is not formed. To form.

Here, in the process of forming the gold plated layer 1150, it is preferable to form the gold plated layer 1150 by performing electrolytic gold plating using a DC rectifier after eroding the original plate 1100 in a gold plated working cylinder. It is more preferable to use a method of depositing gold by applying an appropriate current to the DC rectifier.

In addition, in order to increase adhesion with gold, it is more preferable to form a gold plated layer 1150 after plating nickel thinly.

As shown in FIG. 4F, the plating resist pattern 1200 is removed using a stripping solution.

As shown in FIG. 4G, the gold plating layer 1150 and the solder resist patterns 1140 and 1140 'formed on the wire bonding pads 1131 and the solder ball pads 1132 are used as etching resists, and the original plate 1100 is used as an etching solution. By immersion, the plating lead wire 1133 used in the gold plating process is removed.

In this case, since the nickel or gold plated layer 1150 may be etched in the case of the acid etchant, it is preferable to remove the plating lead line 1133 using the alkaline etchant.

As shown in FIG. 4H, a router bit is used to form a window A for wire bonding in the center of the original plate 1100.

Subsequently, by forming an outline of the original plate 1100 using a router or a power press, the BOC-BGA substrate 1000 according to the first embodiment of the present invention is manufactured.

As shown in FIGS. 4H and 5, the BOC-BGA substrate 1000 according to the first embodiment of the present invention has the wire bonding pad 133 removed since the plating lead wire 1133 is removed before the window A forming process. 1131 and the distal end P of the wire bonding pad region including the remaining plating lead wire 1333 (that is, the distal end P of the remaining plating lead wire 1333) is a predetermined distance from the inner wall W of the window A. Formed.

Therefore, the BOC-BGA substrate 1000 according to the first embodiment of the present invention does not process the metal layer by the rotary cutting tool in the process of forming the window A using the router bit 1300, so that the metal burr is cut on the cutting surface. It can be seen that (metal burr) does not occur.

6A to 6L are cross-sectional views illustrating a flow of a method of manufacturing a BOC-BGA substrate according to a second exemplary embodiment of the present invention, and FIG. 7 is a plan view illustrating a window forming process illustrated in FIG. 6L.

As shown in FIG. 6A, a master plate 2100 is prepared from a copper clad laminate having copper foil layers 2120 and 2120 ′ coated on both surfaces of the insulating layer 2110.

Here, the copper clad laminate used as the disc 2100 may be a glass / epoxy copper clad laminate, a heat resistant resin copper clad laminate, a paper / phenolic copper clad laminate, a high frequency copper clad laminate, a flexible copper clad laminate, a composite copper clad laminate, or the like. .

In the embodiment, although the disc 2100 having a two-layer structure is shown, the disc having a multi-layer structure such as four layers, six layers, and eight layers in which a predetermined circuit pattern and via holes are formed in the inner layer according to the purpose or purpose of use. 2100) may be used.

As shown in FIG. 6B, circuit patterns 2130 including wire bonding pads and solder ball pads are formed on upper and lower copper foil layers 2120 and 2120 ′ of the original plate 2100. Here, the circuit pattern 2130 does not include a plating lead wire for a gold plating layer forming process thereafter.

In an embodiment, the process of forming the circuit pattern 2130 preferably uses a photolithography process using a dry film or a photosensitive material in a liquid state.

As shown in FIG. 6C, an electroless copper plating layer 2200 having a thickness of about 0.2 μm to 0.5 μm is formed on the original plate 2100 on which the circuit pattern 2130 is formed in order to form a plating lead line for the gold plating layer forming process. .

Here, the electroless copper plating layer 2200 may be formed of a catalyst deposition method, a sputtering method, or the like.

Catalytic precipitation processes include degreasing, soft etching, pre-catalyst, catalysis, activation, electroless copper plating, and anti-oxidation. Thus, the electroless copper plating layer 2200 is formed on the original plate 2100 on which the circuit pattern 2130 is formed.

In addition, the sputtering method imparts an ion particle (for example, Ar ⁺ ) of a gas generated by a plasma or the like to a copper target, whereby an electroless copper plating layer ( 2200).

As shown in FIG. 6D, an etching resist pattern 2300 is formed on the portion to be used as the plating lead line in the original plate 2100.

The etching resist pattern 2300 may be formed by applying a dry film or a photosensitive material in a liquid state, followed by exposure and development.

As shown in FIG. 6E, the electroless copper plating layer 2200 of the portion where the etching resist pattern 2300 is not formed is removed by immersing the original plate 2100 on which the etching resist pattern 2300 is formed.

As in FIG. 6F, the etching resist pattern 2300 is removed using a stripping solution.

As shown in FIG. 6G, a plating resist pattern 2400 including an opening corresponding to the wire bonding pad 2131 and the solder ball pad 2132 of the disc 2100 is formed.

The plating resist pattern 2400 may be formed by applying a dry film or a photosensitive material in a liquid state, and then exposing and developing the coating layer.

As shown in FIG. 6H, a thin electroless copper plating layer 2200 is used as the plating lead wire, and the gold plating layer is surface treated on the wire bonding pad 2131 and the solder ball pad 2132 on which the plating resist pattern 2400 is not formed. And form 2150.

Here, in the process of forming the gold plated layer 2150, it is preferable to form the gold plated layer 2150 by performing electrolytic gold plating using a direct current rectifier after eroding the original plate 2100 in a gold plated working cylinder. It is more preferable to use a method of depositing gold by applying an appropriate current to the DC rectifier.

In addition, in order to increase the adhesiveness with gold, it is more preferable to form a gold plated layer 2150 after the nickel is plated thinly.

As in FIG. 6I, the plating resist pattern 2400 is removed using a stripping solution.

As shown in Fig. 6J, the original plate 2100 is immersed in the etchant to remove the thin electroless copper plating layer 2200 used as the plating lead wire.

As shown in FIG. 6K, solder resist patterns 2140 and 2140 ′ are formed on the disc 2100.

The openings in which the solder resist patterns 2140 and 2140 'are not formed include a wire bonding pad 2131 and a solder ball pad 2132.

In an embodiment, the method of forming the solder resist patterns 2140 and 2140 'removes fingerprints, oil, dust, and the like from the disk 2100 on which the circuit patterns 2130 are formed, and gives roughness to the surface of the disk 2100. Perform pretreatment. Next, after apply | coating a soldering resist to the upper and lower surfaces of the original plate 2100, it is temporarily dried. Next, the solder resist patterns 2140 and 2140 'are formed by exposing and developing the solder resist using a photomask having a predetermined pattern corresponding to the solder resist patterns 2140 and 2140'. Subsequently, ultraviolet rays are irradiated to cure the ultraviolet rays, and the solder resist is completely cured using a dryer or the like. Next, the residue, foreign matter, etc. of the solder resist which remain | survived in the part from which the solder resist was removed are removed using a plasma etc.

As shown in FIG. 6L, a router bit is used to form a window B for wire bonding in the center of the disc 2100.

Subsequently, the outer plate 2100 is formed by using a router or a power press to manufacture the BOC-BGA substrate 2000 according to the second embodiment of the present invention.

6L and 7, since the BOC-BGA substrate 2000 according to the second embodiment of the present invention has removed the plating lead wire 2200 before the window B forming process, the wire bonding pad ( The distal end P (ie, the distal end P of the wire bonding pad 2131) of the wire bonding pad region including 2131 is formed at a predetermined distance from the inner wall W of the window B.

Therefore, the BOC-BGA substrate 2000 according to the second embodiment of the present invention does not process the metal layer by the rotary cutting tool in the process of forming the window B by using the router bit 2500, so that the metal burr is cut on the cutting surface. It can be seen that (metal burr) does not occur.

Although the present invention has been described above, this is only one embodiment, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. . However, it will be confirmed through the claims that such changes and modifications fall within the scope of the present invention.

As described above, the board-on-chip ball grid array substrate and the method of manufacturing the same according to the present invention provide a plating lead wire of a wire bonding pad and a solder ball pad. After removal, by forming a window for wire bonding, there is an effect of preventing the occurrence of metal burrs in the window.

In addition, the board-on-chip ball grid array substrate and the method of manufacturing the same according to the present invention do not generate a metal burr in the window, thereby preventing the occurrence of product defects due to the metal burr.

Claims (7)

delete delete (A) forming a circuit pattern including a wire bonding pad, a solder ball pad, and a plating lead wire on a disc; (B) forming a solder resist pattern on the disc including an opening corresponding to the wire bonding pad, the solder ball pad, and the plating lead wire; (C) forming a plating resist pattern including an opening corresponding to the wire bonding pad and the solder ball pad on the original plate on which the solder resist pattern is formed and the plating lead line; (D) forming a gold plating layer on the wire bonding pad and the solder ball pad by performing electrolytic gold plating using the plating lead wire; (E) removing the plating resist pattern; (F) etching the plating lead wire using the solder resist pattern and the gold plated layer as an etching resist; And (G) manufacturing a board-on-chip ball grid array substrate, comprising the step of forming a window for wire bonding in the central portion of the disc. The method of claim 3, wherein In the step (F), the plating lead wire is etched with an alkaline etching solution using the solder resist pattern and the gold plating layer as an etching resist. The method of claim 3, wherein Step (G) is a method of manufacturing a board-on-chip ball grid array substrate, characterized in that for forming a window for wire bonding in the center of the disc using a router bit. (A) forming a circuit pattern including a wire bonding pad and a solder ball pad on a disc; (B) forming a thin electroless copper plating layer on the disc; (C) forming an etching resist pattern on a portion of the electroless copper plating layer to be used as a plating lead wire; (D) etching to remove the electroless copper plating layer on which the etching resist pattern is not formed; (E) removing the etch resist pattern; (F) forming a plating resist pattern on the disc including openings corresponding to the wire bonding pads and the solder ball pads; (G) forming a gold plating layer on the wire bonding pad and the solder ball pad by performing electrolytic gold plating using the electroless copper plating layer as a plating lead; (H) removing the plating resist pattern; (I) removing the electroless copper plating layer used as the plating lead wire; (J) forming a solder resist pattern comprising openings corresponding to the wire bonding pads and the solder ball pads; And (K) manufacturing a board-on-chip ball grid array substrate, comprising the step of forming a window for wire bonding in the central portion of the disc. The method of claim 6, The step (K) is a method for manufacturing a board-on-chip ball grid array substrate, characterized in that for forming a window for wire bonding in the center of the disc using a router bit.

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