JPH05152750A - Manufacture of multilayered wiring board - Google Patents

Manufacture of multilayered wiring board

Info

Publication number
JPH05152750A
JPH05152750A JP24797591A JP24797591A JPH05152750A JP H05152750 A JPH05152750 A JP H05152750A JP 24797591 A JP24797591 A JP 24797591A JP 24797591 A JP24797591 A JP 24797591A JP H05152750 A JPH05152750 A JP H05152750A
Authority
JP
Japan
Prior art keywords
film
resist film
wiring pattern
via hole
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24797591A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Tamura
浩悦 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24797591A priority Critical patent/JPH05152750A/en
Publication of JPH05152750A publication Critical patent/JPH05152750A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the occurrence of disconnection between a via hole and metallic wiring pattern and, it the same time, to reduce the number of processes by preventing the formation of a reversely tapered via hole on the wiring pattern. CONSTITUTION:In this high-density multilayered wiring board manufacturing method in which a polyimide film and metallic wiring pattern are formed, a wiring pattern is formed by irradiating a resist film 4 with excimer laser light and a via hole pattern is formed by irradiating a polyimide film 3 with excimer laser light after the films 3 and 4 are formed on the wiring pattern. Then a metallic thin film and a resist film are etched with excimer laser light in a conductor layer forming process. Therefore, the connectability of the wiring pattern can be improved and, accordingly, the manufacturing yield can be increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層配線基板の製造に
利用する。本発明は、コンピュータなどの電子機器に使
用する大規模集積回路(LSI)装着用高密度多層配線
基板の上下の導体層間を接続するビィアホール形成工程
を含む多層配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION The present invention is used for manufacturing a multilayer wiring board. The present invention relates to a method for manufacturing a multilayer wiring board including a via hole forming step of connecting upper and lower conductor layers of a large-scale integrated circuit (LSI) mounting high-density multilayer wiring board used for electronic equipment such as a computer.

【0002】[0002]

【従来の技術】従来の多層配線基板の製品方法のうち、
特にコンピュータなどの電子機器に使用する大規模集積
回路(LSI)装着用高密度多層配線基板の製造におけ
る上下の導体層を接続するビィアホールの形成は、図2
に示すように基板1上に金属配線パターン2を形成する
第一の工程と、配線パターン2の上に基板1の全面にわ
たって感光性ポリイミド膜9をスピンコート法によって
形成し低温乾燥する第二の工程と、感光性ポリイミド膜
9に所定の部分を遮蔽したガラスマスク10を介して紫
外線Sを照射する第三の工程と、紫外線Sを照射した感
光性ポリイミド膜9を現像して遮蔽した部分に対応する
部分の感光性ポリイミド膜9を除去してビィアホール6
を形成する第四の工程と、感光性ポリイミド膜9をキュ
アしてイミド化する第五の工程と、感光性ポリイミド膜
9の全面にわたって金属薄膜7を形成する第六の工程
と、金属薄膜7上に基板1の全面にわたってレジスト膜
4をスピンコート法によって形成し低温乾燥する第七の
工程と、レジスト膜4に所定の部分を遮蔽したガラスマ
スク10を介して紫外線Sを照射する第八の工程と、紫
外線Sを照射したレジスト膜4を現像して紫外線Sが照
射された部分のレジスト膜4を除去する第九の工程と、
レジスト膜4が除去された部分にメッキ8を形成する第
十の工程と、レジスト膜4を剥離する第十一の工程と、
金属薄膜7をドライエッチングで除去する第十二の工程
とにより行われていた。
2. Description of the Related Art Among conventional methods for producing a multilayer wiring board,
The formation of via holes connecting upper and lower conductor layers in the manufacture of a high-density multi-layer wiring board for mounting large-scale integrated circuits (LSI) used in electronic devices such as computers is particularly shown in FIG.
As shown in FIG. 1, a first step of forming a metal wiring pattern 2 on the substrate 1 and a second step of forming a photosensitive polyimide film 9 on the wiring pattern 2 over the entire surface of the substrate 1 by a spin coating method and drying at a low temperature. Step, a third step of irradiating the photosensitive polyimide film 9 with ultraviolet rays S through a glass mask 10 which shields a predetermined portion, and developing and shielding the photosensitive polyimide film 9 irradiated with the ultraviolet rays S to the shielded portion. The via hole 6 is formed by removing the photosensitive polyimide film 9 at the corresponding portion.
And a fifth step of curing the photosensitive polyimide film 9 to imidize it, a sixth step of forming the metal thin film 7 over the entire surface of the photosensitive polyimide film 9, and a metal thin film 7 A seventh step of forming a resist film 4 on the entire surface of the substrate 1 by a spin coating method and drying at low temperature, and an eighth step of irradiating the resist film 4 with ultraviolet rays S through a glass mask 10 which shields a predetermined portion. And a ninth step of developing the resist film 4 irradiated with the ultraviolet rays S to remove the resist film 4 in the portion irradiated with the ultraviolet rays S,
A tenth step of forming a plating 8 on the portion where the resist film 4 is removed, and an eleventh step of peeling the resist film 4;
And the twelfth step of removing the metal thin film 7 by dry etching.

【0003】[0003]

【発明が解決しようとする課題】このような従来の多層
配線基板の製造方法では、図2(b)に示す工程でスピ
ンコートによる基板内の膜厚のばらつきと、低温乾燥に
よる基板内の温度ばらつきとによる影響があり、また、
図2(c)に示す工程で露光による基板内の露光量のば
らつきの影響を受け、これらの悪影響が重なり、図2
(d)に示すように現像すると基板内でビィアホール6
の側面が正テーパー形(穴の上面が広く、底面が狭くな
る形状)と、逆テーパー形(穴の上面が狭く、底面が広
くなる形状)の両方のビィアホールが形成される。
In such a conventional method for manufacturing a multilayer wiring board as described above, in the step shown in FIG. 2B, variations in film thickness within the substrate due to spin coating and temperature inside the substrate due to low temperature drying are performed. There is an effect of variation and
In the process shown in FIG. 2C, the influence of the variation in the exposure amount in the substrate due to the exposure is influenced, and these adverse effects are overlapped.
When the development is performed as shown in (d), the via holes 6 are formed in the substrate.
The via holes of both the side having a positive taper shape (a shape in which the top surface of the hole is wide and the bottom surface is narrow) and the reverse taper shape (a shape in which the top surface of the hole is narrow and the bottom surface is wide) are formed.

【0004】逆テーパー形のビィアホールが形成される
と、上下の導体層を接続する工程において、図2(i)
に示すように逆テーパー形のビィアホールの側面にレジ
ストが残り、図2(j)のメッキ形成時にレジスト残り
の箇所で上下の導体層間の切断が生じやすく、いわゆる
パターンオープンが発生する欠点がある。
When the reverse taper type via hole is formed, in the step of connecting the upper and lower conductor layers, as shown in FIG.
As shown in FIG. 2, the resist remains on the side surface of the via hole of the inverse taper type, and there is a drawback that the upper and lower conductor layers are likely to be cut at the resist remaining portion at the time of plating formation in FIG.

【0005】本発明はこのような問題を解決するもの
で、レジスト残りによるパターンの切断を防止すること
ができる多層配線基板の製造方法を提供することを目的
とする。
The present invention solves such a problem, and an object of the present invention is to provide a method of manufacturing a multilayer wiring board which can prevent the pattern from being cut due to a resist residue.

【0006】[0006]

【課題を解決するための手段】本発明は、ポリイミドと
金属配線パターンを形成する多層配線基板の製造方法に
おいて、基板上に金属配線パターンを形成する第一の工
程と、前記配線パターン上に前記基板の全面にわたって
ポリイミド膜を形成して低温乾燥する第二の工程と、前
記ポリイミド膜をキュアしてイミド化する第三の工程
と、前記ポリイミド膜上に前記基板の全面にわたってレ
ジスト膜を形成して低温乾燥する第四の工程と、前記レ
ジスト膜に所定の部分をマスクにより遮蔽して除去し配
線パターン用の加工をする第五の工程と、前記レジスト
膜が除去された部分のビィアホール形成部のポリイミド
膜を除去してビィアホールを形成する第六の工程と、前
記基板上の全面にわたって金属薄膜を形成する第七の工
程と、前記レジスト膜上の金属薄膜を除去する第八の工
程と、前記ビィアホール部の金属薄膜上にメッキ層を形
成する第九の工程と、前記レジスト膜を除去する第十の
工程とにより製造することを特徴とする。
The present invention is a method of manufacturing a multilayer wiring board in which a polyimide and a metal wiring pattern are formed, the first step of forming a metal wiring pattern on the board, and the above-mentioned wiring pattern. A second step of forming a polyimide film over the entire surface of the substrate and drying at a low temperature, a third step of curing the polyimide film for imidization, and forming a resist film over the entire surface of the substrate on the polyimide film. And a fourth step of drying at low temperature, a fifth step of removing a predetermined portion of the resist film by masking and removing the resist pattern, and a via hole forming portion of the portion where the resist film is removed. Sixth step of removing the polyimide film to form a via hole, a seventh step of forming a metal thin film over the entire surface of the substrate, and the resist It is characterized by being manufactured by an eighth step of removing the upper metal thin film, a ninth step of forming a plating layer on the metal thin film of the via hole portion, and a tenth step of removing the resist film. To do.

【0007】前記ポリイミド膜の形成はスピンコート法
により行い、前記レジスト膜、前記ポリイミド膜、およ
び前記レジスト膜上の金属薄膜の除去はエキシマレーザ
光の照射によって行うことができる。
The polyimide film can be formed by spin coating, and the resist film, the polyimide film, and the metal thin film on the resist film can be removed by irradiation with excimer laser light.

【0008】[0008]

【作用】基板上に金属配線パターンを形成し、この配線
パターン上に基板の全面にわたってポリイミド膜をスピ
ンコート法によって形成し、低温乾燥する。続いてポリ
イミド膜をキュアしてイミド化し、そのポリイミド膜上
に基板の全面にわたってレジスト膜をスピンコート法に
より形成して低温乾燥する。
A metal wiring pattern is formed on a substrate, a polyimide film is formed on the wiring pattern over the entire surface of the substrate by a spin coating method, and is dried at a low temperature. Subsequently, the polyimide film is cured and imidized, a resist film is formed on the polyimide film over the entire surface of the substrate by a spin coating method, and is dried at a low temperature.

【0009】次いで、レジスト膜に所定の部分を遮蔽し
たマスクを介してエキシマレーザ光を照射し、レジスト
膜を除去して配線パターン用の加工を行い、レジスト膜
が除去された部分のビィアホール形成部のポリイミド膜
にもマスクを介してエキシマレーザ光を照射し、ポリイ
ミド膜を除去してビィアホールを形成する。ビィアホー
ル形成後、基板上の全面にわたって金属薄膜を形成し、
レジスト膜上の金属薄膜の部分にマスクを介してエキシ
マレーザ光を照射させ、金属薄膜を除去し、ビィアホー
ル部の金属薄膜上にメッキ層を形成した後に、レジスト
膜にエキシマレーザ光を照射させてレジスト膜を除去す
る。
Next, the resist film is irradiated with excimer laser light through a mask that shields a predetermined portion, the resist film is removed and wiring pattern processing is performed, and the via hole forming portion where the resist film is removed is formed. The polyimide film is also irradiated with excimer laser light through a mask to remove the polyimide film and form a via hole. After forming the via hole, form a metal thin film on the entire surface of the substrate,
Irradiate excimer laser light on the metal thin film part on the resist film through a mask to remove the metal thin film and form a plating layer on the metal thin film in the via hole part, then irradiate the excimer laser light on the resist film. The resist film is removed.

【0010】これにより、逆テーパ形のビィアホールが
形成されることがなくなり、レジストの抜け残り、絶縁
部のビィアホールからの抜け残り、およびそれに伴って
生じる断線をなくすことができ、製品歩留りをよくする
ことができる。
As a result, the reverse taper-shaped via hole is not formed, and it is possible to eliminate the remaining resist, the remaining insulating part from the via hole, and the resulting disconnection, thus improving the product yield. be able to.

【0011】[0011]

【実施例】次に、本発明実施例を図面に基づいて説明す
る。図1(a)〜(j)は本発明実施例における製造工
程の一例を示す断面図である。
Embodiments of the present invention will now be described with reference to the drawings. 1A to 1J are cross-sectional views showing an example of the manufacturing process in the embodiment of the present invention.

【0012】本実施例における製造工程は、まず、図1
(a)に示すように基板1の上に配線パターン2を形成
する。次に同図(b)に示すように基板1の表面の全面
にポリイミド膜3をスピンコート法によって塗布しオー
ブンで低温乾燥を行う。この状態ではポリイミド膜3の
膜厚は20μm〜30μmであり、まだイミド化されな
い。低温乾燥は温度70℃〜80℃で40分〜60分の
ベーキングを行う。
The manufacturing process in this embodiment is as follows.
As shown in (a), the wiring pattern 2 is formed on the substrate 1. Next, as shown in FIG. 3B, the polyimide film 3 is applied to the entire surface of the substrate 1 by a spin coating method, and low temperature drying is performed in an oven. In this state, the polyimide film 3 has a film thickness of 20 μm to 30 μm and is not imidized yet. The low temperature drying is performed by baking at a temperature of 70 ° C. to 80 ° C. for 40 minutes to 60 minutes.

【0013】次に、同図(c)に示すようにポリイミド
膜3を300℃〜400℃でキュアしイミド化する。続
いて、同図(d)に示すように、ポリイミド膜3の表面
の全面にレジスト膜4をスピンコート法によって塗布し
てオーブンで低温乾燥する。このときのレジスト膜の厚
さは8μm〜12μmであり、低温乾燥温度80℃〜9
0℃で60分〜70分のベーキングを行う。
Next, as shown in FIG. 3C, the polyimide film 3 is cured at 300 ° C. to 400 ° C. for imidization. Subsequently, as shown in FIG. 3D, the resist film 4 is applied on the entire surface of the polyimide film 3 by a spin coating method, and is dried at a low temperature in an oven. The thickness of the resist film at this time is 8 μm to 12 μm, and the low temperature drying temperature is 80 ° C. to 9 μm.
Bake for 60 to 70 minutes at 0 ° C.

【0014】次いで、同図(e)に示すように、レジス
ト膜4表面の所望の部分のみにエキシマレーザ光Eが照
射されるように一部を遮蔽したマスク5を通してエキシ
マレーザ光Eをスキャンさせ、レジスト膜4を除去し、
配線パターン用のパターン加工を行う。この工程でのエ
キシマレーザの条件は、波長248nm、エネルギー密
度0.79(J/cm2 )、ショト数35〜45であ
る。
Then, as shown in FIG. 2E, the excimer laser light E is scanned through a mask 5 which is partially shielded so that only a desired portion of the surface of the resist film 4 is irradiated with the excimer laser light E. , The resist film 4 is removed,
Performs pattern processing for wiring patterns. The conditions of the excimer laser in this step are a wavelength of 248 nm, an energy density of 0.79 (J / cm 2 ), and a Shot number of 35 to 45.

【0015】次に、同図(f)に示すように、レジスト
膜4が除去された部分のビィアホール形成部のポリイミ
ド膜3にもマスク5を介してエキシマレーザ光Eをスキ
ャンさせ、ポリイミド膜3を除去してビィアホール6を
形成する。この工程でのエキシマレーザの条件は波長2
48μm、エネルギー密度0.79(J/cm2 )、シ
ョット数75〜100であり、この条件でパターンおよ
びビィアホールを形成することにより、レジストの抜け
残り、および絶縁のビィアホールの抜け残りのない正テ
ーパ形のビィアホールを形成することができる。
Next, as shown in FIG. 1F, the polyimide film 3 in the via hole forming portion where the resist film 4 has been removed is also scanned with the excimer laser light E through the mask 5 so that the polyimide film 3 is removed. Are removed to form a via hole 6. The condition of the excimer laser in this process is wavelength 2
48 μm, energy density 0.79 (J / cm 2 ) and number of shots 75 to 100. By forming a pattern and a via hole under these conditions, a positive taper without residual resist and insulating via hole is formed. Shaped via holes can be formed.

【0016】続いて、同図(g)に示すように、基板1
上の全面にわたってスパッタリングなどにより、Cr、
Pd、CuまたはTiなどの金属薄膜7を形成する。さ
らに、同図(h)に示すように、レジスト膜4上の金属
薄膜7にエキシマレーザ光Eが照射されるように所定の
部分を遮蔽したマスク5を介してエキシマレーザ光Eを
スキャンさせ金属薄膜7を除去する。この工程でのエキ
シマレーザの条件は波長248nm、エネルギー密度
0.79(J/cm2 )、ショット数5〜10である。
このような条件で金属薄膜をエッチングすることにより
エッチング残りを少なくすることができる。
Subsequently, as shown in FIG.
Cr, etc.
A metal thin film 7 such as Pd, Cu or Ti is formed. Further, as shown in FIG. 1H, the metal thin film 7 on the resist film 4 is scanned with the excimer laser light E through a mask 5 that shields a predetermined portion so that the metal thin film 7 is irradiated with the excimer laser light E. The thin film 7 is removed. The conditions of the excimer laser in this step are a wavelength of 248 nm, an energy density of 0.79 (J / cm 2 ) and a shot number of 5 to 10.
The etching residue can be reduced by etching the metal thin film under such conditions.

【0017】次に、同図(i)に示すように、金属薄膜
7上に電解メッキ8を行う。この工程までのレジスト
膜、ポリイミド膜、金属薄膜に対するエキシマレーザ光
によるエッチング効果により、接続性の優れた配線パタ
ーンを形成することができる。メッキ膜厚は8〜12μ
m程度に形成される。
Next, as shown in FIG. 1I, electrolytic plating 8 is performed on the metal thin film 7. Due to the etching effect of the excimer laser light on the resist film, the polyimide film, and the metal thin film up to this step, a wiring pattern having excellent connectivity can be formed. Plating film thickness is 8-12μ
It is formed to about m.

【0018】最後に、同図(j)に示すように、レジス
ト膜4を除去する。この工程でのエキシマレーザ条件は
同図(e)の工程で示した条件と同等の波長248n
m、エネルギー密度0.79(J/cm2 )、ショット
数35〜45である。また、従来のMEKなどのウェッ
トエッチングによる剥離残りもエキシマレーザ光でレジ
スト膜が除去されるためになくすことができ、このよう
な工程を繰り返し積層して多層配線基板を形成する。
Finally, the resist film 4 is removed as shown in FIG. The excimer laser conditions in this step are the same as those shown in the step (e) of FIG.
m, energy density 0.79 (J / cm 2 ), and the number of shots 35 to 45. In addition, peeling residue due to conventional wet etching such as MEK can be eliminated because the resist film is removed by the excimer laser light, and such a process is repeatedly laminated to form a multilayer wiring board.

【0019】[0019]

【発明の効果】以上説明したように本発明によれば、配
線パターン上にポリイミド膜とレジスト膜を形成した後
にレジスト膜にエキシマレーザ光を照射させて配線パタ
ーン用の加工を行い、さらに、ポリイミド膜にもエキシ
マレーザ光を照射させてビィアホールを形成することに
より、レジストの抜け残り、絶縁部のビィアホールから
の抜け残り、および絶縁の逆テーパ形のビィアホールに
よる断線をなくすことができ、接続性の優れたパターン
およびビィアホールを形成することができる効果があ
る。
As described above, according to the present invention, after forming a polyimide film and a resist film on a wiring pattern, the resist film is irradiated with excimer laser light to perform processing for the wiring pattern. By irradiating the film with an excimer laser beam to form a via hole, it is possible to eliminate the residual resist, the residual via part in the insulating part, and the disconnection due to the reverse tapered via hole for insulation. There is an effect that an excellent pattern and a via hole can be formed.

【0020】従って、次工程の導体層形成工程では、上
下の導体層間のビィアホールの接続性を向上させること
ができ、パターンオープンの発生を防止することがで
き、また、スパッタ膜もエキシマレーザ光でエッチング
して除去するため、エッチング残りをなくしパターンシ
ョートを防止することができ、さらに、工程数を少なく
することができる効果がある。
Therefore, in the subsequent conductor layer forming step, the connectivity of the via holes between the upper and lower conductor layers can be improved, the pattern opening can be prevented, and the sputtered film can be exposed by the excimer laser light. Since it is removed by etching, there is an effect that a pattern short circuit can be prevented by eliminating the etching residue and the number of steps can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例における製造工程の一例を示す断
面図。
FIG. 1 is a sectional view showing an example of a manufacturing process in an embodiment of the present invention.

【図2】従来例における製造工程の一例を示す断面図。FIG. 2 is a sectional view showing an example of a manufacturing process in a conventional example.

【符号の説明】 1 基板 2 配線パターン 3 ポリイミド膜 4 レジスト膜 4′ レジスト残り 5 マスク 6 ビィアホール 7 金属薄膜 8 メッキ 8′ メッキされない箇所 9 感光性ポリイミド膜 10 ガラスマスク[Explanation of Codes] 1 substrate 2 wiring pattern 3 polyimide film 4 resist film 4'resist remaining 5 mask 6 via hole 7 metal thin film 8 plating 8'non-plated area 9 photosensitive polyimide film 10 glass mask

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成4年11月4日[Submission date] November 4, 1992

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例における製造工程の一例を示す断
面図。
FIG. 1 is a sectional view showing an example of a manufacturing process in an embodiment of the present invention.

【図2】本発明実施例における製造工程の一例を示す断
面図。
FIG. 2 is a sectional view showing an example of a manufacturing process in an embodiment of the present invention.

【図3】従来例における製造工程の一例を示す断面図。FIG. 3 is a sectional view showing an example of a manufacturing process in a conventional example.

【図4】従来例における製造工程の一例を示す断面図。FIG. 4 is a sectional view showing an example of a manufacturing process in a conventional example.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図2】 [Fig. 2]

【図4】 [Figure 4]

【図1】 [Figure 1]

【図3】 [Figure 3]

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ポリイミドと金属配線パターンを形成す
る多層配線基板の製造方法において、 基板上に金属配線パターンを形成する第一の工程と、 前記配線パターン上に前記基板の全面にわたってポリイ
ミド膜を形成して低温乾燥する第二の工程と、 前記ポリイミド膜をキュアしてイミド化する第三の工程
と、 前記ポリイミド膜上に前記基板の全面にわたってレジス
ト膜を形成して低温乾燥する第四の工程と、 前記レジスト膜に所定の部分をマスクにより遮蔽して除
去し配線パターン用の加工をする第五の工程と、 前記レジスト膜が除去された部分のビィアホール形成部
のポリイミド膜を除去してビィアホールを形成する第六
の工程と、 前記基板上の全面にわたって金属薄膜を形成する第七の
工程と、 前記レジスト膜上の金属薄膜を除去する第八の工程と、 前記ビィアホール部の金属薄膜上にメッキ層を形成する
第九の工程と、 前記レジスト膜を除去する第十の工程とにより製造する
ことを特徴とする多層配線基板の製造方法。
1. A method of manufacturing a multi-layer wiring board for forming a polyimide and a metal wiring pattern, comprising: forming a metal wiring pattern on a substrate; and forming a polyimide film on the wiring pattern over the entire surface of the substrate. And a low-temperature drying second step, a third step of curing and imidizing the polyimide film, a fourth step of forming a resist film on the polyimide film over the entire surface of the substrate and low-temperature drying A fifth step of removing a predetermined portion of the resist film by masking and removing the resist film to process a wiring pattern; and removing the polyimide film in the via hole forming portion of the resist film removed portion to form a via hole. And a seventh step of forming a metal thin film on the entire surface of the substrate, and removing the metal thin film on the resist film. A multi-layer wiring board, which is manufactured by an eighth step, a ninth step of forming a plating layer on the metal thin film in the via hole portion, and a tenth step of removing the resist film. Method.
【請求項2】 前記ポリイミド膜の形成はスピンコート
法により行う請求項1記載の多層配線基板の製造方法。
2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the polyimide film is formed by a spin coating method.
【請求項3】 前記レジスト膜、前記ポリイミド膜、お
よび前記レジスト膜上の金属薄膜の除去はエキシマレー
ザ光の照射によって行う請求項1記載の多層配線基板の
製造方法。
3. The method for manufacturing a multilayer wiring board according to claim 1, wherein the resist film, the polyimide film, and the metal thin film on the resist film are removed by irradiation with excimer laser light.
JP24797591A 1991-09-26 1991-09-26 Manufacture of multilayered wiring board Pending JPH05152750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24797591A JPH05152750A (en) 1991-09-26 1991-09-26 Manufacture of multilayered wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24797591A JPH05152750A (en) 1991-09-26 1991-09-26 Manufacture of multilayered wiring board

Publications (1)

Publication Number Publication Date
JPH05152750A true JPH05152750A (en) 1993-06-18

Family

ID=17171337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24797591A Pending JPH05152750A (en) 1991-09-26 1991-09-26 Manufacture of multilayered wiring board

Country Status (1)

Country Link
JP (1) JPH05152750A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5746868A (en) * 1994-07-21 1998-05-05 Fujitsu Limited Method of manufacturing multilayer circuit substrate
EP1667502A3 (en) * 1997-02-28 2007-07-25 Ibiden Co., Ltd. Printed wiring board and method of manufacturing the same
JP2007311642A (en) * 2006-05-19 2007-11-29 Sharp Corp Method of manufacturing multilayer printed wiring board
US7594320B2 (en) 1997-01-10 2009-09-29 Ibiden Co., Ltd. Method of manufacturing printed wiring board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5746868A (en) * 1994-07-21 1998-05-05 Fujitsu Limited Method of manufacturing multilayer circuit substrate
US5976393A (en) * 1994-07-21 1999-11-02 Fujitsu Limited Method of manufacturing multilayer circuit substrate
US7594320B2 (en) 1997-01-10 2009-09-29 Ibiden Co., Ltd. Method of manufacturing printed wiring board
US7765692B2 (en) 1997-01-10 2010-08-03 Ibiden Co., Ltd. Method of manufacturing printed wiring board
EP1667502A3 (en) * 1997-02-28 2007-07-25 Ibiden Co., Ltd. Printed wiring board and method of manufacturing the same
JP2007311642A (en) * 2006-05-19 2007-11-29 Sharp Corp Method of manufacturing multilayer printed wiring board

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