JPS60154625A - Formation of through-hole in multilayer insulation film - Google Patents
Formation of through-hole in multilayer insulation filmInfo
- Publication number
- JPS60154625A JPS60154625A JP1005484A JP1005484A JPS60154625A JP S60154625 A JPS60154625 A JP S60154625A JP 1005484 A JP1005484 A JP 1005484A JP 1005484 A JP1005484 A JP 1005484A JP S60154625 A JPS60154625 A JP S60154625A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- forming
- insulation film
- taper angle
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009413 insulation Methods 0.000 title abstract 4
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 238000000034 method Methods 0.000 claims description 22
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分封〕
本発明は多層配線の感光性絶縁膜スルホールの形成方法
に係り、特にスルホール形状の傾きを制御し、上部配線
膜の接続に好適なスルホール形成方法に関する。[Detailed Description of the Invention] [Uses of the Invention] The present invention relates to a method for forming through-holes in a photosensitive insulating film for multilayer wiring, and in particular, a through-hole forming method that controls the inclination of the through-hole shape and is suitable for connecting an upper wiring film. Regarding.
従来のスルホール形成方法は絶縁膜を形成後ホトエッチ
法で形成する。この際ゴミ等によるピンホールが問題と
なる場合、第１図のごとく絶縁膜の形成を２層以上の重
ね構造１と２にしたあと、異なるマスクを用いて２層以
上６，４のレジストを形成し、レジストのビンポールヲ
減少させた抜エッチする。この場合マスクは加工精度を
向上させるためスルホール径の小さい１１に１序に重ね
ていた。この方法は、作湊工数が多いという欠点かあっ
た。The conventional method for forming through holes is to form an insulating film and then use a photo-etching method. At this time, if pinholes due to dust etc. become a problem, after forming the insulating film in a stacked structure 1 and 2 of two or more layers as shown in Figure 1, apply resists 6 and 4 of two or more layers using different masks. Form and etch to reduce the number of resist holes. In this case, in order to improve processing accuracy, the masks were stacked on top of the through hole 11 having the smaller diameter. This method had the disadvantage of requiring a large number of man-hours.
また、感光剤であるレジストはエッチ後除去するためテ
ーパ角制御よりも寸法精度が要求され、スルホールのデ
ーパ角はレジストではｉｔ’ｌｌ イＩｌ′ｌＩできず
、エッチ方法（エッチ孜、エッチ治具クリ）で制御する
が、一般的には等方エッチであるためテーパ角１１ｉ１
１ （ｔｌは不０工能であり、４５°となる。In addition, since resist, which is a photosensitive agent, is removed after etching, dimensional accuracy is required rather than taper angle control. Generally, the taper angle is 11i1 because it is an isotropic etch.
1 (tl is a non-zero power and is 45°.
感光性絶縁膜形成は感光材をそのまま絶縁膜として利用
するためテーパ角制御法が従来と異なり感光材のテーパ
を制御する必要がｋ）る。In the formation of a photosensitive insulating film, since the photosensitive material is used as it is as an insulating film, the taper angle control method is different from the conventional method, and it is necessary to control the taper of the photosensitive material.
本発明の目的は感光性絶縁材料を用いることにより作業
工数を減らすと共にスルホール形状を、最適化すること
により１ｇ順性のある多ノ１４配線技術を提供すること
にある。An object of the present invention is to reduce the number of work steps by using a photosensitive insulating material, and to provide a multi-hole 14 wiring technology with 1g conformability by optimizing the through-hole shape.
ピンホールの少ない絶縁膜を形成する場合、多層膜構造
が用いられる。感光性絶縁膜で直接多層構造のスルホー
ルを形成する場合、レジストと比較して、膜厚が厚くな
り、光の透過が少なくなるため、スルホールのテーパ角
が太キ＜なりやすい。このため最小寸法形成時マスクと
感光性絶縁膜の密着性を悪くし、光の乱れを多くし、最
適なテーパ角を有するスルホールを提供することにある
。When forming an insulating film with few pinholes, a multilayer film structure is used. When directly forming through holes in a multilayer structure using a photosensitive insulating film, the film thickness becomes thicker and less light passes through the film compared to a resist, so the taper angle of the through holes tends to become thicker. For this reason, the objective is to provide a through hole having an optimal taper angle by reducing the adhesion between the mask and the photosensitive insulating film during formation of the minimum dimension and increasing light disturbance.
以下不発明の一実施例を第２図により示す。 An embodiment of the invention will be shown below with reference to FIG.
感光性材料を用い、ピンホールの少ない多層構造のスル
ホールを形成する場合、方式（１）と方式（２）が考え
られる。すなわち、方式（１）はスルホール径の小さい
スルホール５を先に形成後、径の大キいスルホール６を
形成する場合であり、方式（２）は径の大きいスルホー
ル６を形成後、径の小さいスルホール５を形成する方法
である。方式（１）、方式（２）によるちがいはテーバ
角度θが異なることである。すなわち方式（１）の方か
θが大きいことである。角度θは多層配線の従続を確保
するために亀裂な量でありθは４５°〜６０°がよいす
なわち、第３図に示すごとくスルポール形成後金属の魚
屑７等に上部配線が形成されるが、θが太きいとスルホ
ール胸部で上部配線膜厚が薄（なり、極端な場合断線と
なり信頼性不良をともなう。このため、スルホール部の
テーパ角を制御する心安があり、通常の蒸漸法であれば
角度６０°以１下が良いとされている。When forming through-holes in a multilayer structure with few pinholes using a photosensitive material, methods (1) and (2) can be considered. That is, method (1) is a case in which through holes 5 with a small diameter are formed first, and then a through hole 6 with a large diameter is formed, and method (2) is a case where a through hole 6 with a large diameter is formed and then a through hole with a small diameter is formed. This is a method for forming through holes 5. The difference between method (1) and method (2) is that the Taber angle θ is different. In other words, θ is larger in method (1). The angle θ is a crack amount to ensure the continuity of the multilayer wiring, and θ is preferably 45° to 60°. That is, as shown in FIG. However, if θ is large, the upper wiring film thickness at the through-hole chest will be thin (and in extreme cases, it will break and lead to poor reliability. Therefore, it is safe to control the taper angle of the through-hole part, and the normal evaporation temperature It is said that an angle of 60° or less is good if the angle is 1 or less.
本発明の特性は方式（２）を採用することで；ｌｙ）る
。The characteristics of the present invention are obtained by adopting method (2).
すなわち、方式（１）と方式（２）によりイ４ｔられた
テーバ角度の一例を示す。方式（２）は方式（１）はテ
ーパ角が小さく、−安来仕様である６０°以下となり、
方式（２）は多層配線に適するテーパ角を得ることかで
きる。That is, an example of the Taber angle obtained by method (1) and method (2) is shown. Method (2) has a smaller taper angle than method (1), which is less than 60°, which is the Yasugi specification.
Method (2) makes it possible to obtain a taper angle suitable for multilayer wiring.
方式（２）の方がテーパ角が小さくなる理由は上層絶縁
膜のパータン化する際、スルホールを下層スルホール内
に作成するため、下層スルポール内ではマスクと上層感
光性絶縁物が密着せず、露光光線が乱れ、露光部と非露
光部が屯なり、結果として、テーバ角度が小さくなるた
めである。The reason why the taper angle is smaller in method (2) is that when patterning the upper layer insulating film, through holes are created in the lower layer through holes, so the mask and the upper layer photosensitive insulator do not come into close contact in the lower layer through holes, and exposure This is because the light rays are disturbed and the exposed and non-exposed areas are tilted, resulting in a small Taber angle.
本発明によれば感光性絶縁膜を用い、重ね構造絶縁膜の
スルホールのテーパ角を制御することができ、工数を低
減すると共に多層配線の信頼性を向上できる効果がある
。According to the present invention, it is possible to control the taper angle of through-holes in a layered structure insulating film using a photosensitive insulating film, thereby reducing the number of man-hours and improving the reliability of multilayer wiring.
第１図は従来法のスルホール断面図、
第２図は感光性材料を用いたスルホール断面図、
第６図は多層配線の断面図、
第４図は方式（１）、方式（２）によるテーパ角の例を
示す１が図でＡりる。
１．２・・・絶縁膜、 ５．６・・・感光性拐料、代理
人弁理士 高 欄 明 夫
オ ｔｒｗ
／ｆ２図
（α）（１））
才３図
才４図
露危量（ぢ／７）Figure 1 is a cross-sectional view of a through hole using a conventional method. Figure 2 is a cross-sectional view of a through hole using a photosensitive material. Figure 6 is a cross-sectional view of a multilayer wiring. Figure 4 is a cross-sectional view of a through hole using method (1) and method (2). 1 showing an example of a corner is A in the figure. 1.2...Insulating film, 5.6...Photosensitive material, Patent attorney Taka Ran Akio trw/f2 figure (α) (1)) Age 3 figure Age 4 figure exposure risk (ぢ/7)
Claims (1)
層絶縁膜のスルポール形成１麦、上層絶縁膜を形成し、
下層スルホール内に上層スルホールを形成して、スルホ
ールのテーパー角を制御することを特徴とする多層絶縁
族のスルホール形成方法。1. In forming through holes in a multilayer photosensitive insulating film, forming through holes in a lower insulating film 1. Forming an upper insulating film,
A method for forming throughholes in a multilayer insulating group, which comprises forming upper layer throughholes within lower layer throughholes and controlling the taper angle of the throughholes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1005484A JPS60154625A (en) | 1984-01-25 | 1984-01-25 | Formation of through-hole in multilayer insulation film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1005484A JPS60154625A (en) | 1984-01-25 | 1984-01-25 | Formation of through-hole in multilayer insulation film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60154625A true JPS60154625A (en) | 1985-08-14 |
Family
ID=11739674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1005484A Pending JPS60154625A (en) | 1984-01-25 | 1984-01-25 | Formation of through-hole in multilayer insulation film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154625A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62168964A (en) * | 1986-01-21 | 1987-07-25 | Nippon Denso Co Ltd | Starter |
| JPH0191439A (en) * | 1987-06-18 | 1989-04-11 | Seiko Instr & Electron Ltd | Semiconductor device |
-
1984
- 1984-01-25 JP JP1005484A patent/JPS60154625A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62168964A (en) * | 1986-01-21 | 1987-07-25 | Nippon Denso Co Ltd | Starter |
| JPH0191439A (en) * | 1987-06-18 | 1989-04-11 | Seiko Instr & Electron Ltd | Semiconductor device |
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