JPS61245534A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61245534A JPS61245534A JP8637885A JP8637885A JPS61245534A JP S61245534 A JPS61245534 A JP S61245534A JP 8637885 A JP8637885 A JP 8637885A JP 8637885 A JP8637885 A JP 8637885A JP S61245534 A JPS61245534 A JP S61245534A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- holes
- substrate
- mask
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229920001721 polyimide Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 239000009719 polyimide resin Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 239000004642 Polyimide Substances 0.000 abstract description 4
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 description 1
- 150000004984 aromatic diamines Chemical class 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 125000006158 tetracarboxylic acid group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置の製造法に関し、特にポリイミド系
樹脂膜の微細加工技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for microfabrication of polyimide resin films.
ICJPLSI等の半導体装置において、1チツプあた
りの素子数が万単位で増大するに伴い、素子の電極間を
接続するアルミニウム等の配線は2層、3層と多層構造
化する傾向にある。In semiconductor devices such as ICJP LSI, as the number of elements per chip increases by the order of ten thousand, wiring made of aluminum or the like that connects electrodes of elements tends to have a multilayer structure of two or three layers.
この多層配線構造では上下の配線間の層間絶縁膜として
、従来はシリコン酸化物系の無機絶縁膜が使われていた
が、これで1μm以上の厚膜を形成した場合に、熱処理
の際に歪によってクラック等を生じやすく、又、下地の
基板に段差がある場合に多層に重ねられた絶縁膜の表面
で段差がさらに甚しくなり、その上に設けられる配線に
断線不良を生じるなどの問題があった。In this multilayer wiring structure, a silicon oxide-based inorganic insulating film has traditionally been used as an interlayer insulating film between upper and lower wirings, but when a film with a thickness of 1 μm or more is formed with this film, it can be strained during heat treatment. In addition, if there is a step on the underlying substrate, the step becomes even more severe on the surface of the multi-layered insulating film, causing problems such as disconnection in the wiring provided above. there were.
このような無機の絶縁膜に代って、比較的低温処理が可
能でしかも表面平坦性を確保できる有機絶縁膜が使われ
るようになった。特に本発明者によって開発された高耐
熱性のポリイミド系高分子樹脂を眉間絶縁膜を用いた配
線構造が採用されている。(工業調査会電子材料198
0年7月p30参照)
このボリイ叱ド系樹脂は、たとえば、芳香族ジアミンと
芳香族テトラカルボン酸二無水物とを反応して得られる
重合物からなるポリイミド系樹脂のプレポリマー溶液を
基板表面にスピンナ塗布した後、溶媒成分を蒸着させ、
200〜300℃熱処理して重合硬化させるものである
。Instead of such inorganic insulating films, organic insulating films that can be processed at relatively low temperatures and can ensure surface flatness have come to be used. In particular, a wiring structure using a highly heat-resistant polyimide polymer resin developed by the present inventor as a glabellar insulating film is employed. (Industrial Research Council Electronic Materials 198
(See page 30, July 2007) This polyamide resin is produced by applying a prepolymer solution of a polyimide resin, which is a polymer obtained by reacting an aromatic diamine and an aromatic tetracarboxylic dianhydride, to the surface of a substrate. After coating with a spinner, the solvent component is evaporated,
It is polymerized and hardened by heat treatment at 200 to 300°C.
このようなポリイミド系樹脂を使った層間絶縁膜におい
て、上下の八β(アルミニウム)配線の接続のためにス
ルーホール(透孔)をあける場合に、下地の基板に段差
があるとき下記のような問題がある。When making a through hole to connect the upper and lower 8β (aluminum) wiring in an interlayer insulating film using polyimide resin, if there is a step in the underlying substrate, the following will occur. There's a problem.
第7図において、1は下地基板、2は段差部で、たとえ
ば拡散マスクとして使用した酸化膜(Sins)や、下
層のへβ配線等によってできたものである。In FIG. 7, reference numeral 1 indicates a base substrate, and reference numeral 2 indicates a stepped portion, which is formed by, for example, an oxide film (Sins) used as a diffusion mask, or β wiring in the lower layer.
3はポリイミド系樹脂等からなる被膜で、下地の段差に
かかわらず表面が同一平坦面となるように充分に厚く形
成されている。Reference numeral 3 denotes a coating made of polyimide resin or the like, which is formed sufficiently thick so that the surface becomes the same flat surface regardless of the level difference in the base.
4及び5はスルーホール、6はスルーホールをあけるた
めに用いたレジスト・マスクである。4 and 5 are through holes, and 6 is a resist mask used to open the through holes.
上記レジストマスク6の各スルーホールに対応する窓孔
は同じ径at”atであっても、これを通してポリイミ
ド等方性エッチした場合、下地の深さが異なる部分では
ポリイミド膜の厚さが異なるために、穴の太ぎさは、底
の方です、>b、のように異なってくる。このため、ス
ルーホール部における配線の抵抗が変ってきて、ポリイ
ミド膜の厚い部分では抵抗値が高くばらついて好ましく
ない。特にスルーホール寸法が微細化するほど問題があ
る。Even if the window holes corresponding to the through holes in the resist mask 6 have the same diameter at"at, if the polyimide is isotropically etched through them, the thickness of the polyimide film will be different in the areas where the underlying depth is different. In addition, the thickness of the hole differs at the bottom, >b.For this reason, the resistance of the wiring in the through-hole section changes, and the resistance value varies widely in the thick part of the polyimide film. This is not preferable, especially as the through-hole size becomes finer.
本発明は上記した問題を克服するためになされたもので
あり、その目的は、ポリイミド樹脂を用いた層間膜のス
ルーホールの寸法のばらつきをなくし、微細加工を可能
としたスルーホールエッチ技術の提供にある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to provide a through-hole etching technique that eliminates the variation in the dimensions of through-holes in interlayer films using polyimide resin and enables microfabrication. It is in.
本願におい℃開示される発明のうち代表的なものの概要
を簡単に説明すれば下記の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、段差を有する基板下地上で、ポリイミド系樹
脂膜にスルーホールをあけるにあたって、スルーホール
のための第1回のエツチングの後、上記段差をエツチン
グにより形成するために用いたマスクを利用して、段差
による下地の高い部分のスルーホールをレジストでふさ
ぎ、この状態で下地の低い部分のスルーホールを追加エ
ッチすることにより下地の段差にかかわることなく孔径
の等しいスルーホールを得てスルーホールの微細加工を
可能とし、スルーホール抵抗のばらつきをなくすもので
ある。That is, when making a through hole in a polyimide resin film on a substrate base having a step, after the first etching for the through hole, the mask used to form the step by etching is used. By blocking the through holes in the high part of the base due to the step with resist, and additionally etching the through holes in the low part of the base in this state, through holes with the same diameter are obtained without involving the step in the base, and the fineness of the through hole is This enables processing and eliminates variations in through-hole resistance.
第1図乃至第5図は本発明の一実施例を示すものであっ
て、段差を有する基板上で樹脂膜にスルーホールを形成
するプロセスの工程断面図である。FIGS. 1 to 5 show an embodiment of the present invention, and are cross-sectional views of a process for forming through holes in a resin film on a substrate having steps.
以下、各工程にそって説明する。Each step will be explained below.
(1) たとえばSi(シリコン)基板の表面に酸化
膜(Sift)等の形成された下地基板11を用意する
。この下地基板の表面部分をたとえば拡散用のマスクと
して形成するためのホトレジスト処理を行う。すなわち
、全面にホトレジスト材(ネガタイプ)12を塗布し、
この上に一部に不透過部分13を有するホトマスク14
を重ね℃透過部分15を通して露光を行なう。(第1図
)(2)上記レジスト材を現像することにより露光され
た部分を重合硬化させ、未篇光部分を選択的に溶解除去
してホトレジストマスクを得る。このホトレジストマス
クを使っ℃基板をエッチすることにより段差16をもつ
凹部17をほる。(第2図)(31全面にポリイミド樹
脂を塗布し、厚さ1.5〜2.0μm程度の絶縁被膜を
形成する。この被膜は、ポリイミド系樹脂のプレポリマ
ー溶液、又は中型合物溶液を基体表面にスピンナ塗布し
たのち、溶媒成分を蒸着させ、さらに200〜300℃
で熱処理して硬化させることにより表面が平坦面化した
状態のポリイミド系樹脂膜18が形成される。(1) For example, a base substrate 11 having an oxide film (Sift) formed on the surface of a Si (silicon) substrate is prepared. A photoresist process is performed to form the surface portion of this base substrate, for example, as a mask for diffusion. That is, a photoresist material (negative type) 12 is applied to the entire surface,
A photomask 14 having a partially opaque portion 13 thereon
are overlapped and exposed through the °C transparent portion 15. (FIG. 1) (2) The exposed portions are polymerized and hardened by developing the resist material, and the uncut portions are selectively dissolved and removed to obtain a photoresist mask. By etching the C substrate using this photoresist mask, a recess 17 having a step 16 is bored out. (Figure 2) (31) Apply polyimide resin to the entire surface to form an insulating film with a thickness of about 1.5 to 2.0 μm. This film is made by applying a prepolymer solution of polyimide resin or a medium-sized compound solution. After coating the substrate surface with a spinner, the solvent component is vapor-deposited and further heated at 200 to 300°C.
A polyimide resin film 18 with a flat surface is formed by heat treatment and curing.
(第3図)
(4) このあと全面にホトレジストを形成し、特定
、のスルーホールパターンのホトマスクを使用し、露光
・現像処理し、でき上ったマスク19を用いてポリイミ
ド系樹脂をヒドラジン液等でエツチングすることにより
、第1図に示すように、スルーホール20.21をあけ
る。このスルーホールは下地面の高い側では底部の径a
が大きく、下地面の低い側では底部の径すは小さいもの
となる。(Figure 3) (4) After this, photoresist is formed on the entire surface, exposed and developed using a photomask with a specific through-hole pattern, and using the completed mask 19, polyimide resin is coated with hydrazine solution. By etching, as shown in FIG. 1, through holes 20 and 21 are made. This through hole has a bottom diameter of a on the high side of the base surface.
is large, and the bottom diameter is small on the lower side of the base surface.
このようなスルーホールをあけた後、これらスルーホー
ルを埋めるようにホトレジスト22を塗布する。このホ
トレジストの上に前記工程(1)で用いたホトマスク1
4を重ね℃露光する。(第4図)(5)この後現像処理
すれば、ホトマスク14の透過部分15を通し℃露光さ
れた部分のホトレジスト22が残り、他の部分は除去さ
れて、下地面の低い側のスルーホール21が露出する。After opening such through holes, photoresist 22 is applied to fill these through holes. On this photoresist, the photomask 1 used in the step (1) is
Repeat step 4 and expose at ℃. (Fig. 4) (5) After this, if development is carried out, the photoresist 22 in the part exposed to °C through the transparent part 15 of the photomask 14 will remain, the other part will be removed, and the through hole on the lower side of the underlying surface will remain. 21 is exposed.
ここで再度、ヒドラジン液等によるポリイミド系樹脂の
エッチを行い、エツチング量をコントロールすることに
より、レジストで覆われた下地上側のスルーホール20
の底部の径aと同じ底部の径b′をもつ下地下側のスル
ーホール21を加工する。(第5図)
(61最後にホトレジスト22.マスク19を取り除く
ことにより段差によって下地面の高さが異なるにもかか
わらず、等しい底部の径(a=b’)をもつスルーホー
ル20.21を得る巳とができる。 。Here, the polyimide resin is etched again using a hydrazine solution, etc., and by controlling the amount of etching, the through holes 20 on the side of the base covered with the resist are etched.
A through-hole 21 on the lower underground side is machined having the same bottom diameter b' as the bottom diameter a. (Fig. 5) (61 Finally, by removing the photoresist 22. mask 19, a through hole 20.21 with the same bottom diameter (a = b') is created despite the difference in height of the underlying surface due to the step. You can get it.
第8図は本発明を半導体装置において具体化した実施例
を示す断面図である。FIG. 8 is a sectional view showing an embodiment of the present invention in a semiconductor device.
23はトランジスタ等の半導体素子の形成された半導体
(シリコン)基板、24は段差をもつ表面酸化膜である
。25.26は第1層のAμ配線(電極)である。27
はポリイミド系樹脂からなる層間膜である。28.29
はスルーホール、30.31は第2層のAJ配線である
。この場合、表面酸化膜240段差によ−p”Cスルー
ホール28゜29の深さが異なってくるが、深い側のス
ルーホール29の追加エッチにより、ホール底部の径は
両者等しくなっている。23 is a semiconductor (silicon) substrate on which semiconductor elements such as transistors are formed, and 24 is a surface oxide film having steps. 25 and 26 are Aμ wiring (electrodes) of the first layer. 27
is an interlayer film made of polyimide resin. 28.29
30.31 is a through hole, and 30.31 is an AJ wiring in the second layer. In this case, the depths of the -p''C through holes 28 and 29 differ due to the step difference in the surface oxide film 240, but the diameters of the bottoms of the holes are made equal by additional etching of the deeper through holes 29.
以上、実施例で説明した本発明によれば下記のような効
果が得られる。According to the present invention described above in the examples, the following effects can be obtained.
+11 下地段差のある基体上に形成したポリイミド
系樹脂等による絶縁膜によるスルーホールをあけた場合
、ポリイミド膜表面の平坦面化により、段差の上と下と
でポリイミド膜厚差ができ、そのため等方性エッチによ
ってスルーホールをあけた場合、スルーホールの寸法が
異なってくるが、段差の下側のスルーホールを追加エッ
チすることにより、上側のスルーホール径と合わせろこ
とができる。+11 When a through hole is made using an insulating film made of polyimide resin or the like formed on a substrate with a step difference, the flattening of the surface of the polyimide film creates a difference in the thickness of the polyimide film between the top and bottom of the step difference, which results in isotropy. When a through hole is formed by etching, the dimensions of the through hole will be different, but by additionally etching the through hole below the step, it can be made to match the diameter of the through hole above.
(21スルーホールの追加エッチの際、追加エッチしな
い方のスルーホールをふさぐために最初の段差加工に用
いたマスクをそのまま使用することは、特に新たなマス
クをつくることなく簡便にして精度よくレジストマスク
形式ができる。(When performing additional etching for the 21 through-holes, using the same mask used for the initial step processing to close the through-holes that are not additionally etched is a convenient and accurate way to create a resist pattern without creating a new mask.) Mask format is available.
(3) 上記111 、121により、スルーホール
寸法の微細化、及びスルーホール抵抗の低減化ができ、
ひいてはICチップの縮小化を実現できる。(3) With the above 111 and 121, it is possible to miniaturize the through hole dimensions and reduce the through hole resistance,
As a result, the size of the IC chip can be reduced.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな(、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). Not even.
たとえば、ポリイミド系樹脂のスルーホールエッチ、追
加エッチにヒドラジン等を用いるウェットエッチに代え
て、ドライエッチをそれに併用する場合においても、同
様の効果のもたら・されることが期待できる。For example, in place of wet etching using hydrazine or the like for through-hole etching of polyimide resin and additional etching, similar effects can be expected to be produced when dry etching is used in combination.
本発明は有機性樹脂を層間絶縁膜として使用するリニア
ICの多層配線構造全般に適用できる。The present invention can be applied to all multilayer wiring structures of linear ICs that use organic resin as an interlayer insulating film.
第1図乃至第6図は本発明の一実施例を示す半導体装置
プロセスの工程断面図である。
第7図はこれまでの下地段差上のポリイミド層における
スルーホールの形態を示す断面図である。
第8図は本発明の具体例を示す半導体装置の断面図であ
る。
11・・・基板、12・・・ホトレジスト材、13・・
・不透過部分、14・・・ホトマスク、15・・・透過
部、16・・・段差部、17・・・凹部、18・・・ポ
リイミド系樹脂、19・・・マスク、20,21・・・
スルーホール、22・・・ホトレジスト。
へ \1 to 6 are cross-sectional views of a semiconductor device process showing an embodiment of the present invention. FIG. 7 is a cross-sectional view showing the form of through holes in the polyimide layer on the base step. FIG. 8 is a sectional view of a semiconductor device showing a specific example of the present invention. 11... Substrate, 12... Photoresist material, 13...
- Opaque part, 14... Photomask, 15... Transparent part, 16... Step part, 17... Concave part, 18... Polyimide resin, 19... Mask, 20, 21...・
Through hole, 22...photoresist. fart \
Claims (1)
の上に有機樹脂塗布による表面平坦な被膜を形成し、こ
の被膜の一部をエッチして透孔をあけた後、上記段差エ
ッチに用いたマスクを用いて、段差による下地の高い部
分の被膜の透孔をレジスト膜で覆い、この状態で下地の
低い部分の透孔をエッチすることを特徴とする半導体装
置の製造法。 2、上記有機樹脂はポリイミド系樹脂である特許請求の
範囲第1項に記載の半導体装置の製造法。[Claims] 1. A part of the surface of the substrate is etched to form a height difference, a film with a flat surface is formed by applying an organic resin thereon, and a part of this film is etched to form a through hole. After opening, the mask used for the step etching is used to cover the through holes in the film in the high part of the base due to the step with a resist film, and in this state, the through holes in the low part of the base are etched. A method for manufacturing semiconductor devices. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the organic resin is a polyimide resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8637885A JPS61245534A (en) | 1985-04-24 | 1985-04-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8637885A JPS61245534A (en) | 1985-04-24 | 1985-04-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61245534A true JPS61245534A (en) | 1986-10-31 |
Family
ID=13885213
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8637885A Pending JPS61245534A (en) | 1985-04-24 | 1985-04-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61245534A (en) |
-
1985
- 1985-04-24 JP JP8637885A patent/JPS61245534A/en active Pending
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