JPS60103614A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60103614A JPS60103614A JP21098583A JP21098583A JPS60103614A JP S60103614 A JPS60103614 A JP S60103614A JP 21098583 A JP21098583 A JP 21098583A JP 21098583 A JP21098583 A JP 21098583A JP S60103614 A JPS60103614 A JP S60103614A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- layer
- resist layer
- layers
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 13
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000000576 coating method Methods 0.000 abstract description 7
- ZNQVEEAIQZEUHB-UHFFFAOYSA-N 2-ethoxyethanol Chemical group CCOCCO ZNQVEEAIQZEUHB-UHFFFAOYSA-N 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 14
- 238000007796 conventional method Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 5
- 239000004926 polymethyl methacrylate Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、半導体装置の製造方法に関し、特に、サブ
ミクロン級の線巾のＶＬＳ Ｉの製造に好適な半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for manufacturing a VLSI with a submicron line width.
［発明の技術的背景］
シリコン半導体デバイスの製造技術の進歩により、線巾
が１〜２μｍのＶＬＳ Ｉに関する量産技術がほぼ確立
されており、更に線巾がサブミクロン級のＶＬＳＩの量
産技術の開発が進められている。[Technical Background of the Invention] Due to advances in manufacturing technology for silicon semiconductor devices, mass production technology for VLSI with a line width of 1 to 2 μm has almost been established, and further development of mass production technology for VLSI with a line width of submicron class. is in progress.
線幅がサブミクロン級の高密度ＬＳＩの量産技術の開発
のためには、リソグラフィ、エツチング、膜形成技術、
金属配線技術、素子間分離技術等の各種の技術分野で解
決し工ゆかねばならない問題点が多い。 リソグラフィ
技術及び配線形成技術に関しては、多層レジスト構造を
利用するマスクトランスファ技術を採用することにより
、パターン転写工程における解像度の向上と同時にリフ
トオフ配線の実現を図る試みが行われている。In order to develop mass production technology for high-density LSI with submicron line width, lithography, etching, film formation technology,
There are many problems that must be solved in various technical fields such as metal wiring technology and element isolation technology. Regarding lithography technology and wiring formation technology, attempts are being made to improve resolution in the pattern transfer process and at the same time realize lift-off wiring by employing mask transfer technology that utilizes a multilayer resist structure.
従来、前記のごとき、リソグラフィ及び配線技術に採用
されたマスクトランスファ技術には、以下のごとぎ二つ
の方法があった。Conventionally, there have been two methods of mask transfer technology employed in lithography and wiring technology as described above, as described below.
第一の方法は、半導体基板の表面にポリメタクリル酸メ
チル（ＰＭＭＡ）から成る遠紫外線用ポジ型レジストを
厚く塗布して、これを第一（下部）レジス１へ層とし、
更に該第−レジス］・層の上に薄く近紫外線用ポジ型レ
ジスト（例えばＳ ｈｉｐｌｅｙ社Ａ Ｚ １ ’３５
０ Ｊ ）を塗布してこれを第二（上部）レジスト層と
した後、まず第ニレジスト層を近紫外線で露光し、かつ
現像して該第ニレジス１一層からなるレジストパターン
を作り、更に該レジストパターンをマスクとして第一レ
ジスト層を遠紫外線で露光する、という方法である。The first method is to apply a thick layer of deep ultraviolet ray positive resist made of polymethyl methacrylate (PMMA) on the surface of a semiconductor substrate, and apply this as a layer to the first (lower) resist 1.
Furthermore, a thin near-ultraviolet positive type resist (for example, Shipley's AZ 1 '35) is applied on top of the third resist layer.
0 J) to form a second (upper) resist layer, first, the second resist layer was exposed to near ultraviolet light and developed to form a resist pattern consisting of one layer of the second resist 1, and then the resist layer was further exposed to near ultraviolet light and developed. This method involves exposing the first resist layer to deep ultraviolet light using the pattern as a mask.
第１図（ａ ）ないし第１図（ｆ ）はこの第一の方法
を工程順に示したものであり、同図において、１は半導
体基板、２は第一レジスト層、３は第二レジスト層、４
は密着露光型紫外線露光装置のマスク、５の矢印で表示
されているのは近紫外線、同じく６の矢印で示されてい
るのは遠紫外線である。Figures 1(a) to 1(f) show the first method in the order of steps. In the figures, 1 is a semiconductor substrate, 2 is a first resist layer, and 3 is a second resist layer. , 4
is a mask of a contact exposure type ultraviolet exposure device, arrow 5 indicates near ultraviolet rays, and arrow 6 indicates far ultraviolet rays.
一方、第二の方法は以下のような工程（第２図（ａ）な
いし第２図（ｆ））で構成される。 すなわち、第２図
（ａ ）に示されているように、まず、半導体基板１上
に第一レシスト層２（例えばＰＭＭＡを主成分とするポ
ジ型レジスト）を形成した後、更に第一レジスト層２の
上に５ｉ０２などの無機質もしくは金属などの無機膜７
を第２図（ｂ）のように形成し、更に無機膜７の上に第
ニレジスト層（例えばＰＭＭＡを主成分とするポジ型レ
ジスト）３を形成する。 次に第２図（０）に示すよう
に密着露光によって該第ニレジスト層３に遠紫外線を選
択的に露光し、かつ現像することにより第２図（ｄ ）
に示すように開口３ａを有したレジストパターンを形成
する。 そして、該レジストパターンをマスクとして第
２図（ｅ）及び（ｆ ）に示すように、該無機膜７と第
一レジスト層２に、それぞれエツチング及び遠紫外線６
で選択的露光現像を行うことにより第２図（ｆ）に示さ
れるように第一レジスト層２にリフトオフ配線に適した
不払がりの開口（もしくは溝＞２ａを形成する。On the other hand, the second method consists of the following steps (FIG. 2(a) to FIG. 2(f)). That is, as shown in FIG. 2(a), first, a first resist layer 2 (for example, a positive resist mainly composed of PMMA) is formed on a semiconductor substrate 1, and then a first resist layer 2 is formed on the semiconductor substrate 1. An inorganic film 7 made of inorganic material such as 5i02 or metal on top of 2
is formed as shown in FIG. 2(b), and then a second resist layer 3 (for example, a positive resist mainly composed of PMMA) 3 is formed on the inorganic film 7. Next, as shown in FIG. 2(0), the second resist layer 3 is selectively exposed to deep ultraviolet rays by contact exposure and developed.
A resist pattern having openings 3a is formed as shown in FIG. Then, using the resist pattern as a mask, as shown in FIGS. 2(e) and 2(f), the inorganic film 7 and the first resist layer 2 are etched and exposed to deep ultraviolet rays, respectively.
By performing selective exposure and development, as shown in FIG. 2(f), an unburned opening (or groove>2a) suitable for a lift-off wiring is formed in the first resist layer 2.
［青用技術の問題点］
前記のごとき公知のマスクトランスファ技術にはそれぞ
れ、以下のごとき問題点があった。[Problems with blue technology] Each of the known mask transfer technologies described above has the following problems.
第１図に示した第一の方法では、上層のレジメ１〜と下
層のレジストとが直接に接触するのでそれぞれのレジス
トに相溶性があると、該レジスト層の塗布形成時に塗布
むらが生じてレジスト層形成が不良になるという問題が
生じやすかった。 従って、従来は上層レジストと下層
レジストを同一にすることは側底できなかったが、より
微細なパターンの形成を可能とするためには上層レジス
トも遠紫外線用レジストにすることが望ましい。In the first method shown in FIG. 1, the upper layer Regimes 1 to 1 are in direct contact with the lower resist layer, so if the respective resists are compatible, uneven coating will occur during coating formation of the resist layer. The problem of poor resist layer formation was likely to occur. Therefore, conventionally it has not been possible to make the upper layer resist and the lower layer resist the same, but in order to enable the formation of finer patterns, it is desirable that the upper layer resist also be a deep ultraviolet resist.
第２図に示した第二の方法は第一の方法に存する前記問
題点を解決するために提案された方法であり、前記無機
膜７は上層レジストと下層レジストとの相溶性に基因す
る塗布むらの発生を防止するために設けられたものであ
る。 しかしながら、前記第二の方法においては、該無
機膜７を形成除去する工程が一般に複雑である上、無機
膜形成時間が長くかかり、また、高価な無機膜形成設備
も５−
必要になる等の欠点があった。The second method shown in FIG. 2 is a method proposed to solve the above-mentioned problems in the first method. This is provided to prevent unevenness from occurring. However, in the second method, the process of forming and removing the inorganic film 7 is generally complicated, takes a long time to form the inorganic film, and requires expensive inorganic film forming equipment. There were drawbacks.
［発明の目的］
この発明は、前記従来方法に存する欠点を除き、より微
細なパターニングを従来方法よりも短かい時間と短かい
工程とで行うことのできる、半導体装置の製造方法を提
供することを目的とする。[Object of the Invention] The present invention provides a method for manufacturing a semiconductor device, which eliminates the drawbacks of the conventional method and allows finer patterning to be performed in a shorter time and in shorter steps than the conventional method. With the goal.
また、この発明は、微細なリフトオフ配線に適する半導
体装置製造方法の提供を別の目的としている。Another object of the present invention is to provide a method for manufacturing a semiconductor device suitable for fine lift-off wiring.
［発明の概要］
この発明による方法は、半導体基板上に多層レジスト構
造を形成する過程において上層レジスト層と下層レジス
ト層との間に該両層に対して相溶性のない樹脂層を形成
させつつレジストの積層を行うことを特徴とするもので
あり、この発明の方法によれば、相溶性の点から、従来
方法よりも上下レジスト種類の選択について自由度を有
するとともに、はるかに短い時間及び低コストでレジス
ト層の形成を行うことができ′る。[Summary of the Invention] The method according to the present invention forms a resin layer between an upper resist layer and a lower resist layer, which is incompatible with both layers, in the process of forming a multilayer resist structure on a semiconductor substrate. The method of the present invention is characterized by laminating resists, and from the viewpoint of compatibility, it has more freedom in selecting the types of upper and lower resists than the conventional method, and it also takes much less time and costs less. The resist layer can be formed at low cost.
例えば、上下のレジストがＰＭＩＰＫ（ポリメ６−
ヂルイソプ［１ピルケ１−ン）を主成分とするものであ
れば、該樹脂層は例えば、エチルセロソルブを溶媒とす
るノボラック系樹脂で構成することができる。 このよ
うな上下レジストの組合せはザブミクロン級の微細リフ
トオフ用配線の高感度レジストの積層どして極めて好適
である。For example, if the upper and lower resists are mainly composed of PMIPK (polymer 6-dilysop[1-pirkene]), the resin layer can be composed of a novolak-based resin using ethyl cellosolve as a solvent, for example. . Such a combination of upper and lower resists is extremely suitable for laminating high-sensitivity resists for submicron-level fine lift-off wiring.
［発明の実施例］
第３図（ａ ）ないし第３図（Ｃ）を参照して本発明方
法の一実施例を説明する。[Embodiment of the Invention] An embodiment of the method of the present invention will be described with reference to FIGS. 3(a) to 3(C).
本発明の方法においては、まず第３図（ａ ）に示すよ
うに、半導体基板１の表面にＰＭ Ｉ ＰＫを主成分と
する遠紫外線用レジスト（東京応化社製０ＤＵＲ−１０
１４＞を塗布して第一レジスト層２１を形成した後、エ
チルセロソルブを溶媒とするノボラック系樹脂を例えば
０．０５〜０．０７μｍ程度の厚さに塗布して樹脂層８
を形成する。In the method of the present invention, first, as shown in FIG. 3(a), a deep ultraviolet resist (0DUR-10 manufactured by Tokyo Ohka Co., Ltd.
14> to form the first resist layer 21, a novolac resin using ethyl cellosolve as a solvent is applied to a thickness of, for example, about 0.05 to 0.07 μm to form the resin layer 8.
form.
更に、該樹脂層８の上に第一レジスト層２１と同一のレ
ジストをやや薄く塗布して第１１９２１層３１を第３図
（ｈ ）のように形成した後、密着露光型の遠紫外線露
光装置で露光すると（９は該露光装置のマスク）、遠紫
外線に対して上下のレジスト１１２１．３１が同時に感
光するので（樹脂層８は遠紫外線を透過さ−せる）、こ
れを現像すると第３図（Ｃ）のように上下のレジスト層
を貫通する開口１０（もしくは溝）が形成される。Furthermore, after applying a slightly thinner layer of the same resist as the first resist layer 21 on the resin layer 8 to form the 11921st layer 31 as shown in FIG. When exposed to light (9 is the mask of the exposure device), the upper and lower resists 1121.31 are simultaneously exposed to far ultraviolet rays (resin layer 8 transmits far ultraviolet rays), and when this is developed, the result shown in FIG. As shown in (C), an opening 10 (or groove) penetrating the upper and lower resist layers is formed.
第１１９２１層３１の形成時には、該第ニレジスト層と
相溶性のない樹脂層８が既に形成されているので、レジ
ストの塗布むらが起る恐れはなく、均一な塗布が可能と
なる。At the time of forming the 11921st layer 31, the resin layer 8 which is incompatible with the second resist layer has already been formed, so there is no risk of uneven coating of the resist, and uniform coating is possible.
また、第一レジス（一層と第ニレジスト層とは相溶性の
点で制約がないので、第ニレジスト層に高感度遠紫外線
レジストを採用することができ、その結果０．５μｍ級
のりソグラフィが可能となる。In addition, since there are no restrictions in terms of compatibility between the first resist layer and the second resist layer, a highly sensitive deep ultraviolet resist can be used for the second resist layer, and as a result, 0.5 μm class glue lithography is possible. Become.
そしてＰＭＩＰＫのようなポジ型の積層レジスト層を形
成することによって、リフトオフ法に適するリソグラフ
ィをすることができる。By forming a positive laminated resist layer such as PMIPK, lithography suitable for the lift-off method can be performed.
さらに、前記実施例では、上下のレジスト層２１．３１
を共に遠紫外線用の同一レジストを用いて形成したので
露光は一回で済み、従って従来方法よりも工程数が少く
なっている。Furthermore, in the embodiment, the upper and lower resist layers 21.31
Since both are formed using the same resist for deep ultraviolet rays, only one exposure is required, and therefore the number of steps is fewer than in the conventional method.
樹脂層８の形成はレジスト層形成装置とほぼ同一のもの
を使用することができる上、短時間で終了する。 また
、従来方法のように蒸着装置等を必要としないので設備
コストが非常に低順である。The resin layer 8 can be formed using almost the same equipment as the resist layer forming apparatus, and can be completed in a short time. In addition, unlike the conventional method, the method does not require a vapor deposition device, so the equipment cost is extremely low.
なお、前記実施例ではレジストの積層数を２とし、上下
のレジスト層を同一レジストで形成したが、レジメ１〜
層数を３以上とし各層を異種レジスｉ・で構成してもよ
いこては勿論である。 また、上下のレジスト層を電子
ビーム露光用レジストで形成し、かつ電子ビーム露光装
置で露光を作ってもよいことは当然である。In the above example, the number of laminated resist layers was set to 2, and the upper and lower resist layers were formed with the same resist.
Of course, the iron may have three or more layers and each layer may be composed of different types of resists. It is also possible to form the upper and lower resist layers using resists for electron beam exposure and to perform exposure using an electron beam exposure apparatus.
［発明の効果］
以上に説明したように、この発明によれば、従来の半導
体装置の製造方法よりも簡単な工程で低コストで高精度
の半導体装置を製造することができる。[Effects of the Invention] As described above, according to the present invention, a high-precision semiconductor device can be manufactured at low cost and through simpler steps than conventional semiconductor device manufacturing methods.
また、従来方法では塗布むらが発生するので不可能とさ
れるレジストの組合せも本発明方法では可能となり、従
って、従来方法よりも多様なかつ精微なパターニングが
可能となる上、露光時間の９−
短縮も可能となった。 ちなみに従来方法では下層の１
９２１〜層をＰＭＭＡのレジストで構成しているが、前
記実施例のように上下両層をＰＭＩＰＫのレジストで構
成すると、従来方法に比べど露光時間は１７２〜１／３
に短縮する。In addition, the method of the present invention enables combinations of resists that are impossible with conventional methods due to uneven coating.Therefore, it is possible to perform more diverse and precise patterning than with conventional methods, and the exposure time is 9-9 times shorter. is now also possible. By the way, in the conventional method, the lower layer 1
The 921~ layer is made of PMMA resist, but if both the upper and lower layers are made of PMIPK resist as in the above example, the exposure time is 172~1/3 compared to the conventional method.
shorten to
第１図及び第２図は従来のバターニング方法を工程順に
示した図、第３図は本発明方法の一実施例を示した図、
である。
１・・・半導体基板、 ２・・・第一レジスト層、 ３
・・・第ニレジスト、 ４・・・（露光装置の）マスク
、５・・・近紫外線、 ６・・・遠紫外線、 ７・・・
無機膜、８・・・樹脂層、 ９・・・（露光装置の）マ
スク、２１・・・第一レジスト層、 ３１・・・第ニレ
ジスト層。
特許出願人 東京芝浦電気株式会社
１０−
第１５！Ｉ 第２図
第３図1 and 2 are diagrams showing a conventional buttering method in the order of steps, and FIG. 3 is a diagram showing an embodiment of the method of the present invention.
It is. 1... Semiconductor substrate, 2... First resist layer, 3
...Second resist, 4...Mask (of exposure equipment), 5...Near ultraviolet rays, 6...Far ultraviolet rays, 7...
Inorganic film, 8... Resin layer, 9... Mask (of exposure device), 21... First resist layer, 31... Second resist layer. Patent applicant Tokyo Shibaura Electric Co., Ltd. 10-15! I Figure 2 Figure 3
Claims (1)
ジスト層を形成する工程と、該積層レジスト層の最上部
レジスト層を選択開口してレジストパターンを形成した
後に該レジストパターンをマスクとしてそれより下層の
レジスト層を順次開口する工程とを含む半導体装置の製
造方法において、 該積層レジスト層の形成工程で各レジスト層間に上下の
各レジスト層に対して相溶性のない樹脂層を形成させて
おくことを特徴とする半導体装置の製造方法。 ２ 積層レジスト層がリフトオフ配線用レジスト層であ
る特許請求の範囲第１項記載の製造方法。[Claims] 1. A step of forming a laminated resist layer consisting of at least two or more layers on a semiconductor substrate, forming a resist pattern by selectively opening the uppermost resist layer of the laminated resist layer, and then opening the resist pattern. A method for manufacturing a semiconductor device including a step of sequentially opening resist layers below the resist layer as a mask, in which a resin layer incompatible with the upper and lower resist layers is formed between each resist layer in the step of forming the laminated resist layer. 1. A method for manufacturing a semiconductor device, characterized by forming the semiconductor device in advance. 2. The manufacturing method according to claim 1, wherein the laminated resist layer is a resist layer for lift-off wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21098583A JPS60103614A (en) | 1983-11-11 | 1983-11-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21098583A JPS60103614A (en) | 1983-11-11 | 1983-11-11 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60103614A true JPS60103614A (en) | 1985-06-07 |
| JPH0469411B2 JPH0469411B2 (en) | 1992-11-06 |
Family
ID=16598398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21098583A Granted JPS60103614A (en) | 1983-11-11 | 1983-11-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60103614A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006108500A (en) * | 2004-10-07 | 2006-04-20 | Shin Etsu Polymer Co Ltd | Method for forming conductive pattern |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58204532A (en) * | 1982-05-24 | 1983-11-29 | Hitachi Ltd | Formation of pattern |
-
1983
- 1983-11-11 JP JP21098583A patent/JPS60103614A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58204532A (en) * | 1982-05-24 | 1983-11-29 | Hitachi Ltd | Formation of pattern |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006108500A (en) * | 2004-10-07 | 2006-04-20 | Shin Etsu Polymer Co Ltd | Method for forming conductive pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0469411B2 (en) | 1992-11-06 |
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