JPS6266630A - Manufacturing of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the steps by using a material having large etching rate with wrong selectivity for etchings as a resist material used for smoothing the surface of a wafer of a lower layer. CONSTITUTION:An Al film 25 is formed on an intermediate insulating film 24. A large step is formed by the pattern of polysilicons 22, 23 in the patterning step of the film 25. To smooth the step, polymethylmethacrylate (PMMA resist) 26 is coated. The resist 26 includes a light absorbing material. Then, Deep-UV light 27 is emitted to photodecompose the resist 26. Then, the pattern of the resist 28 is exposed, developed, and postbaked. The resist 28 is cured by the Deep-UV light 29 in the postbaking step to improve the etching resistance. Then, with the resist 28 as a mask the resist 26 and the film 25 are etched in the step step.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device that allows fine patterning of a photoresist in a photolithography step in the manufacturing process of a semiconductor device (LSI).

(Conventional Technique WI) In the photolithography process of Al film, etc. that uses wiring circuits in the LSI manufacturing process, reflective ion etching (
Multilayer resist technology (RIE) using RIE
Typical etching process 70-ha,ri□・ For example, Semiconductor World 1984+1
1 P64-102).

i o0□ 工. □、2. Smooth the steps on the wafer surface 1 on the Al film 15 having a strong force.
t'''''''''・1 first blc lower layer&')1.-U7.
) 1611 to 3 μm, and the stepped portion of the Al film 15 is cleaned to a level □ 1.Furthermore, as an intermediate layer, for example, StO! is the main component and ′□
A covering film 17 with a thickness of about 0.3 to 0.5 μm is formed.

In this case, a dye that absorbs ultraviolet light (for example, coumarin φ6 (reagent name)) is contained inside the film.

Finally, a positive resist of about 0.5 μm on the intermediate layer 17:
A mask pattern 18 is formed and exposed and developed to form a mask pattern as shown in FIG.

In this Figure 2 (1), 11 is the base layer, 12°:
13 is a pattern (polysilicon, etc.) that causes a step, and 51. Reference numeral 14 denotes an intermediate insulating film (for example, a ring glass) between the wiring layer and the wiring layer.

λ□, 1. Next, as shown in FIG. 2(b), the upper layer i-)'97° 18 is used as an etching mask, and the first
The middle layer 1 was etched by RIE etching at CE40Hz.
7 StO.

By applying etching, the pattern of the upper layer positive resist 18 is transferred to the intermediate layer 17.

Furthermore, as shown in FIG. 2(c), in the second RIE etching using Ar, the pattern is transferred to the lower positive resist 16 by etching the lower positive resist 16 using the pattern of the intermediate layer 17 as a mask. do. At this time, the upper layer positive resist 18 is removed, but the intermediate layer 17, which is resistant to Ar plasma RIE, is removed.
Since this is not etched, the StO of the intermediate layer 17 and the lower layer positive resist 16 immediately below are formed as an etching mask for the LSI.

The RIE method using such a multilayer resist solves the problem that occurs when a circuit pattern is photolithographically formed on the AA film 15 using a single layer resist, that is, the influence of the reflection of light used for exposure on the surface of the Al film 15. By including a dye that absorbs the exposure wavelength inside the layer, and by reducing the influence of the step of the M film 15, the lower layer 16 is 1 to 3.
If it is formed to a thickness of μ'', it is possible to reduce the number of members by 1゛1 and reduce the number of members to 76. 1..

In the process, a multilayer '1 resist-to-screen structure is formed using three different films, and after normal exposure and development,...

Since the RIE process is required twice, the process is very complicated for the mass production process of LSI, and this has been a problem when applied.

This invention solves the problems that the prior art has, 'l
t7) The present invention provides a method for manufacturing a semiconductor device that solves the problems of long and complicated processes.

i 4□, yo. . or.

1 This invention relates to a method for manufacturing such a semiconductor device, and involves coating a wafer with a resist material that has low selectivity and a high etching rate as a lower layer resist with respect to an etching gas used in etching an Al film.
Then, when baking this lower layer resist, □ is first exposed to Deep-UV light, then the upper layer is coated with a normal □ positive resist, and UV exposure and development is performed to create an etching mask for electrode pattern formation. After forming and developing the upper layer resist, Deep −
Further improving its etching resistance using UV light,
Using the upper positive resist pattern as an etching mask, the lower resist layer and the pattern of the electrode layer such as Al are etched in the same process by a reactive ion etching process to form fine electrode wiring.

(Function) According to the present invention, the above steps are introduced in the method for manufacturing a semiconductor device, so that after forming the upper resist (K) circuit pattern by UV exposure, RIE of the Al film is performed.
During etching, the lower resist film and the Al film are etched in the same step using the above-mentioned upper resist film as a mask, thereby completing the patterning.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1 (&) or Figure 1 (
c) is a process explanatory diagram of one example, and this Fig. 1 (
A photolithography process using the multilayer resist technique according to the present invention will be sequentially explained with reference to FIGS. 1(a) to 1(c).

Further, in FIG. 1(a), reference numeral 21 indicates a base such as a silicon substrate or a silicon oxide film, and reference numerals 22 and 23 indicate a film of polysilicon, for example, which becomes a pattern forming a step.

-, 24 are intermediate insulating films with the wiring layer, such as phosphor glass.

A wiring material 5 of Al is formed on this intermediate insulating film 24 .

In the process of patterning the Al wiring material 25, a large step is formed due to the pattern of the underlying polysilicon 22, 23. In order to smooth this level difference, polymethyl methacrylate 26 (hereinafter referred to as PMMA
coated with a resist (called a resist).

This PMMA resist 26 contains a light absorbing material, and a specific example of the resist is 0EBR-1000 (model name) manufactured by Tokyo Applied Chemical Co., Ltd., for example.

In the second and third step of baking the PMMA resist 26, baking is performed at a temperature of about 185 to 200'C and at the same time the photosensitive area 200' of the PMMA resist 26 is
The PMMA resist 26 on the entire surface of the wafer is photolyzed by irradiation with deep-UV light 27 of ~260 nm.

Next, as shown in FIG. 1(b), a regular resist 28 for forming a circuit pattern is replaced with a PMMA resist 2.
6. Coat on top and bake. During this coating, the upper positive resist film 28 is coated to a thickness of 1.0 μm or more, which is thicker than the film thickness of about 0.5 μm used in conventional multilayer resists.

Next, using a UV light exposure machine, the upper layer l diresist 2 is
The upper layer positive resist 28 is patterned by exposing and developing the pattern No. 8 and performing post-baking.

In this boss baking process, baking is performed at about 100 to 130°C for about 60 to 90 seconds using a pot plate method, and as shown in FIG. Deep
- Irradiate the entire surface of the wafer with UV light 29 to cure the upper layer positive resist 28 forming the circuit pattern;
The selectivity of the AA film 25, which is a film to be etched, during RIE etching is increased.

According to the above process, the lower layer PM shown in FIG. 1(a)
Deep-UV i! when baking the MA resist 26.
Since 7 photons are applied, the PMM in the lower layer is destroyed by photolysis.
Since the molecular weight of the A resist 26 is reduced, it is possible to minimize the interlayer layer, which is a compound of the two resists, that forms at the interface with the upper layer positive resist 28 (see Figure 1). This can be removed by irradiating O and plasma for about 30 seconds.

Next, using the positive resist pattern that is the upper layer positive resist 28 as an etching mask, RIE etching is performed on the Al film 25 as shown in FIG. 1(c).
Since E-etching has extremely high directionality, using the upper layer positive resist 28 as a mask, the lower layer photodecomposed PMMA is etched.
By etching the resist 26 and the Al film 25 with good directionality, an Al circuit pattern can be formed.

In this etching, the relative difference in etching rate of each layer is 28:2500A for the upper layer positive resist and 26:2500A for the PMMA resist for the same etching time.
0A, Al-8l-Cu: about 8000A, and the resist film thickness composition is upper layer positive resist 28:PMM.
A resist 26:Al film thickness ratio is 1.5:0.5
: By forming it to about 1 *, it is possible to form a fine pattern of electrode wiring.

(Effects of the Invention) As explained in detail above, the present invention is particularly effective as a resist material used for smoothing the underlying wafer surface.
A material with a high etching rate that has extremely poor selectivity for IE etching is used, a normal positive resist is used as the resist film for transferring the upper layer circuit pattern, and UVg
After forming a circuit pattern on the upper resist layer using light, during the above-mentioned RIE etching of the Al film, the lower resist film and the Al film are etched in the same process using the upper resist film as a mask to complete the Bata-Jung process. Therefore, the process can be extremely simplified, and the M layer can also be finely patterned.

[Brief explanation of drawings]

I FIGS. 1(a) to 1(e) are process explanatory diagrams of one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG.
Figures (a) 1 to 2 (c) are process explanatory diagrams of a conventional semiconductor device manufacturing method. Intermediate insulating film, 25... Al film, 2
6...□ PMMA resist, 27, 29 - Deep-UV light, l 28... Upper layer positive resist. Patent Applicant: Oki Electric Industry Co., Ltd. No. 2C No. 4 Total 8th Printing I 5114
Figure 1

Claims (1)

[Scope of Claims] (a) A resist material with low selectivity and high etching rate for etching gases and etchants used in electrode pattern formation such as Al film etching is coated on the wafer as a lower layer resist, and the surface of the wafer is (b) Before baking the lower layer resist, it is exposed to Deep-UV light in advance to lower the molecular weight through photolysis, thereby lowering the etching resistance; (c) the upper layer resist. coated with regular positive resist and exposed to UV
(d) forming an upper layer positive resist that becomes a masking layer during etching using Deep-UV light during a baking process after developing the upper layer resist; curing and hardening the layer to further improve the etching resistance of the upper layer positive resist, and (e) using the upper layer positive resist pattern as an etching mask to improve the etching resistance of the lower layer using a reactive ion etching process. A smoothed resist layer with low
A method for manufacturing a semiconductor device, comprising: a step of etching a pattern of an electrode layer such as L in the same process to form fine electrode wiring;