JPH0120782B2 - - Google Patents

Info

Publication number
JPH0120782B2
JPH0120782B2 JP25477484A JP25477484A JPH0120782B2 JP H0120782 B2 JPH0120782 B2 JP H0120782B2 JP 25477484 A JP25477484 A JP 25477484A JP 25477484 A JP25477484 A JP 25477484A JP H0120782 B2 JPH0120782 B2 JP H0120782B2
Authority
JP
Japan
Prior art keywords
memory
dma
data
data transfer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP25477484A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61133460A (ja
Inventor
Kazuhiko Kobori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Juki Corp
Original Assignee
Juki Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Juki Corp filed Critical Juki Corp
Priority to JP25477484A priority Critical patent/JPS61133460A/ja
Publication of JPS61133460A publication Critical patent/JPS61133460A/ja
Publication of JPH0120782B2 publication Critical patent/JPH0120782B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP25477484A 1984-11-30 1984-11-30 メモリ間のデ−タ転送におけるダイレクト・メモリ・アクセス実行方法 Granted JPS61133460A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25477484A JPS61133460A (ja) 1984-11-30 1984-11-30 メモリ間のデ−タ転送におけるダイレクト・メモリ・アクセス実行方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25477484A JPS61133460A (ja) 1984-11-30 1984-11-30 メモリ間のデ−タ転送におけるダイレクト・メモリ・アクセス実行方法

Publications (2)

Publication Number Publication Date
JPS61133460A JPS61133460A (ja) 1986-06-20
JPH0120782B2 true JPH0120782B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-04-18

Family

ID=17269693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25477484A Granted JPS61133460A (ja) 1984-11-30 1984-11-30 メモリ間のデ−タ転送におけるダイレクト・メモリ・アクセス実行方法

Country Status (1)

Country Link
JP (1) JPS61133460A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01258163A (ja) * 1988-04-08 1989-10-16 Fujitsu Ltd ダイレクトメモリアクセス制御装置

Also Published As

Publication number Publication date
JPS61133460A (ja) 1986-06-20

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