JP7475503B2 - 半導体基板の製造方法および半導体装置の製造方法 - Google Patents

半導体基板の製造方法および半導体装置の製造方法 Download PDF

Info

Publication number
JP7475503B2
JP7475503B2 JP2022579226A JP2022579226A JP7475503B2 JP 7475503 B2 JP7475503 B2 JP 7475503B2 JP 2022579226 A JP2022579226 A JP 2022579226A JP 2022579226 A JP2022579226 A JP 2022579226A JP 7475503 B2 JP7475503 B2 JP 7475503B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor layer
nitride semiconductor
reversible adhesive
adhesive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022579226A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2022168217A5 (https=
JPWO2022168217A1 (https=
Inventor
秀一 檜座
邦彦 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of JPWO2022168217A1 publication Critical patent/JPWO2022168217A1/ja
Publication of JPWO2022168217A5 publication Critical patent/JPWO2022168217A5/ja
Application granted granted Critical
Publication of JP7475503B2 publication Critical patent/JP7475503B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H10P34/422Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing using incoherent radiation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416Nitrides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding

Landscapes

  • Recrystallisation Techniques (AREA)
JP2022579226A 2021-02-04 2021-02-04 半導体基板の製造方法および半導体装置の製造方法 Active JP7475503B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/004035 WO2022168217A1 (ja) 2021-02-04 2021-02-04 半導体基板の製造方法および半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JPWO2022168217A1 JPWO2022168217A1 (https=) 2022-08-11
JPWO2022168217A5 JPWO2022168217A5 (https=) 2023-04-06
JP7475503B2 true JP7475503B2 (ja) 2024-04-26

Family

ID=82740968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022579226A Active JP7475503B2 (ja) 2021-02-04 2021-02-04 半導体基板の製造方法および半導体装置の製造方法

Country Status (6)

Country Link
US (1) US20240030055A1 (https=)
EP (1) EP4290553A4 (https=)
JP (1) JP7475503B2 (https=)
KR (1) KR102760469B1 (https=)
CN (1) CN116868309A (https=)
WO (1) WO2022168217A1 (https=)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109208A (ja) 2003-09-30 2005-04-21 Shin Etsu Handotai Co Ltd 発光素子の製造方法
JP2012524399A (ja) 2009-04-16 2012-10-11 スス マイクロテク リソグラフィー,ゲーエムベーハー 一時的なウェハーボンディング及びデボンディングのための改善された装置
JP2014239179A (ja) 2013-06-10 2014-12-18 日本電信電話株式会社 窒化物半導体装置の製造方法
WO2017119412A1 (ja) 2016-01-07 2017-07-13 国立研究開発法人産業技術総合研究所 光可逆接着剤
WO2018143344A1 (ja) 2017-02-02 2018-08-09 三菱電機株式会社 半導体製造方法および半導体製造装置
JP2018538684A (ja) 2015-11-20 2018-12-27 アールエフエイチアイシー コーポレイション デバイス処理のための半導体オンダイヤモンドウェハのマウンティング
JP2019527477A (ja) 2016-07-12 2019-09-26 キューエムエイティ・インコーポレーテッド ドナー基材を再生するための方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268183A (ja) 1993-03-15 1994-09-22 Fujitsu Ltd 半導体装置の製造方法
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
WO2002084631A1 (en) * 2001-04-11 2002-10-24 Sony Corporation Element transfer method, element arrangmenet method using the same, and image display apparatus production method
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
EP1571705A3 (fr) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Réalisation d'une entité en matériau semiconducteur sur substrat
JP4654389B2 (ja) * 2006-01-16 2011-03-16 株式会社ムサシノエンジニアリング ダイヤモンドヒートスプレッダの常温接合方法,及び半導体デバイスの放熱部
US20080122119A1 (en) * 2006-08-31 2008-05-29 Avery Dennison Corporation Method and apparatus for creating rfid devices using masking techniques
FR2921515B1 (fr) * 2007-09-25 2010-07-30 Commissariat Energie Atomique Procede de fabrication de structures semiconductrices utiles pour la realisation de substrats semiconducteur- sur-isolant, et ses applications.
JP5466578B2 (ja) * 2010-05-27 2014-04-09 株式会社神戸製鋼所 ダイヤモンド・アルミニウム接合体及びその製造方法
WO2014095373A1 (en) * 2012-12-18 2014-06-26 Element Six Limited Substrates for semiconductor devices
JP6004100B2 (ja) * 2013-05-24 2016-10-05 富士電機株式会社 半導体装置の製造方法
GB201610886D0 (en) * 2016-06-22 2016-08-03 Element Six Tech Ltd Bonding of diamond wafers to carrier substrates
JP2019026817A (ja) 2017-08-04 2019-02-21 国立研究開発法人産業技術総合研究所 光応答性粘接着剤
KR102734318B1 (ko) * 2019-11-08 2024-11-25 에베 그룹 에. 탈너 게엠베하 기판 결합 장치 및 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109208A (ja) 2003-09-30 2005-04-21 Shin Etsu Handotai Co Ltd 発光素子の製造方法
JP2012524399A (ja) 2009-04-16 2012-10-11 スス マイクロテク リソグラフィー,ゲーエムベーハー 一時的なウェハーボンディング及びデボンディングのための改善された装置
JP2014239179A (ja) 2013-06-10 2014-12-18 日本電信電話株式会社 窒化物半導体装置の製造方法
JP2018538684A (ja) 2015-11-20 2018-12-27 アールエフエイチアイシー コーポレイション デバイス処理のための半導体オンダイヤモンドウェハのマウンティング
WO2017119412A1 (ja) 2016-01-07 2017-07-13 国立研究開発法人産業技術総合研究所 光可逆接着剤
JP2019527477A (ja) 2016-07-12 2019-09-26 キューエムエイティ・インコーポレーテッド ドナー基材を再生するための方法
WO2018143344A1 (ja) 2017-02-02 2018-08-09 三菱電機株式会社 半導体製造方法および半導体製造装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FRANCIS D et al.,Formation and characterization of 4-inch GaN-on-diamond substrates,Diamond and Related Materials,Elsevier,2010年02月,Volume 19, Issues 2-3,Pages 229-233,https://www.sciencedirect.com/science/article/pii/S0925963509002441,doi:10.1016/j.diamond.2009.08.017

Also Published As

Publication number Publication date
KR20230116016A (ko) 2023-08-03
EP4290553A1 (en) 2023-12-13
WO2022168217A1 (ja) 2022-08-11
CN116868309A (zh) 2023-10-10
US20240030055A1 (en) 2024-01-25
JPWO2022168217A1 (https=) 2022-08-11
KR102760469B1 (ko) 2025-01-24
EP4290553A4 (en) 2024-04-03

Similar Documents

Publication Publication Date Title
CN104145330B (zh) 用于临时接合超薄晶片的方法和装置
CN104867859B (zh) 包括电介质材料的半导体器件
JP2022515871A5 (https=)
TW201214585A (en) Method for manufacturing semiconductor device
JP2019125785A (ja) ウェハの処理方法
FR2848337A1 (fr) Procede de realisation d'une structure complexe par assemblage de structures contraintes
JP4284911B2 (ja) 素子の転写方法
CN105810595B (zh) 用于处理产品衬底的方法、粘结的衬底系统以及临时粘合剂
KR102588785B1 (ko) 반도체 소자의 제조 방법
KR101942967B1 (ko) 실록산계 단량체를 이용한 접합 기판 구조체 및 그 제조방법
JP7475503B2 (ja) 半導体基板の製造方法および半導体装置の製造方法
TW202425081A (zh) 半導體裝置之製造方法
JP2009500819A (ja) 酸化物もしくは窒化物の薄い結合層を堆積することによる基板の組み立て方法
CN115428127B (zh) 半导体元件的制造方法
JP2009521813A (ja) 歪み薄膜の緩和方法
JP4856861B2 (ja) 半導体装置の製造方法
US8778112B2 (en) Method for bonding thin film piece
WO2021199426A1 (ja) 研磨方法、半導体基板の製造方法
CN111668122B (zh) 半导体封装方法
JP6004343B2 (ja) 半導体装置の製造方法
JP7482339B1 (ja) 受け取り基板、レーザリフトオフ方法、リフト方法、保持方法、及び微小構造体の洗浄方法
US20230377935A1 (en) Temporary bonding method
CN111383929B (zh) 晶圆塑封方法、晶圆级封装结构及其封装方法、塑封模具
CN121843311A (zh) 微型发光结构及其制备方法、以及微型发光器件
CN120127028A (zh) 一种提升键合效果的键合方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230124

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230124

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240319

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240416

R150 Certificate of patent or registration of utility model

Ref document number: 7475503

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150