JP7328369B2 - 拡大した接合部限界寸法を有する3次元メモリデバイスおよびそのデバイスを形成するための方法 - Google Patents
拡大した接合部限界寸法を有する3次元メモリデバイスおよびそのデバイスを形成するための方法 Download PDFInfo
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- JP7328369B2 JP7328369B2 JP2021576669A JP2021576669A JP7328369B2 JP 7328369 B2 JP7328369 B2 JP 7328369B2 JP 2021576669 A JP2021576669 A JP 2021576669A JP 2021576669 A JP2021576669 A JP 2021576669A JP 7328369 B2 JP7328369 B2 JP 7328369B2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 28
- 230000005641 tunneling Effects 0.000 claims description 24
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 36
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
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- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
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- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
102 基板
103 接合部酸化物層
105 半導体プラグ
106 誘電体層
107 メモリスタック
107A 下部メモリデッキ
107B 上部メモリデッキ
109 導体層
110 メモリ膜
112 遮断層
114 貯蔵層
116 トンネリング層
118 半導体チャネル
122 下部チャネルホール
124 上部チャネルホール
200 3Dメモリデバイス
202 基板
203 接合部酸化物層
205 半導体プラグ
206 誘電体層
2061 誘電体層
207 メモリスタック
207A 下部メモリデッキ
207B 上部メモリデッキ
209 導体層
210 メモリ膜
212 遮断層
2121 遮断層212の小さい部分
2122 遮断層212の小さい部分
2123 連続した鉛直層
214 貯蔵層
216 トンネリング層
218 半導体チャネル
222 チャネルホール
224 チャネルホール
300 3Dメモリデバイス
302 シリコン基板
303 接合部酸化物層
304 誘電体スタック
304A 下部誘電体デッキ
304B 上部誘電体デッキ
305 シリコンプラグ
306 誘電体層
307 メモリスタック
307A 下部メモリデッキ
307B 上部メモリデッキ
308 犠牲層
309 導体層
310 メモリ膜
311 凹部
312 遮断層
314 貯蔵層
316 トンネリング層
318 半導体チャネル
320 チャネルホール
322 下部チャネルホール
324 上部チャネルホール
Claims (27)
- 基板と、
前記基板上に交互に積み重ねられた複数の導体層と誘電体層とを備えるメモリスタックであって、前記導体層は前記誘電体層と接するメモリスタックと、
前記メモリスタックを通って垂直に延在するメモリストリングであって、前記メモリストリングの側壁に沿ったメモリ膜を備えるメモリストリングと
を備える3次元(3D)メモリデバイスであって、
前記メモリスタックが、接合部酸化物層によって分離された上部デッキおよび下部デッキを備え、前記メモリ膜が、貯蔵層と、前記上部デッキおよび前記下部デッキ内の前記誘電体層によって分離された不連続な誘電材料層とを備え、前記不連続な誘電材料層が前記貯蔵層と接し、前記上部デッキおよび前記下部デッキ内の前記不連続な誘電材料層の側壁が、前記接合部酸化物層の側壁と実質的に同一平面にある、3次元(3D)メモリデバイス。 - 前記不連続な誘電材料層が1つまたは複数の部分を備え、
少なくとも1つの部分が導体層の凹部にあって、隣接した誘電体層と、前記導体層の側面とによって囲まれている、請求項1に記載の3Dメモリデバイス。 - 前記不連続な誘電材料層が全面的に不連続である、請求項1または2に記載の3Dメモリデバイス。
- 前記不連続な誘電材料層が部分的に不連続である、請求項1または2に記載の3Dメモリデバイス。
- 前記不連続な誘電材料層の厚さが約4nm~約10nmである、請求項1または2に記載の3Dメモリデバイス。
- 前記メモリ膜がトンネリング層をさらに備える、請求項1または2に記載の3Dメモリデバイス。
- 前記不連続な誘電材料層および前記誘電体層のうちの少なくとも1つが酸化シリコンを含む、請求項1または2に記載の3Dメモリデバイス。
- 前記不連続な誘電材料層の側壁が、前記誘電体層の側壁と実質的に同一平面にある、請求項1に記載の3Dメモリデバイス。
- 基板と、
前記基板上に交互に積み重ねられた複数の導体層と誘電体層とを備えるメモリスタックであって、前記導体層は前記誘電体層と接するメモリスタックと、
前記メモリスタックを通って垂直に延在するメモリストリングであって、前記メモリストリングの側壁に沿ったメモリ膜を備えるメモリストリングと
を備える3次元(3D)メモリデバイスであって、
前記メモリスタックが、接合部酸化物層によって分離された上部デッキおよび下部デッキを備え、前記メモリ膜が、貯蔵層と、前記上部デッキおよび前記下部デッキ内の前記誘電体層によって分離された不連続な誘電材料層とを備え、
前記不連続な誘電材料層が前記貯蔵層と接し、
前記不連続な誘電材料層が複数の部分を備え、
前記不連続な誘電材料層の前記複数の部分のうち隣接した部分のどれも、互いに接触せず、
前記不連続な誘電材料層の側壁が、前記接合部酸化物層の側壁と実質的に同一平面にある、3次元(3D)メモリデバイス。 - 前記不連続な誘電材料層の厚さが約4nm~約10nmである、請求項9に記載の3Dメモリデバイス。
- 前記メモリ膜がトンネリング層をさらに備える、請求項9または10に記載の3Dメモリデバイス。
- 前記不連続な誘電材料層および前記誘電体層のうちの少なくとも1つが酸化シリコンを含む、請求項9または10に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイスを形成するための方法であって、
基板上に、交互に積み重ねられた犠牲層と誘電体層とを含む誘電体デッキを形成するステップと、
前記誘電体デッキを通って垂直に延在する開口を形成するステップと、
前記開口の側壁と接する、前記犠牲層の側面をエッチングするステップと、
前記犠牲層がエッチングされる位置に、不連続な誘電材料層を形成するステップと、
続いて、前記不連続な誘電材料層と、前記不連続な誘電材料層の間の前記誘電体層との上に、貯蔵層、トンネリング層、および半導体チャネルを形成するステップであって、前記不連続な誘電材料層が前記貯蔵層と接する、ステップと
を含む方法。 - 前記誘電体デッキの前記犠牲層を導体層で置換することにより、交互に積み重ねられた前記導体層と前記誘電体層とを備えるメモリスタックを形成するステップをさらに含む、請求項13に記載の方法。
- 前記不連続な誘電材料層が1つまたは複数の部分を含み、
少なくとも1つの部分が導体層の凹部に形成され、隣接した誘電体層と前記導体層の側面とによって囲まれている、請求項14に記載の方法。 - 前記不連続な誘電材料層が全面的に不連続である、請求項13から15のいずれか一項に記載の方法。
- 前記不連続な誘電材料層が部分的に不連続である、請求項13から15のいずれか一項に記載の方法。
- 前記開口の前記側壁に接する、前記犠牲層の前記側面が約1nm~約4nmエッチングされる、請求項13から15のいずれか一項に記載の方法。
- 前記不連続な誘電材料層を形成するステップが、前記犠牲層の前記エッチングされた側面を酸化させるステップを含む、請求項13から15のいずれか一項に記載の方法。
- 前記不連続な誘電材料層が熱酸化または湿式化学酸化のうちの1つによって形成される、請求項19に記載の方法。
- 酸化されている前記犠牲層の厚さが約3nm~約6nmである、請求項19に記載の方法。
- 前記不連続な誘電材料層の厚さが約4nm~約10nmである、請求項13から15のいずれか一項に記載の方法。
- 前記不連続な誘電材料層および前記誘電体層のうちの少なくとも1つが酸化シリコンを含む、請求項13から15のいずれか一項に記載の方法。
- 前記犠牲層が窒化シリコンを含む、請求項13から15のいずれか一項に記載の方法。
- 前記犠牲層の前記側面をエッチングする前に、前記開口の下部に半導体プラグを形成するステップをさらに含む、請求項13から15のいずれか一項に記載の方法。
- 前記誘電体デッキが、接合部酸化物層によって分離された上部デッキおよび下部デッキを備え、
前記不連続な誘電材料層も前記接合部酸化物層によって分離されており、
前記不連続な誘電材料層の側壁が、前記接合部酸化物層の側壁と実質的に同一平面にある、請求項13から15のいずれか一項に記載の方法。 - 前記不連続な誘電材料層の前記側壁が、前記誘電体層の側壁と実質的に同一平面にある、請求項26に記載の方法。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170243879A1 (en) | 2016-02-22 | 2017-08-24 | Sandisk Technologies Inc. | Three dimensional memory device containing discrete silicon nitride charge storage regions |
US20180331117A1 (en) | 2017-05-12 | 2018-11-15 | Sandisk Technologies Llc | Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof |
WO2019089152A1 (en) | 2017-11-06 | 2019-05-09 | Sandisk Technologies Llc | Three-dimensional memory device with annular blocking dielectrics and method of making thereof |
CN110168728A (zh) | 2019-04-12 | 2019-08-23 | 长江存储科技有限责任公司 | 具有沉积的半导体插塞的三维存储器件及其形成方法 |
JP2019169554A (ja) | 2018-03-22 | 2019-10-03 | 東芝メモリ株式会社 | 記憶装置 |
WO2019194895A1 (en) | 2018-04-04 | 2019-10-10 | Western Digital Technologies, Inc. | Non-volatile storage system with adjustable select gates as a function of temperature |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101551901B1 (ko) * | 2008-12-31 | 2015-09-09 | 삼성전자주식회사 | 반도체 기억 소자 및 그 형성 방법 |
US20100314678A1 (en) * | 2009-06-12 | 2010-12-16 | Se-Yun Lim | Non-volatile memory device and method for fabricating the same |
JP2013543266A (ja) * | 2010-10-18 | 2013-11-28 | アイメック | 縦型半導体メモリデバイス及びその製造方法 |
US8946808B2 (en) * | 2012-02-09 | 2015-02-03 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
KR102018614B1 (ko) * | 2012-09-26 | 2019-09-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
WO2014089795A1 (zh) * | 2012-12-13 | 2014-06-19 | 中国科学院微电子研究所 | 一种垂直沟道型三维半导体存储器件及其制备方法 |
US9786678B2 (en) * | 2014-09-11 | 2017-10-10 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device and method of manufacturing the same |
US9666590B2 (en) * | 2014-09-24 | 2017-05-30 | Sandisk Technologies Llc | High stack 3D memory and method of making |
US9236396B1 (en) * | 2014-11-12 | 2016-01-12 | Sandisk Technologies Inc. | Three dimensional NAND device and method of making thereof |
CN107548520B (zh) * | 2015-02-24 | 2021-05-25 | 东芝存储器株式会社 | 半导体存储装置及其制造方法 |
KR20170002080A (ko) * | 2015-06-29 | 2017-01-06 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US9570463B1 (en) * | 2015-10-15 | 2017-02-14 | Sandisk Technologies Llc | Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same |
US9991280B2 (en) * | 2016-02-17 | 2018-06-05 | Sandisk Technologies Llc | Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same |
US10090318B2 (en) * | 2016-08-05 | 2018-10-02 | Micron Technology, Inc. | Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure |
US9881929B1 (en) * | 2016-10-27 | 2018-01-30 | Sandisk Technologies Llc | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof |
US10141328B2 (en) * | 2016-12-15 | 2018-11-27 | Macronix International Co., Ltd. | Three dimensional memory device and method for fabricating the same |
CN109935593B (zh) * | 2017-03-08 | 2021-09-28 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
CN106910746B (zh) * | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法、封装方法 |
US10319635B2 (en) * | 2017-05-25 | 2019-06-11 | Sandisk Technologies Llc | Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof |
WO2019055073A1 (en) * | 2017-09-14 | 2019-03-21 | Sandisk Technologies Llc | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ANNULAR ENGRAVING STOP SPACER AND METHOD FOR MANUFACTURING THE SAME |
CN107946306A (zh) * | 2017-11-23 | 2018-04-20 | 长江存储科技有限责任公司 | 三维存储结构制作方法、存储结构、存储器及电子设备 |
US10580782B2 (en) * | 2017-12-28 | 2020-03-03 | Micron Technology, Inc. | Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor |
US11342498B2 (en) * | 2018-01-08 | 2022-05-24 | Integrated Silicon Solution (cayman) Inc. | High density 3D magnetic random access memory (MRAM) cell integration using wafer cut and transfer |
CN109196643B (zh) * | 2018-06-12 | 2019-11-05 | 长江存储科技有限责任公司 | 存储器件及其形成方法 |
KR20190140773A (ko) * | 2018-06-12 | 2019-12-20 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조방법 |
WO2020000306A1 (en) * | 2018-06-28 | 2020-01-02 | Yangtze Memory Technologies Co., Ltd. | Staircase structures for three-dimensional memory device double-sided routing |
JP2020009904A (ja) * | 2018-07-09 | 2020-01-16 | キオクシア株式会社 | 半導体メモリ |
CN111244100B (zh) * | 2018-08-16 | 2022-06-14 | 长江存储科技有限责任公司 | 用于形成三维存储器器件中的结构增强型半导体插塞的方法 |
CN109314118B (zh) * | 2018-08-21 | 2019-11-08 | 长江存储科技有限责任公司 | 具有贯穿阵列触点的三维存储器件及其形成方法 |
CN109417074A (zh) * | 2018-09-27 | 2019-03-01 | 长江存储科技有限责任公司 | 在三维存储器件中由保护性电介质层保护的半导体插塞及其形成方法 |
WO2020073185A1 (en) * | 2018-10-09 | 2020-04-16 | Yangtze Memory Technologies Co., Ltd. | Methods for reducing defects in semiconductor plug in three-dimensional memory device |
CN109712980B (zh) * | 2018-11-21 | 2023-08-08 | 长江存储科技有限责任公司 | 3d存储器件的制造方法及3d存储器件 |
-
2020
- 2020-01-21 CN CN202080000169.0A patent/CN111263980B/zh active Active
- 2020-01-21 EP EP20915063.0A patent/EP3963629A4/en active Pending
- 2020-01-21 JP JP2021576669A patent/JP7328369B2/ja active Active
- 2020-01-21 KR KR1020217042227A patent/KR102673608B1/ko active IP Right Grant
- 2020-01-21 WO PCT/CN2020/073359 patent/WO2021146878A1/en unknown
- 2020-01-21 CN CN202110879743.0A patent/CN113594173B/zh active Active
- 2020-03-17 TW TW109108717A patent/TWI751509B/zh active
- 2020-04-28 US US16/860,890 patent/US11205661B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170243879A1 (en) | 2016-02-22 | 2017-08-24 | Sandisk Technologies Inc. | Three dimensional memory device containing discrete silicon nitride charge storage regions |
WO2017146808A1 (en) | 2016-02-22 | 2017-08-31 | Sandisk Technologies Llc | Three dimensional memory device containing discrete silicon nitride charge storage regions |
US20180331117A1 (en) | 2017-05-12 | 2018-11-15 | Sandisk Technologies Llc | Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof |
WO2019089152A1 (en) | 2017-11-06 | 2019-05-09 | Sandisk Technologies Llc | Three-dimensional memory device with annular blocking dielectrics and method of making thereof |
US20190139973A1 (en) | 2017-11-06 | 2019-05-09 | Sandisk Technologies Llc | Three-dimensional memory device with annular blocking dielectrics and method of making thereof |
JP2019169554A (ja) | 2018-03-22 | 2019-10-03 | 東芝メモリ株式会社 | 記憶装置 |
WO2019194895A1 (en) | 2018-04-04 | 2019-10-10 | Western Digital Technologies, Inc. | Non-volatile storage system with adjustable select gates as a function of temperature |
US20190311770A1 (en) | 2018-04-04 | 2019-10-10 | Western Digital Technologies, Inc. | Non-volatile storage system with adjustable select gates as a function of temperature |
JP2021512447A (ja) | 2018-04-04 | 2021-05-13 | ウェスタン デジタル テクノロジーズ インコーポレーテッド | 温度に応じて調節可能な選択ゲートを有する非揮発性記憶システム |
CN110168728A (zh) | 2019-04-12 | 2019-08-23 | 长江存储科技有限责任公司 | 具有沉积的半导体插塞的三维存储器件及其形成方法 |
WO2020206681A1 (en) | 2019-04-12 | 2020-10-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with deposited semiconductor plugs and methods for forming the same |
US20200328225A1 (en) | 2019-04-12 | 2020-10-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with deposited semiconductor plugs and methods for forming the same |
JP2022528733A (ja) | 2019-04-12 | 2022-06-15 | 長江存儲科技有限責任公司 | 半導体プラグが堆積された三次元メモリデバイス及びその形成方法 |
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