JP7328148B2 - アレイ基板及びその製造方法、ディスプレイパネル及び表示装置 - Google Patents
アレイ基板及びその製造方法、ディスプレイパネル及び表示装置 Download PDFInfo
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Description
ベース基板と、
前記ベース基板上に位置し、光透過孔を含む遮光層と、
前記遮光層の前記ベース基板から離れた側に位置する薄膜トランジスタのアクティブ層と、
前記ベース基板上に位置し、前記光透過孔に連通している第1貫通孔を含む絶縁層とを備える。
本開示のいくつかの実施例において、前記光透過孔の前記ベース基板での正投影が完全に前記第1貫通孔の前記ベース基板での正投影内にある。
ベース基板を提供するステップと、
前記ベース基板上に遮光膜層を形成するステップと、
前記遮光膜層上に薄膜トランジスタのアクティブ層を形成するステップと、
前記アクティブ層を形成した後、前記遮光膜層をパターニングして、光透過孔を含む遮光層を形成するステップとを含む。
ステップS518:ソース529、ドレイン526及び接続電極571上に平坦化層527、第1電極552及び画素画定層555を形成し、第1電極552は、平坦化層527でのビアホールを介してソース又はドレインに接続される(図2D参照)。
図3Bに示されるように、アレイ基板100は、ゲート絶縁層122及びパッシベーション層124に位置する第3ビアホール133、層間絶縁層125に位置する第4ビアホール134、及び層間絶縁層125が形成された後であって平坦化層127の前に形成された接続電極171をさらに備える。
ベース基板を提供するステップと、
前記ベース基板上に遮光膜層を形成するステップと、
前記遮光膜層上に薄膜トランジスタのアクティブ層を形成するステップとを含み、
たとえば、図3Aに示されるように、本開示の少なくとも1つの実施例に係るアレイ基板の製造方法は、ステップS10~ステップS40を含む。
ステップS211:第2コンデンサ電極142上に層間絶縁膜層1250を形成する(図4K参照)。
(1)本発明の実施例の図面では、本発明の実施例に係る構造のみを示しており、ほかの構造は、通常の設計を参照すればよい。
(2)明瞭さから、本発明の実施例を説明するための図面において、層又は構造の厚さ及び寸法が拡大されている。なお、層、膜、領域又は基板のような素子が別の素子の「上」又は「下」に位置する場合、該素子は、別の素子の「上」又は「下」に「直接」位置してもよく、中間素子が存在してもよい。
(3)矛盾しない限り、本発明の同一実施例及び異なる実施例における特徴を互いに組み合わせ得る。
20 表示装置
100 アレイ基板
111 ベース基板
112 薄膜トランジスタ
113 遮光層
114 光透過孔
115 イメージングデバイス
116 アクティブ層
121 緩衝層
122 ゲート絶縁層
123 ゲート
124 パッシベーション層
125 層間絶縁層
126 ドレイン
127 平坦化層
129 ソース
131 第2ビアホール
132 第1ビアホール
133 第3ビアホール
134 第4ビアホール
135 第5ビアホール
136 第6ビアホール
141 第1コンデンサ電極
142 第2コンデンサ電極
151 発光素子
152 第1電極
153 発光層
154 第2電極
155 画素画定層
156 スペーサー
161 表示領域
162 周辺領域
171 接続電極
191 コンデンサ電極金属層
198 電極充填構造
199 充填構造
511 ベース基板
512 薄膜トランジスタ
513 遮光層
514 孔
515 イメージングデバイス
516 アクティブ層
521 緩衝層
522 ゲート絶縁層
523 ゲート
524 パッシベーション層
525 層間絶縁層
526 ドレイン
527 平坦化層
529 ソース
531 第2ビアホール
533 第3ビアホール
534 第4ビアホール
552 第1電極
553 発光層
555 画素画定層
561 表示領域
562 周辺領域
571 接続電極
581 駆動バックプレーン
582 膜層
583 カバープレート
584 遮光領域
1130 遮光膜層
1210 緩衝膜層
1211 緩衝中間層
1220 ゲート絶縁膜層
1221 ゲート絶縁中間層
1240 パッシベーション膜層
1241 パッシベーション中間層
1250 層間絶縁膜層
Claims (21)
- アレイ基板であって、
ベース基板と、
前記ベース基板上に位置し、光透過孔を含む遮光層と、
前記遮光層の前記ベース基板から離れた側に位置する薄膜トランジスタのアクティブ層と、
前記ベース基板上に位置し、前記光透過孔に連通している第1貫通孔を含む絶縁層とを含み、
前記絶縁層は、緩衝層、パッシベーション層、ゲート絶縁層及び層間絶縁層の少なくとも1つを含み、
前記アレイ基板は、接続電極をさらに備えており、前記接続電極は、前記緩衝層、前記パッシベーション層、前記ゲート絶縁層及び前記層間絶縁層の少なくとも1つを貫通している第3貫通孔を介して前記遮光層に接続される、アレイ基板。 - 前記第1貫通孔の前記ベース基板での正投影が前記アクティブ層の前記ベース基板での正投影と重ならない請求項1に記載のアレイ基板。
- 前記光透過孔の前記ベース基板での正投影が完全に前記第1貫通孔の前記ベース基板での正投影内にある請求項1又は2に記載のアレイ基板。
- 前記第1貫通孔及び前記光透過孔に充填される充填構造をさらに備える請求項1-3のいずれか1項に記載のアレイ基板。
- 前記第1貫通孔及び前記光透過孔は、前記充填構造により完全に充填されている請求項4に記載のアレイ基板。
- 前記絶縁層の前記ベース基板から離れた側に位置し、前記充填構造とは一体に形成された充填層をさらに備える請求項4又は5に記載のアレイ基板。
- 前記充填層は、パッシベーション層、ゲート絶縁層、層間絶縁層及び平坦化層のうちのいずれか一つを含む請求項6に記載のアレイ基板。
- ソース及びドレインをさらに備え、前記ソースと前記ドレインは、前記パッシベーション層、前記ゲート絶縁層及び前記層間絶縁層の少なくとも1つを貫通している第2貫通孔を介して、それぞれ前記アクティブ層に接続される請求項1-7のいずれか1項に記載のアレイ基板。
- 前記光透過孔は、少なくとも部分的に前記アレイ基板の画素の間に位置する請求項1-8のいずれか1項に記載のアレイ基板。
- 前記ベース基板の前記遮光層から離れた側に位置するイメージングデバイスをさらに備え、前記イメージングデバイスは、前記ベース基板に垂直な方向に少なくとも部分的に前記光透過孔と重なる請求項1-9のいずれか1項に記載のアレイ基板。
- ディスプレイパネルであって、請求項1-10のいずれか1項に記載のアレイ基板を備えるディスプレイパネル。
- 表示装置であって、請求項1-10のいずれか1項に記載のアレイ基板又は請求項11に記載のディスプレイパネルを備える表示装置。
- アレイ基板の製造方法であって、
ベース基板を提供するステップと、
前記ベース基板上に遮光膜層を形成するステップと、
前記遮光膜層上に薄膜トランジスタのアクティブ層を形成するステップと、
前記アクティブ層を形成した後、前記遮光膜層をパターニングして、光透過孔を含む遮光層を形成するステップとを含むアレイ基板の製造方法。 - 絶縁層を形成し、第1貫通孔の前記ベース基板での正投影が前記アクティブ層の前記ベース基板での正投影と重ならないように前記絶縁層をパターニングして前記第1貫通孔を形成し、前記第1貫通孔を介して前記遮光膜層をパターニングして前記光透過孔を形成するステップをさらに含む請求項13に記載のアレイ基板の製造方法。
- 前記第1貫通孔及び前記光透過孔に充填される充填構造を形成するステップをさらに含む請求項14に記載のアレイ基板の製造方法。
- 前記充填構造は、前記第1貫通孔及び前記光透過孔を完全に充填する請求項15に記載のアレイ基板の製造方法。
- 前記絶縁層に充填層を形成するステップをさらに含み、前記充填構造は、前記充填層の一部となる請求項15に記載のアレイ基板の製造方法。
- 前記充填層は、パッシベーション層、ゲート絶縁層、層間絶縁層及び平坦化層のうちのいずれか一つを含む請求項17に記載のアレイ基板の製造方法。
- 前記絶縁層の形成には、緩衝膜層、パッシベーション膜層、ゲート絶縁膜層及び層間絶縁膜層の少なくとも1つの形成を含む請求項14-18のいずれか1項に記載のアレイ基板の製造方法。
- 接続電極を形成し、前記緩衝膜層、前記パッシベーション膜層、前記ゲート絶縁膜層及び前記層間絶縁膜層の少なくとも1つを貫通している第3貫通孔を形成するステップをさらに含み、前記接続電極は、前記第3貫通孔を介して前記遮光層に接続される請求項19に記載のアレイ基板の製造方法。
- 前記ベース基板の前記遮光層から離れた側にイメージングデバイスを提供するステップをさらに含み、
前記イメージングデバイスは、前記ベース基板に垂直な方向に少なくとも部分的に前記光透過孔と重なる請求項13-20のいずれか1項に記載のアレイ基板の製造方法。
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EP3796385A4 (en) | 2022-04-20 |
EP3796385A1 (en) | 2021-03-24 |
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