JP7232901B2 - 半導体ウェハフィーチャを製作するための方法 - Google Patents

半導体ウェハフィーチャを製作するための方法 Download PDF

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Publication number
JP7232901B2
JP7232901B2 JP2021512670A JP2021512670A JP7232901B2 JP 7232901 B2 JP7232901 B2 JP 7232901B2 JP 2021512670 A JP2021512670 A JP 2021512670A JP 2021512670 A JP2021512670 A JP 2021512670A JP 7232901 B2 JP7232901 B2 JP 7232901B2
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semiconductor wafer
top surface
thin film
features
deposited
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JP2021536680A (ja
JP2021536680A5 (https=
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ファルハート クリー
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KLA Corp
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KLA Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2021512670A 2018-09-07 2019-09-05 半導体ウェハフィーチャを製作するための方法 Active JP7232901B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862728664P 2018-09-07 2018-09-07
US62/728,664 2018-09-07
US16/184,898 US10796969B2 (en) 2018-09-07 2018-11-08 System and method for fabricating semiconductor wafer features having controlled dimensions
US16/184,898 2018-11-08
PCT/US2019/049611 WO2020051258A1 (en) 2018-09-07 2019-09-05 System and method for fabricating semiconductor wafer features having controlled dimensions

Publications (3)

Publication Number Publication Date
JP2021536680A JP2021536680A (ja) 2021-12-27
JP2021536680A5 JP2021536680A5 (https=) 2022-09-09
JP7232901B2 true JP7232901B2 (ja) 2023-03-03

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US (1) US10796969B2 (https=)
EP (1) EP3847688A4 (https=)
JP (1) JP7232901B2 (https=)
KR (1) KR102550487B1 (https=)
CN (1) CN112714947B (https=)
TW (1) TWI797351B (https=)
WO (1) WO2020051258A1 (https=)

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Publication number Priority date Publication date Assignee Title
US11385187B1 (en) 2020-03-19 2022-07-12 Kla Corporation Method of fabricating particle size standards on substrates

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JP2008134103A (ja) 2006-11-27 2008-06-12 Hitachi High-Technologies Corp 校正用標準部材およびその作製方法、並びに校正用標準部材を用いた走査電子顕微鏡
US20120181665A1 (en) 2011-01-19 2012-07-19 International Business Machines Corporation Structure and method for hard mask removal on an soi substrate without using cmp process
US20140346612A1 (en) 2013-05-23 2014-11-27 International Business Machines Corporation Bulk semiconductor fins with self-aligned shallow trench isolation structures
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JP2017191938A (ja) 2016-04-12 2017-10-19 東京エレクトロン株式会社 自己整列スペーサ形成
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JP2006237620A (ja) 2005-02-25 2006-09-07 Infineon Technologies Ag 自立型ナノ構造部を作成する方法およびそのシステム
US20060281266A1 (en) 2005-06-09 2006-12-14 Wells David H Method and apparatus for adjusting feature size and position
US20070082437A1 (en) 2005-10-07 2007-04-12 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
JP2008134103A (ja) 2006-11-27 2008-06-12 Hitachi High-Technologies Corp 校正用標準部材およびその作製方法、並びに校正用標準部材を用いた走査電子顕微鏡
US20120181665A1 (en) 2011-01-19 2012-07-19 International Business Machines Corporation Structure and method for hard mask removal on an soi substrate without using cmp process
US20140346612A1 (en) 2013-05-23 2014-11-27 International Business Machines Corporation Bulk semiconductor fins with self-aligned shallow trench isolation structures
JP2016154234A (ja) 2015-02-20 2016-08-25 東京エレクトロン株式会社 サブ１０ｎｍパターニングを実現するための材料プロセシング
JP2017191938A (ja) 2016-04-12 2017-10-19 東京エレクトロン株式会社 自己整列スペーサ形成
JP2018085504A (ja) 2016-11-11 2018-05-31 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ Ａｌｄギャップ充填スペーサマスクを用いる自己整合型マルチパターニングプロセスフロー

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Publication number Publication date
KR20210043000A (ko) 2021-04-20
US20200083122A1 (en) 2020-03-12
CN112714947B (zh) 2022-09-16
JP2021536680A (ja) 2021-12-27
TW202016998A (zh) 2020-05-01
EP3847688A4 (en) 2022-06-15
KR102550487B1 (ko) 2023-06-30
WO2020051258A1 (en) 2020-03-12
US10796969B2 (en) 2020-10-06
CN112714947A (zh) 2021-04-27
TWI797351B (zh) 2023-04-01
EP3847688A1 (en) 2021-07-14

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