Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
  • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/27—Structural arrangements therefor
  • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6322—Formation by thermal treatments
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
  • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
  • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
  • H10P52/40—Chemomechanical polishing [CMP]
  • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/04—Apparatus for manufacture or treatment
  • H10P72/0402—Apparatus for fluid treatment
  • H10P72/0418—Apparatus for fluid treatment for etching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
  • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/27—Structural arrangements therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
  • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects

Definitions

• the present invention relates to fabrication of semiconductor wafers, and more particularly to processes for fabricating features of semiconductor wafers for use as dimensional standards.
• VSLI Standards, Inc. consists of a film stack of precisely controlled thicknesses (in the z dimension) that is diced out of a wafer and then mounted on its edge in order for the controlled z dimension to translate in an x/y dimension.
• the advantage of such processes is that it is easier to grow films of uniform and controlled thickness rather than to create uniform features in the x/y dimension using lithography.
• the disadvantage to this existing process is that it requires expensive and time-consuming bonding, dicing, polishing, and then etching processes, and even further the dice require remounting to another substrate with attention to orienting the features perpendicularly.
• a system and method are provided for fabricating semiconductor wafer features with controlled dimensions.
• a top surface of a semiconductor wafer is identified.
• a first portion of the top surface of the semiconductor wafer is then vertically etched to form a step down from a second portion of the top surface of the semiconductor wafer, the step comprised of a horizontal face and a vertical sidewall.
• a film is uniformly deposited across the horizontal face and the vertical sidewall of the step.
• the second portion of the top surface of the semiconductor wafer is vertically etched to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step.
• Figure 1A shows a block diagram illustrating one embodiment of a non-transitory computer-readable medium that includes program instructions executable on a computer system for performing one or more of the computer-implemented methods described herein.
• Figure IB is a schematic diagram illustrating a side view of one embodiment of an inspection system configured to detect defects on a fabricated device.
• Figure 2 shows a method for fabricating semiconductor wafer features with controlled dimensions, in accordance with an embodiment.
• Figure 3A illustrates a top surface of a semiconductor wafer, in accordance with an embodiment.
• Figure 3B illustrates the vertical etching of a first portion of the top surface of the semiconductor wafer of Figure 3A to form a step down from a second portion of the top surface of the semiconductor wafer, in accordance with an embodiment
• Figure 3C illustrates the uniform deposition of a film across a horizontal face and a vertical sidewall of the step of Figure 3B, in accordance with an embodiment.
• Figure 3D illustrates the vertical etching of the second portion of the top surface of the semiconductor wafer of Figure 3C to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step, in accordance with an embodiment.
• Figure 3E illustrates a 3-dimensional view of the feature of Figure 3D, in accordance with an embodiment.
• Figure 4 illustrates a system for fabricating semiconductor wafer features with controlled dimensions, in accordance with an embodiment.
• computer-readable medium 100 includes program instructions 102 executable on computer system 104.
• the program instructions 102 may be executed for the various purposes noted above, such as to detect defects, calibrate the inspection (e.g. metrology) system, or to perform measurement matching between different inspection (e.g. metrology) systems.
• Program instructions 102 may be stored on computer-readable medium 100.
• the computer-readable medium may be a storage medium such as a magnetic or optical disk, or a magnetic tape or any other suitable non-transitory computer-readable medium known in the ait.
• computer-readable medium 100 may be located within computer system 104.
• the program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others.
• the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (“MFC”), or other technologies or methodologies, as desired.
• MFC Microsoft Foundation Classes
• the computer system 104 may take various forms, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, Internet appliance, or other device.
• the term“computer system” may be broadly defined to encompass any device having one or more processors, which executes instructions from a memory medium.
• the computer system 104 may also include any suitable processor known in the art such as a parallel processor.
• the computer system 104 may include a computer platform with high speed processing and software, either as a standalone or a networked tool.
• the computer system 104 may be a subsystem of a larger system that also includes an inspection system 105, as shown in Figure IB.
• the system includes inspection system 105 configured to generate output for a feature fabricated on a wafer (or other device), which is configured in this embodiment as described further herein.
• the system also includes one or more computer systems.
• the one or more computer systems may be configured to perform the operations described above.
• the computer system(s) and the system may also be configured to perform any other operations described herein and may be further configured as described herein.
• one of the computer systems is part of an electronic design automation (EDA) tool, and the inspection system and another of the computer systems are not part of the EDA tool.
• EDA electronic design automation
• These computer systems may include, for example, the computer system 104 described above with reference to Figure 1A.
• one of the computer systems may be computer system 108 included in EDA tool 106.
• the EDA tool 106 and the computer system 108 included in such a tool may include any commercially available EDA tool.
• the inspection system 105 may be configured to generate the output for the feature on a wafer by scanning the wafer with light and detecting light from the wafer during the scanning.
• the inspection system 105 includes light source 120, which may include any suitable light source known in the art. Light from the light source may be directed to beam splitter 118, which may be configured to direct the light from the tight source to wafer 122.
• the light source 120 may be coupled to any other suitable elements (not shown) such as one or more condensing lenses, collimating lenses, relay lenses, objective lenses, apertures, spectral filters, polarizing components and the like. As shown in Figure IB, the light may be directed to the wafer 122 at a normal angle of incidence.
• the light may be directed to the wafer 122 at any suitable angle of incidence including near nonnal and oblique incidence.
• the light or multiple light beams may be directed to the wafer 122 at more than one angle of incidence sequentially or simultaneously.
• the inspection system 105 may be configured to scan the light over the wafer 122 in any suitable manner.
• Light from wafer 122 may be collected and detected by one or more channels of the inspection system 105 during scanning.
• light reflected from wafer 122 at angles relatively close to normal i.e., specular reflected light when the incidence is normal
• Lens 114 may include a refractive optical element as shown in Figure IB.
• lens 114 may include one or more refractive optical elements and/or one or more reflective optical elements.
• Light collected by lens 114 may be focused to detector 112.
• Detector 1 12 may include any suitable detector known in the art such as a charge coupled device (CCD) or another type of imaging detector.
• Detector 112 is configured to generate output that is responsive to the reflected light collected by lens 1 14.
• CCD charge coupled device
• lens 114 and detector 112 form one channel of the inspection system 105.
• This channel of the inspection system 105 may include any other suitable optical components (not shown) known in the art.
• the inspection system shown in Figure IB is configured to detect light specular reflected from the wafer 122, the inspection system 105 is configured as a (bright field) BF inspection system.
• Such an inspection system 105 may, however, also be configured for other types of wafer inspection.
• the inspection system shown in Figure IB may also include one or more other channels (not shown).
• the other channel(s) may include any of the optical components described herein such as a lens and a detector, configured as a scattered light channel.
• the lens and the detector may be further configured as described herein. In this manner, the inspection system 105 may also be configured for (dark field) DF inspection.
• the inspection system 105 may also include a computer system 110.
• the optical elements described above may form optical subsystem 111 of inspection subsystem 105, which may also include computer system 110 that is coupled to the optical subsystem 111.
• output generated by the detector(s) during scanning may be provided to computer system 110.
• the computer system 110 may be coupled to detector 112 (e.g., by one or more transmission media shown by the dashed line in Figure 1B, which may include any suitable transmission media known in the art) such that the computer system 110 may receive the output generated by the detector.
• the computer system 110 of the inspection system 105 may be configured to perform any of the operations described above.
• computer system 110 may be configured for systematic and stochastic characterization of pattern defects identified from the wafer, or for measuring features of the wafer.
• the one or more of the computer system(s) may be configured as a virtual inspector such as that described in U.S. Pat. No. 8,126,255 issued on Feb. 28, 2012 to Bhaskar et al., which is incorporated by reference as if fully set forth herein.
• the computer system 110 of the inspection system 105 may also be coupled to another computer system that is not part of the inspection system such as computer system 108, which may be included in another tool such as the EDA tool 106 described above such that computer system 110 can receive output generated by computer system 108, which may include a design generated by that computer system 108.
• the two computer systems may be effectively coupled by a shared computer-readable storage medium such as a fab database or may be coupled by a transmission medium such as that described above such that information may be transmitted between the two computer systems.
• Figure IB is provided herein to generally illustrate a configuration of an inspection system that may be utilized as described herein.
• the inspection system configuration described herein may be altered to optimize the performance of the inspection system as is normally performed when designing a commercial inspection system.
• the systems described herein may be implemented using an existing inspection system (e.g., by adding functionality described herein to an existing inspection system) such as the 29xx/28xx series of tools that are commercially available from KLA-Tencor.
• the methods described herein may be provided as optional functionality of the system (e.g., in addition to other functionality of the system).
• the system described herein may be designed“from scratch” to provide a completely new system.
• the inspection system 105 may be directly or indirectly coupled to a review system (not shown), such as the SEM review system disclosed in U.S. Patent No. 9,293,298.
• the SEM review system may be operable to review defects detected by the inspection system 105 for classification of the defects, which in turn can be used to train the inspection system 105 for better defect detection.
• Figure 2 shows a method 200 for fabricating semiconductor wafer features with controlled dimensions, in accordance with an embodiment.
• the method 200 may be carried out by any system having hardware components configured for fabricating semiconductor wafer features in the manner described.
• the method 200 may be carried out by the system 400 described below with reference to Figure 4.
• a top surface of a semiconductor wafer is identified.
• the semiconductor wafer may be any wafer comprised of semiconductor material. Accordingly, the top surface of the semiconductor wafer may be a substrate of semiconductor material.
• the semiconductor wafer may be a silicon wafer (i.e. comprised of silicon material).
• the top surface of the semiconductor wafer may be a silicon substrate, such as (110) silicon.
• the top surface of the semiconductor wafer may be a hard mask deposited on the substrate of the semiconductor wafer.
• the hard mask may be silicon nitride.
• a first portion of the top surface of the semiconductor wafer is vertically etched to form a step down from a second portion of the top surface of the semiconductor wafer.
• the step comprises a horizontal face (at a lower height than the second portion of the top surface of the semiconductor wafer) and a vertical sidewall (extending from the second portion of the top surface of the semiconductor wafer to the horizontal face).
• the vertical etching may include wet etching or dry etching.
• vertically etching the first portion of the top surface of the semiconductor wafer may include vertically etching through a first portion of the hard mask and a first portion of the substrate (silicon) of the semiconductor wafer on which the first portion of the hard mask is deposited.
• the first portion of the top surface of the semiconductor wafer may be vertically etched to any desired depth.
• a film is uniformly deposited across the horizontal face and the vertical sidewall of the step.
• the film may include thermal silicon oxide, for example.
• the film may include a vapor grown metal.
• the film may include any other film material as long as the second portion of the top surface of the semiconductor wafer can be vertically etched and thus removed from tlie film deposited on the vertical sidewall of the step, the reasons for which will be noted in further detail below.
• the film may be uniformly deposited by thermal oxidation, by chemical vapor deposition, or any other process capable of uniformly depositing the film across the horizontal face and the vertical sidewall of the step.
• a width of the film deposited on the surface of the step may be controlled.
• the film deposition process that is used may be controlled to deposit the film with a desired, and uniform, thickness.
• the second portion of the top surface of the semiconductor wafer is vertically etched to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step.
• vertically etching the second portion of the top surface of the semiconductor wafer may include partially removing, in a vertical direction, the second portion of the top surface of the semiconductor wafer.
• vertically etching the second portion of the top surface of the semiconductor wafer may include fully removing, in a vertical direction, the second portion of the top surface of the semiconductor wafer.
• the feature may be characterized by the width of the film deposited across the vertical sidewall of the step.
• a controlled dimension of the feature namely the width of the feature, may be provided by controlling the film deposition and etching processes described above.
• a plurality of features of the semiconductor wafer may be formed by repeating the method 200 for different locations of the top surface of the semiconductor wafer.
• the method 200 may also be performed simultaneously in the multiple different locations of the top surface of the semiconductor wafer.
• These features may vary in width, height, and shape, in a controlled manner, by controlling the film deposition and etching process to fabricate each feature.
• the method 200 may provide a well characterized and repeatable dimensional standard for semiconductor wafer features. This may allow these features to be used in the calibration of metrology tools that measure features of less than 100 nm as in the measurement of critical dimensions (CD) in the semiconductor industry, such as Critical Dimension Atomic Force Microscopy (CD-AFM) tools and Critical Dimension Scanning Electron Microscope (CD-SEM) tools. This may also allow these features to be used for measurement matching across different metrology tools, such as the tool matching method for SEMs disclosed in U.S. Patent No. 8,003,940.
• CD critical dimensions
• CD-AFM Critical Dimension Atomic Force Microscopy
• CD-SEM Critical Dimension Scanning Electron Microscope
• the method 200 may provide these controlled features with a simpler film stack than those from the prior art, by eliminating the need for wafer bonding, die polishing, or orienting and mounting to other substrates.
• the method 200 may further provide the ability to fabricate semiconductor wafer features of a variety of shapes and sizes, and using different film materials, as desired.
• Figure 3A illustrates a top surface of a semiconductor wafer, in accordance with an embodiment.
• the semiconductor wafer includes a hard mask 302 deposited on a silicon substrate 304.
• the hard mask 302 may be silicon nitride and the silicon substrate may be (110) silicon. It should be noted that the hard mask 302 may be deposited and patterned across an entire surface of the silicon substrate 304 or a partial surface of the silicon substrate 304, in different applications.
• Figure 3B illustrates the vertical etching of a first portion of the top surface of the semiconductor wafer of Figure 3 A to form a step down from a second portion of the top surface of the semiconductor wafer, in accordance with an embodiment.
• the step is comprised of a vertical sidewall (with a height equal to a depth of the vertical etching) and horizontal face (with a length equal to a length of the first portion of the top surface of the semiconductor wafer), as shown.
• the vertical etching can be performed using wet etching, such as by a wet anisotropic process (e.g. KOH) that is highly uniform and that results in straight lines and the vertical sidewall on (110) silicon wafers.
• the vertical etching can be performed using dry etching, such as by a reactive ion etch process (e.g. the Bosch process), which can vary the shape (in a controlled manner) of the resulting step.
• a reactive ion etch process e.g. the Bosch process
• chemical mechanical polishing of the step may be performed, in the context of Figure 3B. This may sharpen the angle of the step, to enable a sharper resulting feature, as described in more detail below.
• FIG. 3C illustrates the uniform deposition of a film across a horizontal face and a vertical sidewall of the step of Figure 3B, in accordance with an embodiment.
• a film 306 such as thermal silicon oxide
• Other film materials may also be used, other than thermal silicon oxide, such as vapor grown metals, as long as the second portion of the top surface of the semiconductor wafer can be etched from the film 306 (as described below with reference to Figure 3D).
• Use of vapor grown metals may be beneficial for creating the semiconductor wafer feature since a feature of this material may provide greater imaging contrast in certain inspection tools.
• the uniform deposition of the film 306 results in a consistent thickness (t) of the film 306 over the horizontal face and the vertical sidewall of the step.
• CMP chemical mechanical planarization
• Figure 3D illustrates the vertical etching of the second portion of the top surface of the semiconductor wafer of Figure 3C to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step, in accordance with an embodiment.
• the vertical etching may be performed on the second portion of the top surface of the semiconductor wafer (indicated in Figure 3B), including vertically through the hard mask 302 and a part of, the silicon substrate 304.
• the film 306 deposited across the vertical sidewall of the step is freed in part from the sidewall, and forms a vertical feature of the semiconductor wafer characterized by a width (t) of the film 306 and a height (h) corresponding to the depth of the vertical etching shown.
• Figure 3E illustrates a 3-dimensional view of the feature of Figure 3D, in accordance with an embodiment.
• the feature resulting from the fabrication process described with reference to Figures 3A-D is characterized by width (t) and height (h), and is formed from the film 306 material deposited on the silicon substrate 302.
• the semiconductor wafer feature can be used on the existing silicon substrate 302 after characterization with elipsometry (if transparent). It can also be diced and mounted on other substrates (wafers or masks) as a cost reduction measure (one processed wafer could result in thousands of usable features). Through elipsometry and/or cross-sectional transmission electron microscopy (TEM), the thickness of the film 306, and resulting width of the semiconductor wafer feature can be characterized to a traceable standard, such as the atomic lattice of single crystal silicon or the He-Ne laser wavelength. The feature can then be used for tool matching or calibration of CD-AFMs or CD-SEMs.
• TEM transmission electron microscopy
• Figure 4 illustrates a system 400 for fabricating semiconductor wafer features with controlled dimensions, in accordance with an embodiment.
• the system 400 may be implemented to carry out the method 200 of Figure 2 and/or the process described above with reference to Figures 3 A-3E. It should be noted that the system 400 is not limited to the components shown, but may include additional components as is understood in the relevant art. Further, the components of the system 400 are hardware components configured for fabricating semiconductor wafer features with controlled dimensions.
• the system 400 includes an etching component 402.
• the etching component vertically etches a first portion of a top surface of a semiconductor wafer to form a step down from a second portion of the top surface of the semiconductor wafer, where the step is comprised of a horizontal face and a vertical sidewall (see operation 204 of Figure 2 and/or Figure 3B).
• the system 400 also includes a film deposition component 404 that uniformly deposits a film across the horizontal face and the vertical sidewall of the step (see operation 206 of Figure 2 and/or Figure 3C).
• the etching component 402 further vertically etches the second portion of the top surface of the semiconductor wafer to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step (see operation 208 and/or Figure 3D).

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