CN112714947B - 用于制造具有受控尺寸的半导体晶片特征的系统及方法 - Google Patents

用于制造具有受控尺寸的半导体晶片特征的系统及方法 Download PDF

Info

Publication number
CN112714947B
CN112714947B CN201980060767.4A CN201980060767A CN112714947B CN 112714947 B CN112714947 B CN 112714947B CN 201980060767 A CN201980060767 A CN 201980060767A CN 112714947 B CN112714947 B CN 112714947B
Authority
CN
China
Prior art keywords
semiconductor wafer
top surface
film
features
vertical sidewalls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980060767.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN112714947A (zh
Inventor
F·奎利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KLA Corp
Original Assignee
KLA Tencor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KLA Tencor Corp filed Critical KLA Tencor Corp
Publication of CN112714947A publication Critical patent/CN112714947A/zh
Application granted granted Critical
Publication of CN112714947B publication Critical patent/CN112714947B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
CN201980060767.4A 2018-09-07 2019-09-05 用于制造具有受控尺寸的半导体晶片特征的系统及方法 Active CN112714947B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862728664P 2018-09-07 2018-09-07
US62/728,664 2018-09-07
US16/184,898 US10796969B2 (en) 2018-09-07 2018-11-08 System and method for fabricating semiconductor wafer features having controlled dimensions
US16/184,898 2018-11-08
PCT/US2019/049611 WO2020051258A1 (en) 2018-09-07 2019-09-05 System and method for fabricating semiconductor wafer features having controlled dimensions

Publications (2)

Publication Number Publication Date
CN112714947A CN112714947A (zh) 2021-04-27
CN112714947B true CN112714947B (zh) 2022-09-16

Family

ID=69720071

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980060767.4A Active CN112714947B (zh) 2018-09-07 2019-09-05 用于制造具有受控尺寸的半导体晶片特征的系统及方法

Country Status (7)

Country Link
US (1) US10796969B2 (https=)
EP (1) EP3847688A4 (https=)
JP (1) JP7232901B2 (https=)
KR (1) KR102550487B1 (https=)
CN (1) CN112714947B (https=)
TW (1) TWI797351B (https=)
WO (1) WO2020051258A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11385187B1 (en) 2020-03-19 2022-07-12 Kla Corporation Method of fabricating particle size standards on substrates

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339000B1 (en) * 1998-09-25 2002-01-15 Conexant Systems, Inc. Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures
JP2002118083A (ja) * 2000-10-05 2002-04-19 Hitachi Ltd 半導体集積回路装置の製造方法
US6602759B2 (en) * 2000-12-07 2003-08-05 International Business Machines Corporation Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
KR20020071063A (ko) * 2001-03-02 2002-09-12 삼성전자 주식회사 덴트 없는 트렌치 격리 구조 및 그 형성 방법
JP3597495B2 (ja) * 2001-08-31 2004-12-08 株式会社ルネサステクノロジ 半導体集積回路装置
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7052921B1 (en) * 2004-09-03 2006-05-30 Advanced Micro Devices, Inc. System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process
US8384148B2 (en) * 2004-12-22 2013-02-26 Micron Technology, Inc. Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
US7008853B1 (en) 2005-02-25 2006-03-07 Infineon Technologies, Ag Method and system for fabricating free-standing nanostructures
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7638381B2 (en) 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US7271063B2 (en) * 2005-10-13 2007-09-18 Elite Semiconductor Memory Technology, Inc. Method of forming FLASH cell array having reduced word line pitch
JP2007109966A (ja) * 2005-10-14 2007-04-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4638800B2 (ja) 2005-10-27 2011-02-23 株式会社日立ハイテクノロジーズ 走査電子顕微鏡装置における機差管理システムおよびその方法
US8129242B2 (en) * 2006-05-12 2012-03-06 Macronix International Co., Ltd. Method of manufacturing a memory device
JP4857090B2 (ja) 2006-11-27 2012-01-18 株式会社日立ハイテクノロジーズ 校正用標準部材およびその作製方法、並びに校正用標準部材を用いた走査電子顕微鏡
US8021563B2 (en) * 2007-03-23 2011-09-20 Alpha & Omega Semiconductor, Ltd Etch depth determination for SGT technology
US8126255B2 (en) 2007-09-20 2012-02-28 Kla-Tencor Corp. Systems and methods for creating persistent data for a wafer and for using persistent data for inspection-related functions
US7824983B2 (en) 2008-06-02 2010-11-02 Micron Technology, Inc. Methods of providing electrical isolation in semiconductor structures
US8853091B2 (en) * 2009-01-16 2014-10-07 Microchip Technology Incorporated Method for manufacturing a semiconductor die with multiple depth shallow trench isolation
KR101186043B1 (ko) 2009-06-22 2012-09-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8232179B2 (en) * 2009-10-01 2012-07-31 International Business Machines Corporation Method to improve wet etch budget in FEOL integration
US8293625B2 (en) 2011-01-19 2012-10-23 International Business Machines Corporation Structure and method for hard mask removal on an SOI substrate without using CMP process
JP5862492B2 (ja) * 2012-07-09 2016-02-16 信越半導体株式会社 半導体ウェーハの評価方法及び製造方法
KR20140131681A (ko) 2013-05-06 2014-11-14 코닝정밀소재 주식회사 전력 소자용 기판, 그 제조방법 및 이를 포함하는 전력 소자
US9087869B2 (en) 2013-05-23 2015-07-21 International Business Machines Corporation Bulk semiconductor fins with self-aligned shallow trench isolation structures
US9293298B2 (en) 2013-12-23 2016-03-22 Kla-Tencor Corp. Defect discovery and inspection sensitivity optimization using automated classification of corresponding electron beam images
US9443731B1 (en) 2015-02-20 2016-09-13 Tokyo Electron Limited Material processing to achieve sub-10nm patterning
US20170059758A1 (en) * 2015-08-24 2017-03-02 Moxtek, Inc. Small-Pitch Wire Grid Polarizer
US10483109B2 (en) 2016-04-12 2019-11-19 Tokyo Electron Limited Self-aligned spacer formation
US10276674B2 (en) * 2016-06-28 2019-04-30 Globalfoundries Inc. Method of forming a gate contact structure and source/drain contact structure for a semiconductor device
EP3312882B1 (en) * 2016-10-20 2021-09-15 IMEC vzw A method of patterning a target layer
US10832908B2 (en) 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10431663B2 (en) * 2018-01-10 2019-10-01 Globalfoundries Inc. Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure

Also Published As

Publication number Publication date
KR20210043000A (ko) 2021-04-20
US20200083122A1 (en) 2020-03-12
JP2021536680A (ja) 2021-12-27
TW202016998A (zh) 2020-05-01
EP3847688A4 (en) 2022-06-15
KR102550487B1 (ko) 2023-06-30
WO2020051258A1 (en) 2020-03-12
JP7232901B2 (ja) 2023-03-03
US10796969B2 (en) 2020-10-06
CN112714947A (zh) 2021-04-27
TWI797351B (zh) 2023-04-01
EP3847688A1 (en) 2021-07-14

Similar Documents

Publication Publication Date Title
CN108463877B (zh) 用于扩展的红外线光谱椭偏测量的系统及方法
CN105914159B (zh) 利用已知形状薄片自动s/tem采集和计量的图形匹配
JP6356397B2 (ja) 基板の外位置分析システムおよび方法
TW201828382A (zh) 用於製程控制之量測系統及方法
KR20190049890A (ko) 반도체 웨이퍼 검사를 위한 결함 마킹
CN108603830B (zh) 具有改进的光斑大小能力的单波长椭圆偏振测量法
JP2010507783A (ja) Ｓ／ｔｅｍのサンプルを作成する方法およびサンプル構造
CN110326094B (zh) 用于测量三维半导体晶片上的掩埋缺陷的三维校准结构及方法
TWI299536B (en) In-situ critical dimension measurnment
CN114450581B (zh) 激光表面检查装置的坐标位置识别精度校准方法及半导体晶圆的评价方法
CN112714947B (zh) 用于制造具有受控尺寸的半导体晶片特征的系统及方法
JP4400331B2 (ja) ウエーハの形状評価方法及び管理方法
JP7457896B2 (ja) 加工変質層の評価方法及び評価システム
JP6182677B2 (ja) ウエハーの損傷深さを測定する方法
US5443684A (en) Method for measuring thin film thickness
Yang Metrology and Inspection Equipment
US11385187B1 (en) Method of fabricating particle size standards on substrates
TW202601056A (zh) 影像模型輔助計量學
TW202614255A (zh) 關鍵尺寸測量中之線性之評估
US8384029B2 (en) Cross-section systems and methods
JP2007171384A (ja) フォトマスクの白欠陥修正方法及び装置
KR20150062208A (ko) 사파이어 기판의 결함 검사 방법 및 투명 기판의 결함 검사 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant