TWI797351B - 用於製造具有控制尺寸之半導體晶圓特徵之系統及方法 - Google Patents

用於製造具有控制尺寸之半導體晶圓特徵之系統及方法 Download PDF

Info

Publication number
TWI797351B
TWI797351B TW108123050A TW108123050A TWI797351B TW I797351 B TWI797351 B TW I797351B TW 108123050 A TW108123050 A TW 108123050A TW 108123050 A TW108123050 A TW 108123050A TW I797351 B TWI797351 B TW I797351B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
top surface
film
deposited
etching
Prior art date
Application number
TW108123050A
Other languages
English (en)
Other versions
TW202016998A (zh
Inventor
伐漢特 A 奎利
Original Assignee
美商克萊譚克公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商克萊譚克公司 filed Critical 美商克萊譚克公司
Publication of TW202016998A publication Critical patent/TW202016998A/zh
Application granted granted Critical
Publication of TWI797351B publication Critical patent/TWI797351B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明提供一種用於製造具有控制尺寸之半導體晶圓特徵之系統及方法。在使用中,識別一半導體晶圓之一頂表面。接著,垂直地蝕刻該半導體晶圓之該頂表面之一第一部分,以形成從該半導體晶圓之該頂表面之一第二部分向下之一階狀部,該階狀部包括一水平面及一垂直側壁。另外,跨該階狀部之該水平面及該垂直側壁均勻地沈積一膜。此外,垂直地蝕刻該半導體晶圓之該頂表面之該第二部分,以曝露跨該階狀部之該垂直側壁沈積之該膜作為該半導體晶圓之一特徵。

Description

用於製造具有控制尺寸之半導體晶圓特徵之系統及方法
本發明係關於半導體晶圓之製造,且更特定言之係關於用於製造用作尺寸標準之半導體晶圓之特徵之程序。
用於製造半導體晶圓之現有程序涉及根據定義尺寸製造半導體晶圓之特徵。為產生如預期般運作之半導體晶圓,可期望將所製造半導體晶圓上之實際特徵尺寸儘可能緊密地對準至定義尺寸。此外,在一些特定應用中,半導體晶圓經製造用於計量工具之校準或匹配,此需要此等所製造半導體晶圓上之實際特徵尺寸在定義尺寸之一可容許容限內。因此,需要提供具有控制尺寸之晶圓特徵之半導體晶圓製程。
由VSLI Standards,Inc.標準製成之一個現有製程由具有精確控制厚度(在z維度上)之一膜堆疊構成,該膜堆疊從一晶圓切割且接著安裝於其邊緣上以便使控制z維度在一x/y維度上平移。此等程序之優點係生長具有均勻且控制厚度之膜比使用微影術在x/y維度上產生均勻特徵更容易。然而,此現有程序之缺點係其需要昂貴且耗時之接合、切割、拋光及接著蝕刻程序,且更進一步,切割需要至另一基板之重新安裝且注意垂 直地定向特徵。
因此,需要解決與先前技術相關聯之此等及/或其他問題。
本發明提供一種用於製造具有控制尺寸之半導體晶圓特徵之系統及方法。在使用中,識別一半導體晶圓之一頂表面。接著,垂直地蝕刻該半導體晶圓之該頂表面之一第一部分以形成從該半導體晶圓之該頂表面之一第二部分向下之一階狀部,該階狀部包括一水平面及一垂直側壁。另外,跨該階狀部之該水平面及該垂直側壁均勻地沈積一膜。此外,垂直地蝕刻該半導體晶圓之該頂表面之該第二部分以曝露跨該階狀部之該垂直側壁沈積之該膜作為該半導體晶圓之一特徵。
100:電腦可讀媒體
102:程式指令
104:電腦系統
105:檢測系統
106:電子設計自動化(EDA)工具
108:電腦系統
110:電腦系統
111:光學子系統
112:偵測器
114:透鏡
118:光束分離器
120:光源
122:晶圓
200:方法
202:操作
204:操作
206:操作
208:操作
302:硬遮罩
304:矽基板
306:膜
400:系統
402:蝕刻組件
404:膜沈積組件
圖1A係繪示包含可在一電腦系統上執行以用於執行本文中描述之電腦實施方法之一或多者之程式指令之一非暫時性電腦可讀媒體之一項實施例之一方塊圖。
圖1B係繪示經組態以偵測一所製造裝置上之缺陷之一檢測系統之一項實施例之一側視圖之一示意圖。
圖2展示根據一實施例之用於製造具有控制尺寸之半導體晶圓特徵之一方法。
圖3A繪示根據一實施例之一半導體晶圓之一頂表面。
圖3B繪示根據一實施例垂直地蝕刻圖3A之半導體晶圓之頂表面之一第一部分以形成從半導體晶圓之頂表面之一第二部分向下之一階狀部。
圖3C繪示根據一實施例跨圖3B之階狀部之一水平面及一 垂直側壁均勻地沈積一膜。
圖3D繪示根據一實施例垂直地蝕刻圖3C之半導體晶圓之頂表面之第二部分以曝露跨階狀部之垂直側壁沈積之膜作為半導體晶圓之一特徵。
圖3E繪示根據一實施例之圖3D之特徵之一三維視圖。
圖4繪示根據一實施例之用於製造具有控制尺寸之半導體晶圓特徵之一系統。
相關申請案
本申請案主張2018年9月7日申請之美國臨時專利申請案第62/728,664號的權利,該案之全部內容係以引用的方式併入本文中。
以下描述揭示一種用於製造具有控制尺寸之半導體晶圓特徵之系統及方法。一旦製造晶圓,其便可出於各種目的使用一檢測系統檢測,諸如偵測缺陷、校準檢測(例如,計量)系統或執行不同檢測(例如,計量)系統之間的量測匹配。圖1A至圖1B描述一檢測系統之各種實施例。
如圖1A中展示,電腦可讀媒體100包含可在電腦系統104上執行之程式指令102。程式指令102可經執行用於上文提及之各種目的,諸如偵測缺陷、校準檢測(例如,計量)系統或執行不同檢測(例如,計量)系統之間的量測匹配。
程式指令102可儲存於電腦可讀媒體100上。電腦可讀媒體可為一儲存媒體,諸如一磁碟或光碟或一磁帶或此項技術中已知的任何其他適合非暫時性電腦可讀媒體。作為一選項,電腦可讀媒體100可定位於電腦系統104內。
程式指令可以各種方式之任一者實施,包含基於程序之技術、基於組件之技術及/或物件導向技術等。例如,程式指令可視需要使用ActiveX控制項、C++物件、JavaBeans、微軟基礎類別(「MFC」)或其他技術或方法實施。
電腦系統104可採用各種形式,包含一個人電腦系統、影像電腦、主機電腦系統、工作站、網路設備、網際網路設備,或其他裝置。一般言之,術語「電腦系統」可係廣泛地定義為涵蓋具有執行來自一記憶體媒體之指令之一或多個處理器之任何裝置。電腦系統104亦可包含此項技術中已知的任何適合處理器,諸如一平行處理器。另外,電腦系統104可包含具有高速處理及軟體之一電腦平台(作為一獨立或一網路化工具)。
在一項實施例中,電腦系統104可為亦包含一檢測系統105之一較大系統之一子系統,如圖1B中展示。系統包含經組態以針對在一晶圓(或其他裝置)上製造之一特徵產生輸出之檢測系統105,其在此實施例中係如本文中進一步描述般組態。系統亦包含一或多個電腦系統。一或多個電腦系統可經組態以執行上文描述之操作。(若干)電腦系統及系統亦可經組態以執行本文中描述之任何其他操作,且可如本文中描述般進一步組態。
在圖1B中展示之實施例中,電腦系統之一者係一電子設計自動化(EDA)工具之部分,且檢測系統及電腦系統之另一者並非EDA工具之部分。此等電腦系統可包含(例如)上文參考圖1A所描述之電腦系統104。例如,如圖1B中展示,電腦系統之一者可為被包含於EDA工具106中之電腦系統108。EDA工具106及被包含於此一工具中之電腦系統108可 包含任何市售EDA工具。
檢測系統105可經組態以藉由使用光來掃描一晶圓,且在掃描期間偵測來自晶圓之光而針對晶圓上之特徵產生輸出。例如,如圖1B中展示,檢測系統105包含光源120,光源120可包含此項技術中已知的任何適合光源。可將來自光源之光引導至光束分離器118,光束分離器118可經組態以將來自光源之光引導至晶圓122。光源120可被耦合至任何其他適合元件(未展示),諸如一或多個聚光透鏡、準直透鏡、中繼透鏡、物鏡、光圈、光譜濾波器、偏光組件,及類似物。如圖1B中展示,可依一法向入射角將光引導至晶圓122。然而,可依任何適合入射角(包含近法向入射及傾斜入射)將光引導至晶圓122。另外,可依序或同時依一個以上入射角將光或多個光束引導至晶圓122。檢測系統105可經組態以依任何適合方式使光掃描遍及晶圓122。
在掃描期間可藉由檢測系統105之一或多個通道收集及偵測來自晶圓122之光。例如,依相對接近於法線之角度從晶圓122反射之光(即,在入射係法向時之鏡面反射光)可穿過光束分離器118至透鏡114。透鏡114可包含一折射光學元件,如圖1B中展示。另外,透鏡114可包含一或多個折射光學元件及/或一或多個反射光學元件。可將由透鏡114收集之光聚焦至偵測器112。偵測器112可包含此項技術中已知的任何適合偵測器,諸如一電荷耦合裝置(CCD)或另一類型之成像偵測器。偵測器112經組態以產生回應於由透鏡114收集之反射光之輸出。因此,透鏡114及偵測器112形成檢測系統105之一個通道。檢測系統105之此通道可包含此項技術中已知的任何其他適合光學組件(未展示)。
由於圖1B中展示之檢測系統經組態以偵測從晶圓122鏡面 反射之光,所以檢測系統105經組態為一(明場)BF檢測系統。然而,此一檢測系統105亦可經組態用於其他類型之晶圓檢測。例如,圖1B中展示之檢測系統亦可包含一或多個其他通道(未展示)。(若干)其他通道可包含本文中描述之光學組件之任一者,諸如組態為一散射光通道之一透鏡及一偵測器。透鏡及偵測器可如本文中描述般進一步組態。以此方式,檢測系統105亦可經組態用於(暗場)DF檢測。
檢測系統105亦可包含一電腦系統110。例如,上文描述之光學元件可形成檢測子系統105之光學子系統111,檢測子系統105亦可包含耦合至光學子系統111之電腦系統110。以此方式,可將在掃描期間由(若干)偵測器產生之輸出提供至電腦系統110。例如,電腦系統110可耦合至偵測器112(例如,藉由由圖1B中之虛線展示之一或多個傳輸媒體,其可包含此項技術中已知的任何適合傳輸媒體),使得電腦系統110可接收由偵測器產生之輸出。
檢測系統105之電腦系統110可經組態以執行上文描述之操作之任一者。例如,電腦系統110可經組態用於從晶圓識別之圖案缺陷之系統及隨機特性化或用於量測晶圓之特徵。另外,(若干)電腦系統之一或多者可組態為一虛擬檢測器,諸如2012年2月28日發佈之Bhaskar等人之美國專利第8,126,255號中描述之虛擬檢測器,該案以宛如全文闡述引用的方式併入本文中。
檢測系統105之電腦系統110亦可耦合至並非檢測系統之部分之另一電腦系統(諸如電腦系統108,其可包含於諸如上文描述之EDA工具106之另一工具中),使得電腦系統110可接收由電腦系統108產生之輸出,該輸出可包含由該電腦系統108產生之一設計。例如,兩個電腦系統 可由一共用電腦可讀儲存媒體(諸如一製作資料庫(fab database))有效地耦合或可由一傳輸媒體(諸如上文描述之傳輸媒體)耦合,使得可在兩個電腦系統之間傳輸資訊。
應注意,本文中提供圖1B以大體上繪示可如本文中描述般利用之一檢測系統之一組態。顯然,如在設計一商業檢測系統時通常所執行般,可更改本文中描述之檢測系統組態以最佳化檢測系統之效能。另外,本文中描述之系統可使用諸如購自KLA-Tencor之29xx/28xx系列工具之一現有檢測系統(例如,藉由將本文中描述之功能性添加至一現有檢測系統)實施。對於一些此等系統,本文中描述之方法可提供為系統之選用功能性(例如,除系統之其他功能性以外)。替代地,可「從頭開始」設計本文中描述之系統以提供一全新系統。
在一進一步實施例中,檢測系統105可直接或間接耦合至一檢視系統(未展示),諸如美國專利第9,293,298號中揭示之SEM檢視系統。SEM檢視系統可操作以檢視由檢測系統105偵測之缺陷以對缺陷分類,該等缺陷繼而可用於訓練檢測系統105以進行更佳缺陷偵測。
圖2展示根據一實施例之用於製造具有控制尺寸之半導體晶圓特徵之一方法200。方法200可由具有經組態用於以所描述之方式製造半導體晶圓特徵之硬體組件之任何系統實行。例如,方法200可由下文參考圖4描述之系統400實行。
如操作202中展示,識別一半導體晶圓之一頂表面。半導體晶圓可為包括半導體材料之任何晶圓。因此,半導體晶圓之頂表面可為半導體材料之一基板。
例如,在一項實施例中,半導體晶圓可為一矽晶圓(即,包 括矽材料)。在此實施例中,半導體晶圓之頂表面可為一矽基板,諸如(110)矽。在另一實施例中,半導體晶圓之頂表面可為沈積於半導體晶圓之基板上之一硬遮罩。在此實施例中,硬遮罩可為氮化矽。
如操作204中展示,垂直地蝕刻半導體晶圓之頂表面之一第一部分以形成從半導體晶圓之頂表面之一第二部分向下之一階狀部。由於垂直蝕刻,階狀部包括一水平面(在低於半導體晶圓之頂表面之第二部分之一高度處)及一垂直側壁(從半導體晶圓之頂表面之第二部分延伸至水平面)。垂直蝕刻可包含乾式蝕刻或濕式蝕刻。
在上文描述之實施例中(其中半導體晶圓之頂表面係沈積於半導體晶圓之基板上之一硬遮罩),垂直地蝕刻半導體晶圓之頂表面之第一部分可包含垂直地蝕刻穿過硬遮罩之一第一部分及硬遮罩之第一部分經沈積於其上之半導體晶圓之基板(矽)之一第一部分。在任何情況中,應注意,可將半導體晶圓之頂表面之第一部分垂直地蝕刻至任何所要深度。
另外,如操作206中展示,跨階狀部之水平面及垂直側壁均勻地沈積一膜。例如,膜可包含熱氧化矽。作為另一實例,膜可包含一氣相生長金屬。然而,當然,膜可包含任何其他膜材料,只要半導體晶圓之頂表面之第二部分可經垂直地蝕刻且因此從經沈積於階狀部之垂直側壁上之膜移除即可,此原因將在下文更詳細提及。
為此,在各種實施例中,可藉由熱氧化、化學氣相沈積或能夠跨階狀部之水平面及垂直側壁均勻地沈積膜之任何其他程序來均勻地沈積膜。藉由跨階狀部之水平面及垂直側壁均勻地沈積膜,可控制沈積於階狀部之表面上之膜之一寬度。例如,可控制所使用之膜沈積程序,以依一所要與均勻厚度來沈積膜。
此外,如操作208中展示,垂直地蝕刻半導體晶圓之頂表面之第二部分,以曝露跨階狀部之垂直側壁沈積之膜作為半導體晶圓之一特徵。在一項實施例中,垂直地蝕刻半導體晶圓之頂表面之第二部分可包含在一垂直方向上部分移除半導體晶圓之頂表面之第二部分。在另一實施例中,垂直地蝕刻半導體晶圓之頂表面之第二部分可包含在一垂直方向上完全移除半導體晶圓之頂表面之第二部分。藉由垂直地蝕刻半導體晶圓之頂表面之第二部分以曝露跨階狀部之垂直側壁沈積之膜作為一特徵,可控制該特徵之一高度。
因此,可藉由跨階狀部之垂直側壁沈積之膜之寬度特性化該特徵。以此方式,可藉由控制上文描述之膜沈積及蝕刻程序而提供特徵之一控制尺寸(即,特徵之寬度)。
應注意,可藉由針對半導體晶圓之頂表面之不同位置重複方法200而形成半導體晶圓之複數個特徵。方法200亦可在半導體晶圓之頂表面之多個不同位置中同時執行。藉由控制膜沈積及蝕刻程序以製造各特徵,此等特徵可以一控制方式在寬度、高度及形狀上變化。
以上文描述之方式,方法200可為半導體晶圓特徵提供一良好特性化且可重複之尺寸標準。此可容許此等特徵用於校準如在半導體工業中之臨界尺寸(CD)量測中量測小於100nm之特徵之計量工具,諸如臨界尺寸原子力顯微鏡(CD-AFM)工具及臨界尺寸掃描電子顯微鏡(CD-SEM)工具。此亦可容許此等特徵用於跨不同計量工具之量測匹配,諸如美國專利第8,003,940號中揭示之SEM之工具匹配方法。
另外,方法200可藉由消除對晶圓接合、晶粒拋光或至其他基板之定向及安裝之需求而為此等控制特徵提供比來自先前技術之特徵 更簡單之一膜堆疊。方法200可進一步提供視需要製造具有各種形狀及大小且使用不同膜材料之半導體晶圓特徵之能力。
現在將闡述關於各種選用架構及用途之更多闡釋性資訊,其中根據使用者需求可實施或可不實施前述方法。應注意,以下資訊係出於闡釋性目的而闡述且不應以任何方式解釋為限制性的。在排除或不排除所描述之其他特徵的情況下可視情況併入以下特徵之任一者。
圖3A繪示根據一實施例之一半導體晶圓之一頂表面。如展示,半導體晶圓包含沈積於一矽基板304上之一硬遮罩302。硬遮罩302可為氮化矽且矽基板可為(110)矽。應注意,在不同應用中,可跨矽基板304之一整個表面或矽基板304之一部分表面沈積且圖案化硬遮罩302。
圖3B繪示根據一實施例垂直地蝕刻圖3A之半導體晶圓之頂表面之一第一部分以形成從半導體晶圓之頂表面之一第二部分向下之一階狀部。階狀部包括一垂直側壁(具有等於垂直蝕刻之一深度之一高度)及水平面(具有等於半導體晶圓之頂表面之第一部分之一長度之一長度),如展示。垂直蝕刻可使用濕式蝕刻執行,諸如藉由高度均勻且導致(110)矽晶圓上之直線及垂直側壁之一濕各向異性程序(例如,KOH)。作為另一選項,垂直蝕刻可使用乾式蝕刻執行,諸如藉由可改變所得階狀部之形狀(以一控制方式)之一反應性離子蝕刻程序(例如,波希(Bosch)程序)。
作為一選項,在圖3B之內容脈絡中,可執行階狀部之化學機械拋光。此可使階狀部之角度銳化以實現一更尖銳所得特徵,如下文更詳細描述。
圖3C繪示根據一實施例跨圖3B之階狀部之一水平面及一垂直側壁均勻地沈積一膜。如展示,跨階狀部之水平面及垂直側壁均勻地 沈積(生長)一膜306(諸如熱氧化矽)。除熱氧化矽以外,亦可使用其他膜材料,諸如氣相生長金屬,只要半導體晶圓之頂表面之第二部分可從膜306蝕刻即可(如下文參考圖3D描述)。氣相生長金屬之使用可有益於產生半導體晶圓特徵,因為此材料之一特徵可在某些檢測工具中提供較大成像對比度。在任何情況中,膜306之均勻沈積導致膜306在階狀部之水平面及垂直側壁上方之一致厚度(t)。
作為一選項,在均勻地沈積膜306之後,可對半導體晶圓之頂表面之第二部分執行化學機械平坦化(CMP)。此可移除硬遮罩302且減小階狀部高度。重要的是,此可移除矽基板304、硬遮罩302及膜306之接面處之界面非化學計量組合物,否則其等無法經由圖3D中描述之垂直蝕刻蝕刻至一乾淨特徵中。
圖3D繪示根據一實施例垂直地蝕刻圖3C之半導體晶圓之頂表面之第二部分以曝露跨階狀部之垂直側壁沈積之膜作為半導體晶圓之一特徵。在一項實施例中,可對半導體晶圓之頂表面之第二部分執行垂直蝕刻(在圖3B中指示),包含垂直穿過硬遮罩302及矽基板304之一部分。因此,跨階狀部之垂直側壁沈積之膜306部分從側壁釋放,且形成半導體晶圓之一垂直特徵,其藉由膜306之一寬度(t)及對應於所展示垂直蝕刻之深度之一高度(h)特性化。
圖3E繪示根據一實施例之圖3D之特徵之一三維視圖。如展示,由參考圖3A至圖3D描述之製程導致之特徵藉由寬度(t)及高度(h)特性化且由沈積於矽基板304上之膜306材料形成。
在使用橢圓偏光術特性化之後(若透明),可在現有矽基板304上使用半導體晶圓特徵。其亦可經切割且安裝於其他基板(晶圓或遮 罩)上以作為一成本降低措施(一個經處理晶圓可導致數千個可用特徵)。透過橢圓偏光術及/或橫截面透射電子顯微鏡(TEM),可將膜306之厚度及半導體晶圓特徵之所得寬度特性化為一可追蹤標準,諸如單晶矽之原子晶格或He-Ne雷射波長。接著,特徵可用於CD-AFM或CD-SEM之工具匹配或校準。
圖4繪示根據一實施例之用於製造具有控制尺寸之半導體晶圓特徵之一系統400。系統400可經實施以實行圖2之方法200及/或上文參考圖3A至圖3E描述之程序。應注意,系統400不限於所展示之組件,而可包含如相關技術中所理解之額外組件。此外,系統400之組件係經組態用於製造具有控制尺寸之半導體晶圓特徵之硬體組件。
如展示,系統400包含一蝕刻組件402。蝕刻組件垂直地蝕刻一半導體晶圓之一頂表面之一第一部分以形成從半導體晶圓之頂表面之一第二部分向下之一階狀部,其中階狀部包括一水平面及一垂直側壁(參見圖2之操作204及/或圖3B)。系統400亦包含一膜沈積組件404,其跨階狀部之水平面及垂直側壁均勻地沈積一膜(參見圖2之操作206及/或圖3C)。蝕刻組件402進一步垂直地蝕刻半導體晶圓之頂表面之第二部分以曝露跨階狀部之垂直側壁沈積之膜作為半導體晶圓之一特徵(參見操作208及/或圖3D)。
雖然上文已描述各種實施例,但應理解其等僅藉由實例呈現且非限制性。因此,一較佳實施例之範圍及範疇不應受上述例示性實施例之任一者限制,而應僅根據下列發明申請專利範圍及其等效物定義。
200:方法
202:操作
204:操作
206:操作
208:操作

Claims (11)

  1. 一種用於製造具有控制尺寸之半導體晶圓特徵之方法,其包括:識別一半導體晶圓之一頂表面,其中該半導體晶圓之該頂表面係經沈積於該半導體晶圓之一基板上之一硬遮罩;垂直地蝕刻該半導體晶圓之該頂表面之一第一部分至一選擇深度以形成從該半導體晶圓之該頂表面之一第二部分向下之一階狀部,該階狀部包括:一水平面,其在低於該半導體晶圓之該頂表面之該第二部分之一高度處;及一垂直側壁,其從該半導體晶圓之該頂表面之該第二部分延伸至該水平面;執行該階狀部之化學機械拋光;在執行該階狀部之化學機械拋光之後,跨該階狀部之該水平面及該垂直側壁均勻地沈積一選擇厚度之一膜;在跨該階狀部之該水平面及該垂直側壁均勻地沈積該膜之後,對該半導體晶圓之該頂表面之該第二部分執行化學機械平坦化(CMP)以減小該階狀部之一高度;對該半導體晶圓之該頂表面之該第二部分執行化學機械平坦化(CMP)以減小該階狀部之一高度之後,藉由垂直地蝕刻穿過該硬遮罩之一第一部分及該硬遮罩之該第一部分經沈積於其上之該半導體晶圓之該基板之一第一部分來從該膜垂直地蝕刻該半導體晶圓之該頂表面之該第二部分至一選擇深度,以曝露跨該階狀部之該垂直側壁沈積之該膜作為該半導體 晶圓之一特徵,其中該特徵的尺寸是根據該膜被沈積的該選擇厚度以及該半導體晶圓之該頂表面之該第二部分被垂直地蝕刻的該選擇深度所控制。
  2. 如請求項1之方法,其中該半導體晶圓係一矽晶圓。
  3. 如請求項1之方法,其中該半導體晶圓之該基板係一矽基板。
  4. 如請求項1之方法,其中該硬遮罩係氮化矽。
  5. 如請求項1之方法,其中使用濕式蝕刻垂直地蝕刻該半導體晶圓之該頂表面之該第一部分。
  6. 如請求項1之方法,其中使用乾式蝕刻垂直地蝕刻該半導體晶圓之該頂表面之該第一部分。
  7. 如請求項1之方法,其中藉由熱氧化,跨該階狀部之該垂直側壁,均勻地沈積該選擇厚度之該膜。
  8. 如請求項1之方法,其中藉由化學氣相沈積,跨該階狀部之該垂直側壁,以該控制寬度均勻地沈積該膜。
  9. 如請求項1之方法,其中該特徵係用於一計量工具之校準。
  10. 如請求項1之方法,其中該特徵係用於複數個計量工具中之量測匹配。
  11. 如請求項1之方法,其中藉由針對該半導體晶圓之該頂表面之不同位置重複該半導體晶圓之該頂表面之該第一部分之該垂直蝕刻、該膜之該均勻沈積及該半導體晶圓之該頂表面之該第二部分之該垂直蝕刻來形成該半導體晶圓之複數個特徵。
TW108123050A 2018-09-07 2019-07-01 用於製造具有控制尺寸之半導體晶圓特徵之系統及方法 TWI797351B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862728664P 2018-09-07 2018-09-07
US62/728,664 2018-09-07
US16/184,898 US10796969B2 (en) 2018-09-07 2018-11-08 System and method for fabricating semiconductor wafer features having controlled dimensions
US16/184,898 2018-11-08

Publications (2)

Publication Number Publication Date
TW202016998A TW202016998A (zh) 2020-05-01
TWI797351B true TWI797351B (zh) 2023-04-01

Family

ID=69720071

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108123050A TWI797351B (zh) 2018-09-07 2019-07-01 用於製造具有控制尺寸之半導體晶圓特徵之系統及方法

Country Status (7)

Country Link
US (1) US10796969B2 (zh)
EP (1) EP3847688A4 (zh)
JP (1) JP7232901B2 (zh)
KR (1) KR102550487B1 (zh)
CN (1) CN112714947B (zh)
TW (1) TWI797351B (zh)
WO (1) WO2020051258A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11385187B1 (en) 2020-03-19 2022-07-12 Kla Corporation Method of fabricating particle size standards on substrates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060205136A1 (en) * 2004-12-22 2006-09-14 Stmicroelectronics S.R.L. Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
TW201413848A (zh) * 2012-07-09 2014-04-01 Shinetsu Handotai Kk 半導體晶圓的評價方法及製造方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339000B1 (en) * 1998-09-25 2002-01-15 Conexant Systems, Inc. Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures
JP2002118083A (ja) * 2000-10-05 2002-04-19 Hitachi Ltd 半導体集積回路装置の製造方法
US6602759B2 (en) * 2000-12-07 2003-08-05 International Business Machines Corporation Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
KR20020071063A (ko) * 2001-03-02 2002-09-12 삼성전자 주식회사 덴트 없는 트렌치 격리 구조 및 그 형성 방법
JP3597495B2 (ja) * 2001-08-31 2004-12-08 株式会社ルネサステクノロジ 半導体集積回路装置
US7291886B2 (en) * 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7052921B1 (en) * 2004-09-03 2006-05-30 Advanced Micro Devices, Inc. System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process
US7008853B1 (en) * 2005-02-25 2006-03-07 Infineon Technologies, Ag Method and system for fabricating free-standing nanostructures
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US7271063B2 (en) * 2005-10-13 2007-09-18 Elite Semiconductor Memory Technology, Inc. Method of forming FLASH cell array having reduced word line pitch
JP2007109966A (ja) * 2005-10-14 2007-04-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4638800B2 (ja) 2005-10-27 2011-02-23 株式会社日立ハイテクノロジーズ 走査電子顕微鏡装置における機差管理システムおよびその方法
US8129242B2 (en) * 2006-05-12 2012-03-06 Macronix International Co., Ltd. Method of manufacturing a memory device
JP4857090B2 (ja) * 2006-11-27 2012-01-18 株式会社日立ハイテクノロジーズ 校正用標準部材およびその作製方法、並びに校正用標準部材を用いた走査電子顕微鏡
US8021563B2 (en) * 2007-03-23 2011-09-20 Alpha & Omega Semiconductor, Ltd Etch depth determination for SGT technology
US8126255B2 (en) 2007-09-20 2012-02-28 Kla-Tencor Corp. Systems and methods for creating persistent data for a wafer and for using persistent data for inspection-related functions
US7824983B2 (en) * 2008-06-02 2010-11-02 Micron Technology, Inc. Methods of providing electrical isolation in semiconductor structures
US8853091B2 (en) * 2009-01-16 2014-10-07 Microchip Technology Incorporated Method for manufacturing a semiconductor die with multiple depth shallow trench isolation
KR101186043B1 (ko) 2009-06-22 2012-09-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8232179B2 (en) * 2009-10-01 2012-07-31 International Business Machines Corporation Method to improve wet etch budget in FEOL integration
US8293625B2 (en) 2011-01-19 2012-10-23 International Business Machines Corporation Structure and method for hard mask removal on an SOI substrate without using CMP process
KR20140131681A (ko) 2013-05-06 2014-11-14 코닝정밀소재 주식회사 전력 소자용 기판, 그 제조방법 및 이를 포함하는 전력 소자
US9087869B2 (en) 2013-05-23 2015-07-21 International Business Machines Corporation Bulk semiconductor fins with self-aligned shallow trench isolation structures
US9293298B2 (en) 2013-12-23 2016-03-22 Kla-Tencor Corp. Defect discovery and inspection sensitivity optimization using automated classification of corresponding electron beam images
US9443731B1 (en) * 2015-02-20 2016-09-13 Tokyo Electron Limited Material processing to achieve sub-10nm patterning
US20170059758A1 (en) * 2015-08-24 2017-03-02 Moxtek, Inc. Small-Pitch Wire Grid Polarizer
US10483109B2 (en) * 2016-04-12 2019-11-19 Tokyo Electron Limited Self-aligned spacer formation
US10276674B2 (en) * 2016-06-28 2019-04-30 Globalfoundries Inc. Method of forming a gate contact structure and source/drain contact structure for a semiconductor device
EP3312882B1 (en) * 2016-10-20 2021-09-15 IMEC vzw A method of patterning a target layer
US10832908B2 (en) * 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10431663B2 (en) * 2018-01-10 2019-10-01 Globalfoundries Inc. Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060205136A1 (en) * 2004-12-22 2006-09-14 Stmicroelectronics S.R.L. Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
TW201413848A (zh) * 2012-07-09 2014-04-01 Shinetsu Handotai Kk 半導體晶圓的評價方法及製造方法

Also Published As

Publication number Publication date
EP3847688A4 (en) 2022-06-15
US20200083122A1 (en) 2020-03-12
US10796969B2 (en) 2020-10-06
JP2021536680A (ja) 2021-12-27
TW202016998A (zh) 2020-05-01
KR102550487B1 (ko) 2023-06-30
CN112714947A (zh) 2021-04-27
WO2020051258A1 (en) 2020-03-12
JP7232901B2 (ja) 2023-03-03
CN112714947B (zh) 2022-09-16
EP3847688A1 (en) 2021-07-14
KR20210043000A (ko) 2021-04-20

Similar Documents

Publication Publication Date Title
US11047806B2 (en) Defect discovery and recipe optimization for inspection of three-dimensional semiconductor structures
US10887580B2 (en) Three-dimensional imaging for semiconductor wafer inspection
TWI746498B (zh) 用於擴展之紅外線光譜橢偏量測之系統及方法
US10082470B2 (en) Defect marking for semiconductor wafer inspection
US9305341B2 (en) System and method for measurement of through silicon structures
TW201828382A (zh) 用於製程控制之量測系統及方法
JP2006343331A (ja) 試料のエッジ検査のためのシステム及び方法
JP6758309B2 (ja) フォーカスエラー感応性が減少した光学的計測
KR102362673B1 (ko) 개선된 스폿 크기 능력을 갖는 단일 파장 엘립소메트리
KR20120030378A (ko) 기판들 사이에서 베벨 에칭 재현성을 개선시키기 위한 장치 및 방법
TWI797351B (zh) 用於製造具有控制尺寸之半導體晶圓特徵之系統及方法
US5443684A (en) Method for measuring thin film thickness
JP3927780B2 (ja) 回路基板の製造方法
US11385187B1 (en) Method of fabricating particle size standards on substrates
US10024804B2 (en) System and method of characterizing micro-fabrication processes
TW202314239A (zh) 分析樣本的隱藏層
KR20150062208A (ko) 사파이어 기판의 결함 검사 방법 및 투명 기판의 결함 검사 방법
KR20090071072A (ko) 반도체 공정 중에 발생하는 파티클의 양을 측정하는 방법