JP7213803B2 - 半導体装置及び半導体装置の駆動方法 - Google Patents
半導体装置及び半導体装置の駆動方法 Download PDFInfo
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Description
本実施の形態では、開示する発明の一態様に係る半導体装置の回路構成および動作について、図1乃至図6を参照して説明する。
はじめに、後述する半導体装置のメモリセルの回路構成について、図1(A)及び図1(B)を参照して説明する。ここで、図1(A)は半導体装置の立体的な構成に対応させて、メモリセル10の回路構成を立体的に示した回路図の一例であり、図1(B)は、メモリセル10の構成例を示す断面模式図である。
次に、図1に示す回路を応用した、より具体的な回路構成および動作について、図2乃至図6を参照して説明する。
2次元メモリセルアレイ30[1]の一括消去においては、まず、配線SG2[1]に電位V1を与えて、選択トランジスタセル60(1,1)乃至(1,m2)のトランジスタ62をオン状態にし、配線WBL[1]乃至[m2]を、対応する配線WBL[1,1]乃至[1,m2]と導通状態にする。また、配線SG2[2]乃至[m1]をGNDとして、選択トランジスタセル60(2,1)乃至(m1,m2)のトランジスタ62をオフ状態にし、配線WBL[1]乃至[m2]を、対応する配線WBL[2,1]乃至[m1,m2]と非導通状態にしておく。このようにして一括消去動作の対象として2次元メモリセルアレイ30[1]を選択する。
2次元メモリセルアレイ30[1]の1行目書き込みにおいては、まず、2次元メモリセルアレイ30[1]の一括消去と同様の動作で書き込み動作の対象として2次元メモリセルアレイ30[1]を選択する。
2次元メモリセルアレイ30[1]の1行目読み出しにおいては、まず、配線SG1[1]に電位V1を与えて、選択トランジスタセル60(1,1)乃至(1,m2)のトランジスタ61をオン状態にし、配線RBL[1]乃至[m2]を、対応する配線RBL[1,1]乃至[1,m2]と導通状態にする。また、配線SG1[2]乃至[m1]をGNDとして、選択トランジスタセル60(2,1)乃至(m1,m2)のトランジスタ61をオフ状態にし、配線RBL[1]乃至[m2]を、対応する配線RBL[2,1]乃至[m1,m2]と非導通状態にしておく。このようにして読み出し動作の対象として2次元メモリセルアレイ30[1]を選択する。
本実施の形態では、本発明の一態様に係る半導体装置の構成について、図7乃至図26を用いて説明する。
メモリセル10および、当該メモリセル10が複数配列した3次元メモリセルアレイ40の構成について図7乃至図9を用いて説明する。図7は、3次元メモリセルアレイ40の立体的な模式図である。図8(A)は、メモリセル10を含む3次元メモリセルアレイ40の一部の断面図であり、図8(B)、図9(A)および図9(B)に示す一点鎖線A1-A2に対応する。図8(B)は、図8(A)に示す層140の平面図である。また、図9(A)は、図8(A)に示す層141の平面図である。また、図9(B)は、図8(A)に示す層142の平面図である。なお、図7乃至図9において、図2と同様に、x軸、y軸、z軸からなる直交座標系を便宜上設定して説明する。ここで、3次元メモリセルアレイ40が設けられる基板の上面は概略xy平面に平行であり、z軸は当該基板の上面に略垂直である。なお、図7においては、メモリセル10の一部の構成(例えば、絶縁体116、絶縁体112など)を省略して表現している。
以下では、本実施の形態に示す半導体装置に用いることができる構成材料について説明する。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。本実施の形態に示す絶縁体は、その機能に応じて下記の絶縁体から選択して、単層または積層で形成することができる。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
以下では、本発明に係る酸化物106および酸化物134に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(c-axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記金属酸化物をトランジスタのチャネル形成領域に用いる場合について説明する。
ここで、金属酸化物中における各不純物の影響について説明する。
次に、先の実施の形態に示す選択トランジスタアレイが有するトランジスタの構成の一例について図13を用いて説明する。
次に、上記半導体装置の作製方法について、図14乃至図26を用いて説明する。図14乃至図26は、上記半導体装置の3次元メモリセルアレイ40の一部のメモリセル10の作製過程を示した図である。図14(A)乃至図26(A)はメモリセル10の層140の平面図であり、図14(B)乃至図26(B)はメモリセル10の断面図であり、図14(A)乃至図26(A)に示す一点鎖線A1-A2に対応する。また、図14(A)乃至図26(A)は図8(B)に示す平面図に対応しており、図14(B)乃至図26(B)は図8(A)に示す断面図に対応している。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図27にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置やリムーバブルメモリに用いられる。
本実施の形態では、図28を用いて、上記実施の形態に示す半導体装置を適用した、AIシステムについて説明を行う。
<AIシステムの応用例>
本実施の形態では、上記実施の形態に示すAIシステムの応用例について図29を用いて説明を行う。
本実施の形態は、上記実施の形態に示すAIシステムが組み込まれたICの一例を示す。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図31乃至図33に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
Claims (7)
- メモリセルを有する半導体装置であって、
前記メモリセルは、
第1の導電体と、
前記第1の導電体上の第1の絶縁体と、
前記第1の絶縁体上の、第1の領域、第2の領域、および前記第1の領域と前記第2の領域との間に配置された第3の領域を有する第1の酸化物と、
前記第1の酸化物上の第2の絶縁体と、
前記第2の絶縁体上の第2の導電体と、
前記第1の領域の側面に接して配置された第3の絶縁体と、
前記第1の領域の側面に、前記第3の絶縁体を介して配置された第2の酸化物と、を有し、
前記第1の領域は、前記第1の導電体と重畳する領域を有し、
前記第3の領域は、前記第2の導電体と重畳する領域を有し、
前記第1の導電体、前記第2の導電体、前記第1の絶縁体、および前記第2の絶縁体は、開口を有し、
前記第2の酸化物は、前記第3の絶縁体を介して、前記開口内に配置される領域を有し、
前記第1の領域、および前記第2の領域は、前記第3の領域よりも低抵抗である、半導体装置。 - メモリセルを有する半導体装置であって、
前記メモリセルは、
第1の導電体と、
前記第1の導電体上の第1の絶縁体と、
前記第1の絶縁体上の、第1の領域、第2の領域、および前記第1の領域と前記第2の領域との間に配置された第3の領域を有する第1の酸化物と、
前記第1の酸化物上の第2の絶縁体と、
前記第2の絶縁体上の第2の導電体と、
前記第1の領域の側面に接して配置された第3の絶縁体と、
前記第1の領域の側面に、前記第3の絶縁体を介して配置された第2の酸化物と、を有し、
前記第1の領域は、前記第1の導電体と重畳する領域を有し、
前記第3の領域は、前記第2の導電体と重畳する領域を有し、
前記第1の導電体、前記第2の導電体、前記第1の絶縁体、および前記第2の絶縁体は、開口を有し、
前記第2の酸化物は、前記第3の絶縁体を介して、前記開口内に配置される領域を有し、
前記第1の領域、および前記第2の領域は、前記第3の領域よりも低抵抗であり、
前記第1の導電体、前記第1の絶縁体、および前記第1の領域は、容量素子として機能し、
前記第1の酸化物、前記第2の絶縁体、および前記第2の導電体は、第1のトランジスタとして機能し、
前記第2の酸化物、前記第3の絶縁体、および前記第1の領域は、第2のトランジスタとして機能する、半導体装置。 - 請求項1または請求項2において、
前記第1の酸化物、および前記第2の酸化物は、Inと、元素M(MはAl、Ga、Y、またはSn)と、Znと、を有する、半導体装置。 - 請求項1または請求項2において、
前記半導体装置は、基体を有し、
前記基体上に、複数の前記メモリセルを有する、半導体装置。 - 請求項4において、
前記半導体装置は、第4の絶縁体と、を有し、
前記半導体装置は、前記基体が有する一の面に対して水平な方向に、mh個(mhは2以上の整数)のメモリセルを有し、
前記第4の絶縁体は、前記第1の絶縁体と、前記第2の絶縁体との間に配置され、前記第1の酸化物の側面と接し、
前記mh個のメモリセルは、前記第4の絶縁体により、素子分離されている、半導体装置。 - 請求項4において、
前記半導体装置は、前記基体が有する一の面に対して垂直な方向に、mv個(mvは2以上の整数)のメモリセルを有する、半導体装置。 - 請求項6において、
前記第2の酸化物は、前記mv個のメモリセルで共通して設けられる、半導体装置。
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