JP7166818B2 - 光半導体素子 - Google Patents
光半導体素子 Download PDFInfo
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- JP7166818B2 JP7166818B2 JP2018133328A JP2018133328A JP7166818B2 JP 7166818 B2 JP7166818 B2 JP 7166818B2 JP 2018133328 A JP2018133328 A JP 2018133328A JP 2018133328 A JP2018133328 A JP 2018133328A JP 7166818 B2 JP7166818 B2 JP 7166818B2
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Description
四隅を除いて、サブマウント電極13に合致する形状であって、当該四隅に対応する角部が欠けている形状を有している。換言すれば、チップ電極17は、四隅が欠けている点を除いては、サブマウント電極13に合致する平面形状を有している。また、サブマウント電極は13は、当該四隅を除いてチップ電極17に合致して接合されている。
図6Cは、本実施例の変形例である光半導体素子11Rの下面図である。図6Dは、図6Cの6D-6D線に沿った断面図であり、サブマウント12を最下層として示している。
11、31、51 光半導体素子
12、52 サブマウント
13、33、53 サブマウント電極
13S、33S、53S 露出面
15、35、55 接合層
17、37、57 チップ電極
18、38 素子基板
19、59 半導体構造層
20、40、60 半導体チップ
21、61A、61B 給電接着剤
23A、23B 通電パッド
24 ボンディングワイヤ
25 リフレクタ
26 キャビティ
Claims (12)
- 搭載面を有する平板状のサブマウントと、
前記サブマウントの前記搭載面上に設けられ、全体として矩形形状を有するサブマウント電極と、
素子基板、前記素子基板上に形成された半導体構造層、及び前記サブマウント電極に接合層を介して接合されたチップ電極を含む半導体チップと、を有し、
前記チップ電極は、前記サブマウント電極の四隅に対応する角部が欠けている形状を有し、
前記サブマウント電極は前記四隅において前記チップ電極から露出した部分である露出面を有して前記チップ電極に合致して接合され、
前記接合層は、前記四隅の全ての前記露出面まで延在している光半導体素子。 - 前記サブマウント電極は、各々が矩形形状を有し、互いに離間して配置された2つのサブマウント電極片を有し、
前記チップ電極は、前記サブマウント電極の前記四隅を除いて、各々が対応する前記サブマウント電極片に合致する形状及び配置を有し、前記サブマウント電極の前記四隅に対応する角部が欠けている2つのチップ電極片を有し、
前記四隅を除いて、前記2つのサブマウント電極片と、前記2つのチップ電極片とが、互いに合致して接合されている、請求項1に記載の光半導体素子。 - 前記2つのチップ電極片の各々は、前記2つのサブマウント電極片の各々の四隅に対応する角部が欠けており、
前記2つのサブマウント電極片の各々は、前記各々の四隅において前記露出面を有し、
前記接合層は、前記各々の四隅の全ての前記露出面まで延在している請求項2に記載の光半導体素子。 - 前記サブマウント電極は、各々がストライプ形状を有し互いに離間して配置された第1乃至第n(n≧2)のサブマウント電極片を含み、
前記チップ電極は、前記サブマウント電極の四隅を除いて、各々が対応する前記サブマウント電極片に合致する形状及び配置を有し、第1及び第nの前記サブマウント電極片の両端部に対応する端部が欠けている第1乃至第nのチップ電極片を有し、
前記四隅を除いて、前記サブマウント電極片の各々と、前記チップ電極片の各々と、が互いに合致して接合されている請求項1に記載の光半導体素子。 - 前記サブマウント電極は、各々がストライプ形状を有し互いに離間して配置された第1乃至第n(n≧2)のサブマウント電極片を含み、
前記チップ電極は、前記サブマウント電極片の各々の端部を除いて、各々が対応する前記サブマウント電極片に合致する形状及び配置を有し、前記サブマウント電極片の各々の両端部に対応する端部が欠けている第1乃至第nのチップ電極片を有し、
前記サブマウント電極片の各々は、前記各々の両端部において前記チップ電極片の各々から露出した部分である露出面を有し、
前記接合層は、前記サブマウント電極片の各々の前記露出面まで延在している請求項1に記載の光半導体素子。 - 請求項4又は5に記載の光半導体素子であって、
前記第1乃至第nのサブマウント電極片は、前記ストライプ形状の長辺同士が互いに平行に配置されてn行の配列をなし、
前記半導体チップは、前記第1乃至第nのチップ電極片から離間して設けられたチップ側反対電極を有し、
前記サブマウントは、前記搭載面上に、前記サブマウント電極から離間して設けられて、前記チップ側反対電極に前記接合層を介して接合されているサブマウント側反対電極を有する光半導体素子。 - 前記半導体構造層は、第1導電型半導体層、活性層及び第2導電型半導体層を含み、
前記第1乃至第nのチップ電極片は、前記第1導電型半導体層に電気的に接続され、
前記第1導電型半導体層は、前記第1乃至第nのチップ電極片の各々に対応する形状及び配置を有する櫛歯部及び前記櫛歯部の片側の端部を連結する基部からなる櫛歯状に形成された第1の電極層を有し、
前記第2導電型半導体層は、前記チップ側反対電極に電気的に接続された基部、及び前記第1乃至第nのチップ電極片の間隙に伸長する櫛歯部からなる櫛歯状に形成された第2の電極層を有する請求項6に記載の光半導体素子。 - 前記接合層は、前記露出面の各々の全体を覆うように延在している請求項1乃至7のいずれか1項に記載の光半導体素子。
- 前記素子基板は、所定の波長の光に対して透光性を有する請求項1乃至8のいずれか1項に記載の光半導体素子。
- 前記素子基板は可視光領域の波長の光に対して透光性を有する請求項1乃至9のいずれか1項に記載の光半導体素子。
- 搭載面を有する平板状のサブマウントと、
前記サブマウントの前記搭載面上に設けられたサブマウント電極と、
素子基板、前記素子基板上に形成された半導体構造層、及び前記サブマウント電極に接合層を介して接合され、全体として矩形形状を有するチップ電極を含む半導体チップと、を有し、
前記サブマウント電極は、前記チップ電極の四隅に対応する角部が欠けている形状を有し、
前記チップ電極は前記四隅において前記サブマウント電極から露出した部分である露出面を有して前記サブマウント電極に合致して接合され、
前記接合層は、前記四隅の全ての前記露出面まで延在している光半導体素子。 - 前記サブマウントは、所定の波長の光に対して透光性を有する請求項11に記載の光半導体素子。
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