JP7158373B2 - 裏面半導体成長 - Google Patents
裏面半導体成長 Download PDFInfo
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- JP7158373B2 JP7158373B2 JP2019506348A JP2019506348A JP7158373B2 JP 7158373 B2 JP7158373 B2 JP 7158373B2 JP 2019506348 A JP2019506348 A JP 2019506348A JP 2019506348 A JP2019506348 A JP 2019506348A JP 7158373 B2 JP7158373 B2 JP 7158373B2
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
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- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
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- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Geometry (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/234,889 US9780210B1 (en) | 2016-08-11 | 2016-08-11 | Backside semiconductor growth |
| US15/234,889 | 2016-08-11 | ||
| PCT/US2017/041755 WO2018031175A1 (en) | 2016-08-11 | 2017-07-12 | Backside semiconductor growth |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019525478A JP2019525478A (ja) | 2019-09-05 |
| JP2019525478A5 JP2019525478A5 (enExample) | 2020-08-06 |
| JP7158373B2 true JP7158373B2 (ja) | 2022-10-21 |
Family
ID=59485418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019506348A Active JP7158373B2 (ja) | 2016-08-11 | 2017-07-12 | 裏面半導体成長 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9780210B1 (enExample) |
| EP (1) | EP3497715B8 (enExample) |
| JP (1) | JP7158373B2 (enExample) |
| KR (1) | KR102505236B1 (enExample) |
| CN (1) | CN109643691B (enExample) |
| BR (1) | BR112019002343B1 (enExample) |
| CA (1) | CA3030289C (enExample) |
| WO (1) | WO2018031175A1 (enExample) |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112015006959T5 (de) | 2015-09-24 | 2018-06-07 | Intel Corporation | Verfahren zum bilden rückseitiger selbstausgerichteter durchkontaktierungen und dadurch gebildete strukturen |
| WO2017171842A1 (en) | 2016-04-01 | 2017-10-05 | Intel Corporation | Transistor cells including a deep via lined with a dielectric material |
| US9847293B1 (en) * | 2016-08-18 | 2017-12-19 | Qualcomm Incorporated | Utilization of backside silicidation to form dual side contacted capacitor |
| US10872820B2 (en) | 2016-08-26 | 2020-12-22 | Intel Corporation | Integrated circuit structures |
| DE102018106266B4 (de) | 2017-06-30 | 2024-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und verfahren zu ihrer herstellung |
| US10431664B2 (en) * | 2017-06-30 | 2019-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure and methods thereof |
| US10439565B2 (en) | 2017-09-27 | 2019-10-08 | Qualcomm Incorporated | Low parasitic capacitance low noise amplifier |
| KR102019354B1 (ko) | 2017-11-03 | 2019-09-09 | 삼성전자주식회사 | 안테나 모듈 |
| US11869890B2 (en) | 2017-12-26 | 2024-01-09 | Intel Corporation | Stacked transistors with contact last |
| US11430814B2 (en) | 2018-03-05 | 2022-08-30 | Intel Corporation | Metallization structures for stacked device connectivity and their methods of fabrication |
| US10580903B2 (en) | 2018-03-13 | 2020-03-03 | Psemi Corporation | Semiconductor-on-insulator transistor with improved breakdown characteristics |
| CN110504240B (zh) * | 2018-05-16 | 2021-08-13 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
| US20190371891A1 (en) * | 2018-06-01 | 2019-12-05 | Qualcomm Incorporated | Bulk layer transfer based switch with backside silicidation |
| US10680086B2 (en) * | 2018-06-18 | 2020-06-09 | Qualcomm Incorporated | Radio frequency silicon-on-insulator integrated heterojunction bipolar transistor |
| US10573674B2 (en) | 2018-07-19 | 2020-02-25 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
| US10672806B2 (en) | 2018-07-19 | 2020-06-02 | Psemi Corporation | High-Q integrated circuit inductor structure and methods |
| US10658386B2 (en) | 2018-07-19 | 2020-05-19 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
| TWI716748B (zh) * | 2018-10-11 | 2021-01-21 | 世界先進積體電路股份有限公司 | 半導體裝置及其製造方法 |
| CN111092086B (zh) * | 2018-10-24 | 2022-04-19 | 世界先进积体电路股份有限公司 | 半导体装置及其制造方法 |
| US11688780B2 (en) | 2019-03-22 | 2023-06-27 | Intel Corporation | Deep source and drain for transistor structures with back-side contact metallization |
| US11296023B2 (en) * | 2019-04-10 | 2022-04-05 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| US11476363B2 (en) | 2019-04-10 | 2022-10-18 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| CN111816710A (zh) * | 2019-04-10 | 2020-10-23 | 联华电子股份有限公司 | 半导体装置 |
| KR102801648B1 (ko) * | 2019-05-21 | 2025-05-02 | 삼성전자주식회사 | 반도체 소자 |
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Also Published As
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| EP3497715B1 (en) | 2025-06-04 |
| BR112019002343B1 (pt) | 2023-04-04 |
| KR20190036533A (ko) | 2019-04-04 |
| CN109643691A (zh) | 2019-04-16 |
| CA3030289C (en) | 2025-02-18 |
| CN109643691B (zh) | 2023-09-01 |
| KR102505236B1 (ko) | 2023-03-02 |
| JP2019525478A (ja) | 2019-09-05 |
| EP3497715A1 (en) | 2019-06-19 |
| EP3497715B8 (en) | 2025-07-09 |
| WO2018031175A1 (en) | 2018-02-15 |
| BR112019002343A2 (pt) | 2019-06-18 |
| US9780210B1 (en) | 2017-10-03 |
| EP3497715C0 (en) | 2025-06-04 |
| CA3030289A1 (en) | 2018-02-15 |
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