KR102505236B1 - 백사이드 반도체 성장 - Google Patents
백사이드 반도체 성장 Download PDFInfo
- Publication number
- KR102505236B1 KR102505236B1 KR1020197003917A KR20197003917A KR102505236B1 KR 102505236 B1 KR102505236 B1 KR 102505236B1 KR 1020197003917 A KR1020197003917 A KR 1020197003917A KR 20197003917 A KR20197003917 A KR 20197003917A KR 102505236 B1 KR102505236 B1 KR 102505236B1
- Authority
- KR
- South Korea
- Prior art keywords
- backside
- source
- drain region
- transistor
- circuit structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
-
- H01L29/165—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H01L29/1608—
-
- H01L29/66651—
-
- H01L29/7838—
-
- H01L29/7848—
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
- H04B1/006—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6744—Monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/234,889 US9780210B1 (en) | 2016-08-11 | 2016-08-11 | Backside semiconductor growth |
| US15/234,889 | 2016-08-11 | ||
| PCT/US2017/041755 WO2018031175A1 (en) | 2016-08-11 | 2017-07-12 | Backside semiconductor growth |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20190036533A KR20190036533A (ko) | 2019-04-04 |
| KR102505236B1 true KR102505236B1 (ko) | 2023-03-02 |
Family
ID=59485418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020197003917A Active KR102505236B1 (ko) | 2016-08-11 | 2017-07-12 | 백사이드 반도체 성장 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9780210B1 (enExample) |
| EP (1) | EP3497715B8 (enExample) |
| JP (1) | JP7158373B2 (enExample) |
| KR (1) | KR102505236B1 (enExample) |
| CN (1) | CN109643691B (enExample) |
| BR (1) | BR112019002343B1 (enExample) |
| CA (1) | CA3030289C (enExample) |
| WO (1) | WO2018031175A1 (enExample) |
Families Citing this family (51)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112015006959T5 (de) | 2015-09-24 | 2018-06-07 | Intel Corporation | Verfahren zum bilden rückseitiger selbstausgerichteter durchkontaktierungen und dadurch gebildete strukturen |
| WO2017171842A1 (en) | 2016-04-01 | 2017-10-05 | Intel Corporation | Transistor cells including a deep via lined with a dielectric material |
| US9847293B1 (en) * | 2016-08-18 | 2017-12-19 | Qualcomm Incorporated | Utilization of backside silicidation to form dual side contacted capacitor |
| KR102548835B1 (ko) * | 2016-08-26 | 2023-06-30 | 인텔 코포레이션 | 집적 회로 디바이스 구조체들 및 양면 제조 기술들 |
| DE102018106266B4 (de) | 2017-06-30 | 2024-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und verfahren zu ihrer herstellung |
| US10431664B2 (en) * | 2017-06-30 | 2019-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure and methods thereof |
| US10439565B2 (en) * | 2017-09-27 | 2019-10-08 | Qualcomm Incorporated | Low parasitic capacitance low noise amplifier |
| KR102019354B1 (ko) * | 2017-11-03 | 2019-09-09 | 삼성전자주식회사 | 안테나 모듈 |
| US11869890B2 (en) | 2017-12-26 | 2024-01-09 | Intel Corporation | Stacked transistors with contact last |
| WO2019172879A1 (en) | 2018-03-05 | 2019-09-12 | Intel Corporation | Metallization structures for stacked device connectivity and their methods of fabrication |
| US10580903B2 (en) | 2018-03-13 | 2020-03-03 | Psemi Corporation | Semiconductor-on-insulator transistor with improved breakdown characteristics |
| CN110504240B (zh) * | 2018-05-16 | 2021-08-13 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
| US20190371891A1 (en) * | 2018-06-01 | 2019-12-05 | Qualcomm Incorporated | Bulk layer transfer based switch with backside silicidation |
| US10680086B2 (en) * | 2018-06-18 | 2020-06-09 | Qualcomm Incorporated | Radio frequency silicon-on-insulator integrated heterojunction bipolar transistor |
| US10672806B2 (en) * | 2018-07-19 | 2020-06-02 | Psemi Corporation | High-Q integrated circuit inductor structure and methods |
| US10658386B2 (en) | 2018-07-19 | 2020-05-19 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
| US10573674B2 (en) | 2018-07-19 | 2020-02-25 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
| TWI716748B (zh) * | 2018-10-11 | 2021-01-21 | 世界先進積體電路股份有限公司 | 半導體裝置及其製造方法 |
| CN111092086B (zh) * | 2018-10-24 | 2022-04-19 | 世界先进积体电路股份有限公司 | 半导体装置及其制造方法 |
| US11688780B2 (en) | 2019-03-22 | 2023-06-27 | Intel Corporation | Deep source and drain for transistor structures with back-side contact metallization |
| US11476363B2 (en) | 2019-04-10 | 2022-10-18 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| US11296023B2 (en) * | 2019-04-10 | 2022-04-05 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| CN111816710A (zh) * | 2019-04-10 | 2020-10-23 | 联华电子股份有限公司 | 半导体装置 |
| KR102801648B1 (ko) * | 2019-05-21 | 2025-05-02 | 삼성전자주식회사 | 반도체 소자 |
| US10777636B1 (en) | 2019-06-12 | 2020-09-15 | Psemi Corporation | High density IC capacitor structure |
| US11004972B2 (en) * | 2019-06-12 | 2021-05-11 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure |
| TWI787787B (zh) | 2020-04-24 | 2022-12-21 | 台灣積體電路製造股份有限公司 | 半導體電晶體裝置及形成半導體電晶體裝置的方法 |
| US11658220B2 (en) * | 2020-04-24 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Drain side recess for back-side power rail device |
| DE102021101178B4 (de) * | 2020-04-29 | 2024-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrierte-schaltkreis-struktur mit rückseitiger dielektrischer schicht mit luftspalt sowie verfahren zu deren herstellung |
| CN114914292A (zh) * | 2020-05-11 | 2022-08-16 | 北京华碳元芯电子科技有限责任公司 | 一种晶体管 |
| DE102020122823B4 (de) * | 2020-05-12 | 2022-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtungen mit entkopplungskondensatoren |
| DE102020131611B4 (de) * | 2020-05-28 | 2025-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung mit luftspalten und verfahren zu deren herstellung |
| US11862561B2 (en) * | 2020-05-28 | 2024-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with backside routing and method of forming same |
| DE102021103791A1 (de) | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silizid-belegter source/drain-bereich und dessen herstellungsverfahren |
| US11563095B2 (en) | 2020-05-29 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide-sandwiched source/drain region and method of fabricating same |
| US11626494B2 (en) * | 2020-06-17 | 2023-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial backside contact |
| US11532713B2 (en) | 2020-06-25 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain contacts and methods of forming same |
| US11557510B2 (en) * | 2020-07-30 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Spacers for semiconductor devices including backside power rails |
| US11456209B2 (en) * | 2020-07-31 | 2022-09-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Spacers for semiconductor devices including a backside power rails |
| US11482594B2 (en) | 2020-08-27 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with backside power rail and method thereof |
| US11588050B2 (en) * | 2020-08-31 | 2023-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Backside contact |
| US11437379B2 (en) * | 2020-09-18 | 2022-09-06 | Qualcomm Incorporated | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits |
| US12165973B2 (en) * | 2020-09-30 | 2024-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with backside power rail and method for forming the same |
| US12218664B2 (en) | 2020-10-21 | 2025-02-04 | Arm Limited | Backside power supply techniques |
| US11658119B2 (en) * | 2020-10-27 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside signal interconnection |
| US11967551B2 (en) * | 2021-04-07 | 2024-04-23 | Arm Limited | Standard cell architecture |
| US20220352256A1 (en) * | 2021-04-28 | 2022-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside memory integration |
| US20220359679A1 (en) * | 2021-05-05 | 2022-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Backside source/drain contacts and methods of forming the same |
| CN115376994B (zh) * | 2021-05-19 | 2025-10-21 | 邱志威 | 晶体管下具有电源连接结构的半导体结构及其制造方法 |
| US12224286B2 (en) | 2021-09-22 | 2025-02-11 | Qualcomm Incorporated | Symmetric dual-sided MOS IC |
| US11935927B2 (en) | 2021-11-10 | 2024-03-19 | Globalfoundries U.S. Inc. | Bipolar transistor with collector contact |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080206977A1 (en) | 2007-02-22 | 2008-08-28 | Frank David J | Methods of forming wiring to transistor and related transistor |
| US20130134527A1 (en) | 2010-11-11 | 2013-05-30 | International Business Machines Corporation | Structure and method to fabricate a body contact |
| US20150091092A1 (en) | 2013-10-02 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dynamic Threshold MOS and Methods of Forming the Same |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0483348A (ja) * | 1990-07-26 | 1992-03-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP3092761B2 (ja) * | 1991-12-02 | 2000-09-25 | キヤノン株式会社 | 画像表示装置及びその製造方法 |
| TW473914B (en) * | 2000-01-12 | 2002-01-21 | Ibm | Buried metal body contact structure and method for fabricating SOI MOSFET devices |
| JP3764401B2 (ja) * | 2002-04-18 | 2006-04-05 | 株式会社東芝 | 半導体装置の製造方法 |
| DE102004033149B4 (de) * | 2004-07-08 | 2006-09-28 | Infineon Technologies Ag | Verfahren zum Herstellen eines Doppel-Gate-Transistors, einer Speicherzelle, eines Vertikaltransistors sowie vergrabenen Wort- bzw. Bitleitungen jeweils unter Verwendung einer vergrabenen Ätzstoppschicht |
| JP4175650B2 (ja) * | 2004-08-26 | 2008-11-05 | シャープ株式会社 | 半導体装置の製造方法 |
| WO2006070310A1 (en) * | 2004-12-28 | 2006-07-06 | Koninklijke Philips Electronics N.V. | Method for the manufacture of a semiconductor device and a semiconductor device obtained through it |
| US7816231B2 (en) | 2006-08-29 | 2010-10-19 | International Business Machines Corporation | Device structures including backside contacts, and methods for forming same |
| JP2008252068A (ja) * | 2007-03-08 | 2008-10-16 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
| JP5322408B2 (ja) * | 2007-07-17 | 2013-10-23 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
| US7897468B1 (en) * | 2009-09-10 | 2011-03-01 | International Business Machines Corporation | Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island |
| US8373228B2 (en) * | 2010-01-14 | 2013-02-12 | GlobalFoundries, Inc. | Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method |
| US8716091B2 (en) | 2010-03-30 | 2014-05-06 | International Business Machines Corporation | Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain |
| US8318574B2 (en) | 2010-07-30 | 2012-11-27 | International Business Machines Corporation | SOI trench DRAM structure with backside strap |
| US8772874B2 (en) * | 2011-08-24 | 2014-07-08 | International Business Machines Corporation | MOSFET including asymmetric source and drain regions |
| US8895379B2 (en) * | 2012-01-06 | 2014-11-25 | International Business Machines Corporation | Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same |
| US9219129B2 (en) * | 2012-05-10 | 2015-12-22 | International Business Machines Corporation | Inverted thin channel mosfet with self-aligned expanded source/drain |
| US9023688B1 (en) * | 2013-06-09 | 2015-05-05 | Monolithic 3D Inc. | Method of processing a semiconductor device |
| CN104241357A (zh) | 2013-06-18 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 一种晶体管、集成电路以及集成电路的制造方法 |
| US9209305B1 (en) * | 2014-06-06 | 2015-12-08 | Stmicroelectronics, Inc. | Backside source-drain contact for integrated circuit transistor devices and method of making same |
| WO2017052667A1 (en) * | 2015-09-27 | 2017-03-30 | Intel Corporation | Metal on both sides of the transistor integrated with magnetic inductors |
-
2016
- 2016-08-11 US US15/234,889 patent/US9780210B1/en active Active
-
2017
- 2017-07-12 EP EP17745908.8A patent/EP3497715B8/en active Active
- 2017-07-12 KR KR1020197003917A patent/KR102505236B1/ko active Active
- 2017-07-12 BR BR112019002343-7A patent/BR112019002343B1/pt active IP Right Grant
- 2017-07-12 JP JP2019506348A patent/JP7158373B2/ja active Active
- 2017-07-12 CN CN201780049283.0A patent/CN109643691B/zh active Active
- 2017-07-12 CA CA3030289A patent/CA3030289C/en active Active
- 2017-07-12 WO PCT/US2017/041755 patent/WO2018031175A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080206977A1 (en) | 2007-02-22 | 2008-08-28 | Frank David J | Methods of forming wiring to transistor and related transistor |
| US20130134527A1 (en) | 2010-11-11 | 2013-05-30 | International Business Machines Corporation | Structure and method to fabricate a body contact |
| US20150091092A1 (en) | 2013-10-02 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dynamic Threshold MOS and Methods of Forming the Same |
Also Published As
| Publication number | Publication date |
|---|---|
| CA3030289C (en) | 2025-02-18 |
| CN109643691B (zh) | 2023-09-01 |
| JP7158373B2 (ja) | 2022-10-21 |
| KR20190036533A (ko) | 2019-04-04 |
| CN109643691A (zh) | 2019-04-16 |
| EP3497715C0 (en) | 2025-06-04 |
| EP3497715B8 (en) | 2025-07-09 |
| JP2019525478A (ja) | 2019-09-05 |
| BR112019002343A2 (pt) | 2019-06-18 |
| WO2018031175A1 (en) | 2018-02-15 |
| CA3030289A1 (en) | 2018-02-15 |
| BR112019002343B1 (pt) | 2023-04-04 |
| EP3497715B1 (en) | 2025-06-04 |
| US9780210B1 (en) | 2017-10-03 |
| EP3497715A1 (en) | 2019-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102505236B1 (ko) | 백사이드 반도체 성장 | |
| KR102054924B1 (ko) | 듀얼-사이디드 프로세싱을 갖는 로직 회로 블록 레이아웃들 | |
| US10420171B2 (en) | Semiconductor devices on two sides of an isolation layer | |
| US10431558B2 (en) | Method and apparatus for back-biased switch transistors | |
| US10074942B2 (en) | Switch device performance improvement through multisided biased shielding | |
| US9812580B1 (en) | Deep trench active device with backside body contact | |
| US9917062B1 (en) | Self-aligned transistors for dual-side processing | |
| US10043752B2 (en) | Substrate contact using dual sided silicidation | |
| US10290579B2 (en) | Utilization of backside silicidation to form dual side contacted capacitor | |
| HK40009868A (en) | Logic circuit block layouts with dual-sided processing | |
| HK40009868B (en) | Logic circuit block layouts with dual-sided processing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20190208 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20200626 Comment text: Request for Examination of Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20220726 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20221221 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20230224 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20230224 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration |