BR112019002343A2 - crescimento de semicondutores na parte posterior - Google Patents

crescimento de semicondutores na parte posterior

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Publication number
BR112019002343A2
BR112019002343A2 BR112019002343A BR112019002343A BR112019002343A2 BR 112019002343 A2 BR112019002343 A2 BR 112019002343A2 BR 112019002343 A BR112019002343 A BR 112019002343A BR 112019002343 A BR112019002343 A BR 112019002343A BR 112019002343 A2 BR112019002343 A2 BR 112019002343A2
Authority
BR
Brazil
Prior art keywords
drain
body region
source
transistor
integrated circuit
Prior art date
Application number
BR112019002343A
Other languages
English (en)
Other versions
BR112019002343B1 (pt
Inventor
Hammond Richard
Goktepeli Sinan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112019002343A2 publication Critical patent/BR112019002343A2/pt
Publication of BR112019002343B1 publication Critical patent/BR112019002343B1/pt

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    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • General Physics & Mathematics (AREA)
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  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
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  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

uma estrutura de circuito integrado pode incluir um transistor sobre uma camada de semicondutores frontal apoiada por uma camada de isolamento. o transistor é uma primeira região fonte/dreno/corpo. a estrutura de circuito integrado também pode incluir uma região fonte/dreno/corpo elevada acoplada a uma parte posterior da primeira região fonte/dreno/corpo do transistor. o transistor é uma região fonte/dreno/corpo elevada que se estende a partir da parte posterior da primeira região fonte/dreno/corpo em direção a uma camada dielétrica posterior que apoia a camada de isolamento. a estrutura de circuito integrado pode ainda incluir uma metalização posterior acoplada à região fonte/dreno/corpo elevada.
BR112019002343-7A 2016-08-11 2017-07-12 Estrutura de circuito integrado, método de construção de uma estrutura de circuito integrado, e módulo inicial de radiofrequência, rf BR112019002343B1 (pt)

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US15/234,889 US9780210B1 (en) 2016-08-11 2016-08-11 Backside semiconductor growth
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PCT/US2017/041755 WO2018031175A1 (en) 2016-08-11 2017-07-12 Backside semiconductor growth

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CA3030289A1 (en) 2018-02-15
BR112019002343B1 (pt) 2023-04-04
JP7158373B2 (ja) 2022-10-21
CN109643691B (zh) 2023-09-01
JP2019525478A (ja) 2019-09-05
US9780210B1 (en) 2017-10-03
WO2018031175A1 (en) 2018-02-15
EP3497715A1 (en) 2019-06-19
KR20190036533A (ko) 2019-04-04
KR102505236B1 (ko) 2023-03-02

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