CN109643691A - 背面半导体生长 - Google Patents
背面半导体生长 Download PDFInfo
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- CN109643691A CN109643691A CN201780049283.0A CN201780049283A CN109643691A CN 109643691 A CN109643691 A CN 109643691A CN 201780049283 A CN201780049283 A CN 201780049283A CN 109643691 A CN109643691 A CN 109643691A
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Abstract
一种集成电路结构可以包括位于由隔离层支撑的正面半导体层上的晶体管。晶体管是第一源极/漏极/体部区域。集成电路结构还可以包括耦合到晶体管的第一源极/漏极/体部区域的背面的凸起的源极/漏极/体部区域。晶体管是凸起的源极/漏极/体部区域,凸起的源极/漏极/体部区域从第一源极/漏极/体部区域的背面朝向支撑隔离层的背面电介质层延伸。集成电路结构可以进一步包括耦合到凸起的源极/漏极/体部区域的背面金属化部。
Description
技术领域
本公开一般地涉及集成电路(IC)。更具体地,本公开涉及用于背面半导体生长的方法和装置。
背景技术
由于成本和功耗考虑,包括高性能双工器的移动射频(RF)芯片设计(例如,移动RF收发器)已经迁移到深亚微米工艺节点。这种移动RF收发器的设计在该深亚微米工艺节点变得复杂。这些移动RF收发器的设计复杂性由添加的电路功能以支持通信增强(诸如载波聚合)而进一步复杂化。对于移动RF收发器的进一步的设计挑战包括模拟/RF性能考虑,这包括失配、噪声和其他性能考虑。这些移动RF收发器的设计包括使用附加的无源器件,例如,以抑制谐振,和/或以执行滤波、旁路和耦合。
这些移动RF收发器的设计可以包括使用绝缘体上硅(SOI)技术。SOI技术利用分层的硅-绝缘体-硅衬底来取代常规的硅衬底,以减少寄生器件电容并提高性能。基于SOI的器件不同于常规的硅制器件,因为硅结位于电隔离体上方,电隔离体通常是掩埋氧化物(BOX)层。然而,厚度减小的BOX层可能不足以减小由硅层上的有源器件与支撑BOX层的衬底的靠近所引起的寄生电容。
SOI层上的有源器件可以包括互补金属氧化物半导体(CMOS)晶体管。遗憾的是,使用SOI技术对晶体管的成功制造可能涉及使用凸起的源极/漏极区域。常规地,凸起的源极/漏极被指定为使得凸起的源极/漏极区域与随后的金属化层之间的接触成为可能。另外,凸起的源极/漏极区域提供了用于载流子行进的通道。作为结果,具有凸起的源极/漏极区域的常规晶体管通常遭受凸起的源极/漏极区域问题。源极/漏极区域问题的特征在于,以晶体管的栅极与源极/漏极区域之间的边缘电容和重叠电容为形式的不想要的寄生电容。
发明内容
一种集成电路结构可以包括位于由隔离层支撑的正面半导体层上的晶体管。晶体管包括第一源极/漏极/体部区域。集成电路结构还可以包括耦合到晶体管的第一源极/漏极/体部区域的背面的凸起的源极/漏极/体部区域。凸起的源极/漏极/体部区域可以从第一源极/漏极/体部区域的背面朝向支撑隔离层的背面电介质层延伸。集成电路结构可以进一步包括耦合到凸起的源极/漏极/体部区域的背面金属化部。
一种构造集成电路结构的方法可以包括:使用由隔离层支撑的正面半导体层来制造晶体管。晶体管包括第一源极/漏极/体部区域。该方法还可以包括:暴露第一源极/漏极/体部区域的背面。该方法可以进一步包括:制造耦合到晶体管的第一源极/漏极/体部区域的背面的凸起的源极/漏极/体部区域。凸起的源极/漏极/体部区域可以从第一源极/漏极/体部区域的背面朝向支撑隔离层的第一背面电介质层延伸。该方法还可以包括:制造耦合到凸起的源极/漏极/体部区域的背面金属化部。
一种集成电路结构可以包括位于由隔离层支撑的正面半导体层上的晶体管。晶体管包括第一源极/漏极/体部区域。集成电路结构还可以包括用于将晶体管的第一源极/漏极/体部区域的背面从隔离层朝向支撑隔离层的背面电介质层延伸的部件。集成电路结构可以进一步包括背面金属化部,该背面金属化部通过延伸部件耦合到第一源极/漏极/体部区域的背面。
一种射频(RF)前端模块可以包括集成RF电路结构。集成RF电路结构可以包括位于由隔离层支撑的正面半导体层上的开关晶体管。开关晶体管包括第一源极/漏极/体部区域和凸起的源极/漏极/体部区域,凸起的源极/漏极/体部区域耦合到开关晶体管的第一源极/漏极/体部区域的背面。凸起的源极/漏极/体部区域从第一源极/漏极/体部区域的背面朝向支撑隔离层的背面电介质层延伸。开关晶体管还包括耦合到凸起的源极/漏极/体部区域的背面金属化部。RF前端模块可以进一步包括耦合到开关晶体管的输出的天线。
这已经相当广泛地概述了本公开的特征和技术优点,以便随后的详细描述可以更好地被理解。下面将描述本公开的附加特征和优点。本领域技术人员应当明白,本公开可以容易地用作修改或设计用于执行本公开的相同目的的其他结构的基础。本领域技术人员还应当认识到,这样的等效构造不脱离所附权利要求中阐述的本公开的教导。当关于附图来考虑时,从随后的描述来看,将更好地理解被相信是本公开的关于其组织和操作方法两者的特性的新型特征、以及进一步的目的和优点。然而,将明确理解的是,附图中的每个附图被提供仅用于说明和描述的目的,并且不旨在作为本公开的界限的定义。
附图说明
为了更完全地理解本公开,现在参考结合附图作出的以下描述。
图1A是根据本公开的一方面的采用双工器的射频(RF)前端(RFFE)模块的示意图。
图1B是根据本公开的各方面的采用用于芯片组的双工器以提供载波聚合的射频(RF)前端(RFFE)模块的示意图。
图2A是根据本公开的一方面的双工器设计的示图。
图2B是根据本公开的一方面的射频(RF)前端模块的示图。
图3A至图3E示出了根据本公开的各方面的在层转移工艺期间的集成射频(RF)电路结构的横截面视图。
图4是根据本公开的各方面的使用层转移工艺制造的集成射频(RF)电路结构的横截面视图。
图5A和图5B图示了根据本公开的各方面的集成电路结构,其中层转移后工艺形成有源器件的背面凸起的源极/漏极区域。
图6A至图6E是图示了根据本公开的各方面的用于制造集成电路结构的工艺的横截面视图,该集成电路结构包括背面凸起的源极/漏极区域。
图7A至图7E是图示了根据本公开的各方面的用于制造集成电路结构的工艺的横截面视图,该集成电路结构包括背面延伸的源极/漏极/体部区域。
图8A至图8E是图示了根据本公开的各方面的工艺的横截面视图,该工艺用于在有源器件的源极/漏极/体部区域与有源器件的背面延伸的源极/漏极/体部区域之间的自对准。
图9是图示了根据本公开的一方面的构造集成电路结构的方法的工艺流程图,该集成电路结构包括具有背面延伸的源极/漏极/体部区域的有源器件。
图10是示出了可以在其中有利地采用本公开的配置的示例性无线通信系统的框图。
图11是图示了根据一种配置的用于半导体组件的电路、布局和逻辑设计的设计工作站的框图。
具体实施方式
下面关于附图阐述的详细描述旨在作为对各种配置的描述,而无意表示可以实践本文所描述的概念的仅有配置。该详细描述包括具体细节以用于提供对各种概念的透彻理解的目的。然而,对本领域技术人员将明显的是,可以没有这些具体细节来实践这些概念。在一些实例中,以框图形式示出了公知的结构和组件,以避免使这样的概念模糊不清。如本文中描述的,术语“和/或”的使用旨在表示“包括性的或”,并且术语“或”的使用旨在表示“排他性的或”。
由于成本和功耗考虑,移动射频(RF)芯片设计(例如,移动RF收发器)已经迁移到深亚微米工艺节点。移动RF收发器的设计复杂性由添加的电路功能以支持通信增强(诸如载波聚合)而进一步复杂化。对于移动RF收发器的进一步的设计挑战包括模拟/RF性能考虑,这包括失配、噪声和其他性能考虑。这些移动RF收发器的设计包括使用无源器件,例如,以抑制谐振、和/或以执行滤波、旁路和耦合。
现代半导体芯片产品的成功制造涉及材料和所采用的工艺之间的相互作用。特别地,在后端制程(BEOL)工艺中形成用于半导体制造的导电材料镀制是工艺流程的越来越具有挑战性的部分。这在维持小特征尺寸方面特别是真实的。维持小特征尺寸的相同挑战也适用于玻璃上无源(POG)技术,其中高性能组件(诸如电感器和电容器)构建在高度绝缘的衬底上,该衬底还可以具有非常低的损耗以支持移动RF收发器设计。
这些移动RF收发器的设计可以包括使用绝缘体上硅(SOI)技术。SOI技术利用分层的硅-绝缘体-硅衬底来取代常规的硅衬底,以减少寄生器件电容并提高性能。基于SOI的器件不同于常规的硅制器件,因为硅结位于电隔离体上方,电隔离体通常是掩埋氧化物(BOX)层,其中BOX层的厚度可以减小。然而,厚度减小的BOX层可能不足以减小由硅层上的有源器件与支撑BOX层的衬底的靠近所引起的寄生电容。另外,SOI层上的有源器件可以包括互补金属氧化物半导体(CMOS)晶体管。
遗憾的是,使用SOI技术对晶体管的成功制造可能涉及使用凸起的源极/漏极区域。常规地,凸起的源极/漏极使得凸起的源极/漏极区域与随后的金属化层之间的接触成为可能。另外,凸起的源极/漏极区域提供了用于载流子行进的通道。具有凸起的源极/漏极区域的常规晶体管通常遭受凸起的源极/漏极区域问题。凸起的源极/漏极区域问题的特征在于,以栅极与源极/漏极区域之间的边缘电容和重叠电容为形式的不想要的寄生电容。另外,常规的CMOS技术限于在有源器件的正面的外延生长。作为结果,本公开的各方面包括层转移后工艺以使得背面半导体沉积/生长成为可能,以消除凸起的源极/漏极区域问题。
本公开的各个方面提供了用于集成电路结构的技术,这些集成电路结构包括具有背面延伸的(凸起的)源极/漏极/体部区域的晶体管。用于集成电路结构的半导体制造的工艺流程可以包括前端制程(FEOL)工艺、中间制程(MOL)(也被称为中端制程(MEOL))工艺、和后端制程(BEOL)工艺。前端制程工艺可以包括形成有源器件(诸如晶体管、电容器、二极管)的工艺步骤集合。FEOL工艺包括离子注入、退火、氧化、化学气相沉积(CVD)或原子层沉积(ALD)、蚀刻、化学机械抛光(CMP)、外延。中间制程工艺可以包括使得晶体管到BEOL互连部的连接成为可能的工艺步骤集合。这些步骤包括硅化和接触形成以及应力引入。后端制程工艺可以包括形成将独立晶体管连结的互连部和形成电路的工艺步骤集合。当前,铜和铝提供互连部,但是随着技术的进一步发展,可以使用其他导电材料。
将理解,术语“层”包括膜,并且将不解释为指示竖直或水平厚度,除非另有陈述。如本文中描述的,术语“衬底”可以指代切割的晶片的衬底,或者可以指代未切割的晶片的衬底。类似地,术语芯片和裸片可以互换使用,除非这种互换将耗尽信任。
本公开的各方面描述了包括具有背面凸起的源极/漏极/体部区域的晶体管的集成电路结构,这些晶体管可以用作用于高品质(Q)因子RF应用的集成射频(RF)电路结构中的天线开关晶体管。在一种配置中,层转移后工艺形成晶体管的背面凸起的源极/漏极/体部区域。层转移后工艺可以在晶体管的源极/漏极区域的背面上形成背面半导体层。背面半导体层可以从隔离层的第一表面延伸到第二表面,其中隔离层的第一表面支撑晶体管。
在这种配置中,层转移后工艺可以包括层沉积后工艺或层生长后工艺,以用于在晶体管的源极/漏极区域的背面上形成背面半导体层。凸起的源极/漏极/体部区域由外延生长的背面半导体材料组成。替换地,凸起的源极/漏极区域可以使用化学气相沉积(CVD)、原子层沉积(ALD)、或其他类似的前端制程制造工艺来形成。在这种配置中,晶体管的背面凸起的源极/漏极区域可以减小如下的寄生电容,该寄生电容与使用常规CMOS工艺制造的正面凸起的源极/漏极区域相关联。也就是说,源极/漏极区域延伸到晶体管的背面有助于防止在晶体管的体部与常规的正面凸起的源极/漏极区域之间的寄生电容的形成。
驱动无线通信行业的一个目标是向消费者提供增加的带宽。在当前一代通信中使用载波聚合提供了用于实现该目标的一种可能的解决方案。通过同时使用两个频率用于单个通信流,载波聚合使得无线载波能够使带宽最大化,该无线载波具有在特定地理区域中的两个频带(例如,700MHz和2GHz)的许可。当增加的数据量被提供给最终用户时,载波聚合实施方式被噪声复杂化,该噪声归因于用于数据传输的频率而在谐波频率处产生。例如,700MHz传输可能在2.1GHz处产生谐波,其干扰在2GHz频率处的数据广播。
对于无线通信,无源器件用于处理载波聚合系统中的信号。在载波聚合系统中,信号利用高频带和低频带两者来通信。在芯片组中,无源器件(例如,双工器)通常被插入在天线和调谐器(或射频(RF)开关)之间以确保高性能。通常,双工器设计包括电感器和电容器。双工器可以通过使用具有高品质(Q)因子的电感器和电容器来获得高性能。高性能双工器也可以通过减少组件之间的电磁耦合来获得,这可以通过组件的几何结构和方向的布置来实现。
图1A是根据本公开的一方面的采用双工器200的射频(RF)前端(RFFE)模块100的示意图。RF前端模块100包括功率放大器102、双信器/滤波器104、以及射频(RF)开关模块106。功率放大器102将(多个)信号放大到某个功率水平以用于传输。双信器/滤波器104根据各种不同的参数(包括频率、插入损耗、抑制或其他类似参数)对输入/输出信号进行滤波。另外,RF开关模块106可以选择输入信号的某些部分以传递到RF前端模块100的其余部分。
RF前端模块100还包括调谐器电路系统112(例如,第一调谐器电路系统112A和第二调谐器电路系统112B)、双工器200、电容器116、电感器118、接地端子115和天线114。调谐器电路系统112(例如,第一调谐器电路系统112A和第二调谐器电路系统112B)包括诸如调谐器、便携式数据输入终端(PDET)和内务(house keeping)模数转换器(HKADC)之类的组件。调谐器电路系统112可以执行针对天线114的阻抗调谐(例如,电压驻波比(VSWR)优化)。RF前端模块100还包括耦合到无线收发器(WTR)120的无源组合器108。无源组合器108组合来自第一调谐器电路系统112A和第二调谐器电路系统112B的检测到的功率。无线收发器120处理来自无源组合器108的信息,并且将该信息提供给调制解调器130(例如,移动台调制解调器(MSM))。调制解调器130向应用处理器(AP)140提供数字信号。
如图1A中示出的,双工器200位于调谐器电路系统112的调谐器组件与电容器116、电感器118和天线114之间。双工器200可以放置在天线114和调谐器电路系统112之间,以提供从RF前端模块100到包括无线收发器120、调制解调器130和应用处理器140的芯片组的高系统性能。双工器200还在高频带频率和低频带频率两者上执行频域复用。在双工器200对输入信号执行其频率复用功能之后,双工器200的输出被馈送到包括电容器116和电感器118的可选LC(电感器/电容器)网络。当需要时,LC网络可以提供用于天线114的额外的阻抗匹配组件。然后,具有特定频率的信号由天线114发射或接收。尽管示出了单个电容器和电感器,但是也设想到多个组件。
图1B是根据本公开的一方面的用于芯片组160以提供载波聚合的包括第一双工器200-1的无线局域网(WLAN)(例如,WiFi)模块170以及包括第二双工器200-2的RF前端模块150的示意图。WiFi模块170包括将天线192可通信地耦合到无线局域网模块(例如,WLAN模块172)的第一双工器200-1。RF前端模块150包括通过双信器180将天线194可通信地耦合到无线收发器(WTR)120的第二双工器200-2。无线收发器120和WiFi模块170的WLAN模块172耦合到调制解调器(MSM,例如,基带调制解调器)130,调制解调器130由电源152通过电力管理集成电路(PMIC)156供电。芯片组160还包括电容器162和164、以及(多个)电感器166以提供信号完整性。PMIC 156、调制解调器130、无线收发器120和WLAN模块172均包括电容器(例如,158、132、122和174)并且根据时钟154操作。芯片组160中的各种电感器组件和电容器组件的几何结构和布置可以减少组件之间的电磁耦合。
图2A是根据本公开的一方面的双工器200的示图。双工器200包括高频带(HB)输入端口212、低频带(LB)输入端口214和天线216。双工器200的高频带路径包括高频带天线开关210-1。双工器200的低频带路径包括低频带天线开关210-2。包括RF前端模块的无线设备可以使用天线开关210和双工器200,以使得用于无线设备的RF输入和RF输出的宽范围频带成为可能。另外,天线216可以是多输入多输出(MIMO)天线。多输入多输出天线将广泛用于无线设备的RF前端,以支持诸如载波聚合之类的特征。
图2B是根据本公开的一方面的RF前端模块250的示图。RF前端模块250包括天线开关(ASW)210和双工器200(或三工器),以使得图2A中指出的宽范围频带成为可能。另外,RF前端模块250包括由衬底202支撑的滤波器230、RF开关220和功率放大器218。滤波器230可以包括各种LC滤波器,其具有沿衬底202布置的电感器(L)和电容器(C),以用于形成双工器、三工器、低通滤波器、巴伦滤波器和/或陷波滤波器,以阻止RF前端模块250中的高次谐波。双工器200可以实施为在系统板201(例如,印刷电路板(PCB)或封装衬底)上的表面安装器件(SMD)。替换地,双工器200可以实施在衬底202上。
在这种配置中,RF前端模块250使用绝缘体上硅(SOI)技术来实施,这有助于减少RF前端模块250中的高次谐波。SOI技术利用分层的硅-绝缘体-硅衬底来取代常规的硅衬底,以减少寄生器件电容并提高性能。基于SOI的器件不同于常规的硅制器件,因为硅结位于电绝缘体(通常是掩埋氧化物(BOX)层)上方。然而,厚度减小的BOX层可能不足以减小由(硅层上的)有源器件与支撑BOX层的衬底之间的靠近所引起的寄生电容。作为结果,如图3A至图3E中示出的,本公开的各方面包括层转移工艺,以进一步将有源器件与衬底分离。
图3A至图3E示出了根据本公开的各方面的在层转移工艺期间的集成射频(RF)电路结构300的横截面视图。如图3A中示出的,RF绝缘体上硅(SOI)器件包括有源器件310,有源器件310位于由牺牲衬底301(例如,块体晶片)支撑的掩埋氧化物(BOX)层320上。RF SOI器件还包括互连部350,互连部350在第一电介质层306内耦合到有源器件310。如图3B中示出的,处理衬底302被接合到RF SOI器件的第一电介质层306。另外,牺牲衬底301被去除。使用层转移工艺对牺牲衬底301的去除通过增加电介质厚度而使得高性能、低寄生的RF器件成为可能。也就是说,RF SOI器件的寄生电容与电介质厚度成比例,电介质厚度决定了有源器件310和处理衬底302之间的距离。
如图3C中示出的,一旦处理衬底302被固定并且牺牲衬底301被去除,RF SOI器件就被翻转。如图3D中示出的,层转移后金属化工艺使用例如普通的互补金属氧化物半导体(CMOS)工艺被执行。如图3E中示出的,集成RF电路结构300通过以下来完成:沉积钝化层、打开接合焊盘、沉积再分布层、以及形成导电凸块/柱,以使得集成RF电路结构300到系统板(例如,印刷电路板(PCB))的接合成为可能。
再次参考图3A,RF SOI器件可以包括在牺牲衬底301和BOX层320之间的富陷阱层。另外,牺牲衬底301可以利用处理衬底来取代,并且BOX层320的厚度可以增加以改进谐波。虽然RF SOI器件的该布置相对于纯硅或SOI实施方式可以提供改进的谐波,但是RF SOI器件被来自处理衬底的非线性响应所限制,尤其是当使用硅处理衬底时。也就是说,在图3A中,相对于图3B至图3E中示出的配置,BOX层320的增加的厚度没有在有源器件310和牺牲衬底301之间提供足够的距离。此外,RF SOI器件中的有源器件310的体部可能不被连结。
图4是根据本公开的各方面的使用层转移工艺制造的集成RF电路结构400的横截面视图。代表性地,集成RF电路结构400包括有源器件410,有源器件410具有形成在隔离层420上的栅极、体部、和源极/漏极区域。在绝缘体上硅(SOI)实施方式中,隔离层420是掩埋氧化物(BOX)层,并且体部和源极/漏极区域由SOI层形成,该SOI层包括由BOX层支撑的浅沟槽隔离(STI)区域。
集成RF电路结构400还包括耦合到有源器件410的源极/漏极区域的中端制程(MEOL)/后端制程(BEOL)互连部。如本文中描述的,MEOL层/BEOL层被称为正面层。相比之下,支撑隔离层420的层在本文中可以称为背面层。根据这种命名,正面互连部450通过正面接触部412耦合到有源器件410的源极/漏极区域,并且布置在正面电介质层406中。另外,处理衬底402直接耦合到正面电介质层406。在这种配置中,背面电介质440与隔离层420相邻并且可能支撑隔离层420。另外,背面金属化部430耦合到正面互连部450。
如图4中示出的,层转移工艺在有源器件410和处理衬底402之间提供增加的间隔,以改进集成RF电路结构400的谐波。虽然层转移工艺使得高性能、低寄生的RF器件成为可能,但是集成RF电路结构400可能遭受浮体效应。因此,通过使用后转移金属化部来提供对有源器件410的背面的访问,以连结有源器件410的体部区域,集成RF电路结构400的性能可以进一步被改进。
本公开的各个方面提供了用于在集成射频(RF)集成结构的有源器件的背面上的层转移后沉积/生长工艺的技术。相比之下,在前端制程(FEOL)工艺期间形成的对有源器件的访问常规地在中端制程(MEOL)处理期间被提供,中端制程处理提供有源器件的栅极和源极/漏极区域与后端制程(BEOL)互连层(例如,M 1、M2等)之间的接触。本公开的各方面涉及用于形成晶体管的背面延伸的(凸起的)源极/漏极/体部区域的层转移后生长/沉积工艺,这些晶体管可以用作用于高品质(Q)因子RF应用的集成射频(RF)电路结构中的天线开关晶体管。其他应用包括低功率放大器模块、低噪声放大器和天线分集开关中的有源器件。
图5A是根据本公开的各方面的集成电路结构500的横截面视图,其中层转移后工艺在有源器件(例如,晶体管)的源极/漏极(S/D)区域的背面上执行。代表性地,集成电路结构500包括有源器件510,有源器件510具有形成在隔离层520上的栅极、体部、和源极/漏极(S/D)区域。对于绝缘体上硅(SOI)实施方式,隔离层520可以是掩埋氧化物(BOX)层,其中体部和源极/漏极区域由SOI层形成。在这种配置中,浅沟槽隔离(STI)区域也由BOX层支撑。
集成RF电路结构500包括布置在正面电介质层506中的正面金属化部570(例如,第一BEOL互连部(M1))。正面金属化部凭借过孔560耦合到背面金属化部550的第三部分550-3,其中背面金属化部550布置在背面电介质层540中。另外,有源器件510的栅极包括栅极接触部512,其可以由正面硅化物层组成。另外,处理衬底502耦合到正面电介质层506。背面电介质层540与隔离层520相邻并且可能支撑隔离层520。在这种配置中,层转移后金属化工艺形成背面金属化部550。
在本公开的各方面,层转移后工艺用于在有源器件510的源极/漏极区域的背面上提供背面半导体层。在本公开的各方面,背面半导体层可以被沉积为非晶半导体层。替换地,背面半导体层可以作为层转移后生长工艺的一部分而外延地生长。一旦形成,背面半导体层可以可选地经历后沉积退火工艺(例如,低温或短时局部的激光退火),以形成凸起的源极/漏极(S/D)区域530。在这种配置中,背面凸起的源极/漏极区域530从有源器件510的源极/漏极区域的背面延伸到隔离层520中。一旦形成,背面接触部532(例如,背面硅化物层)可以沉积在距源极/漏极区域的正面的远端处的背面凸起的源极/漏极区域530上。层转移后金属化工艺然后被执行,以将背面金属化部550的第一部分550-1和第二部分550-2耦合到有源器件510的背面凸起的源极/漏极区域530的背面接触部532。如图5A中示出的,正面金属化部570被布置在距背面金属化部550的远端。
图5B是根据本公开的各方面的集成电路结构580的横截面视图,其中层转移后工艺也在有源器件510(例如,晶体管)的源极/漏极(S/D)区域516的背面上执行。如将认识到的,集成电路结构580的配置类似于图5A的集成电路结构500的配置。然而,在图5B中示出的配置中,有源器件510仅包括背面凸起的源极/漏极区域530之一。替代地,背面接触部582直接位于有源器件510的源极/漏极区域516的背面上。另外,背面金属化部550的第二部分550-2耦合到有源器件510的源极/漏极区域516的背面接触部582。
再次参考图5A,背面凸起的源极/漏极区域530被提供在隔离层520中,并且被布置成使得与背面金属化部550的接触成为可能。有源器件510的源极/漏极区域的延伸有助于阻止寄生电容在有源器件510的体部与常规的正面凸起的源极/漏极区域之间的形成。在这种配置中,层转移后工艺可以包括用于形成背面凸起的源极/漏极区域530的层沉积后工艺或层生长后工艺。在这种配置中,背面凸起的源极/漏极区域530可以减少与使用常规CMOS工艺制造的凸起的源极/漏极区域相关联的寄生电容。
根据本公开的各方面,处理衬底502可以由半导体材料(诸如硅)组成。在这种配置中,处理衬底502可以包括至少一个其他有源器件。替换地,处理衬底502可以是无源衬底,以通过减小寄生电容来进一步改进谐波。在这种配置中,处理衬底502可以包括至少一个其他无源器件。如本文中描述的,术语“无源衬底”可以指代切割的晶片或面板的衬底,或者可以指代未切割的晶片/面板的衬底。在一种配置中,无源衬底由玻璃、空气、石英、蓝宝石、高电阻率硅、或其他类似的无源材料组成。无源衬底也可以是无芯衬底。
图6A至图6E是图示了根据本公开的各方面的用于制造集成电路结构的工艺的横截面视图,该集成电路结构包括背面延伸的源极/漏极区域。如图6A中示出的,集成电路结构600以与图5A中示出的集成电路结构500的配置相类似的配置被示出。然而,在图6A中示出的配置中,在形成有源器件510(510-1和510-2)之后,层转移工艺被执行以将处理衬底502接合到正面电介质层506。如图6B中示出的,层转移后工艺开始于背面电介质层540的沉积。尽管示出了单个层,但是应当认识到可以沉积多个电介质层。
如图6C中示出的,层转移后工艺继续于背面电介质层540和隔离层520的图案化和蚀刻,以暴露有源器件510的源极/漏极区域的背面。在图6D中,层转移后沉积/生长工艺被执行以制造背面凸起的源极/漏极区域530。在图6E中,层转移后金属化工艺被执行,以通过背面接触部532将背面金属化部550耦合到背面凸起的源极/漏极区域530。另外,背面金属化部550的第五部分550-5凭借过孔560耦合到正面金属化部570。在这种配置中,背面金属化部550的第三部分550-3耦合到背面凸起的源极/漏极区域530之一的背面接触部532,并且背面金属化部550的第四部分550-4耦合到第二有源器件510-2的背面凸起的源极/漏极区域530之一的背面接触部532。
在生长工艺中可以使用不同的材料来对有源器件施加压力。例如,PFET器件可以利用锗生长被施加应力,在一种配置中高达40%。NMOS器件可以使用例如碳掺杂的硅被施加应力,其中碳的百分比不多于3%至百分之四。碳的该百分比阻止硅中的位错。应当认识到,凸起的体部区域也可以包括应力源。
图7A至图7E是图示了根据本公开的各方面的用于制造集成电路结构的工艺的横截面视图,该集成电路结构包括背面延伸的源极/漏极/体部区域。如图7A中示出的,集成电路结构700以与图5A中示出的集成电路结构500的配置相类似的配置被示出。然而,在图7A中示出的配置中,在形成有源器件510(510-1和510-2)之后,层转移工艺被执行以将处理衬底502接合到正面电介质层506。另外,正面金属化部570的第一部分570-1将第一有源器件510-1的源极/漏极区域的正面接触部514耦合到第二有源器件510-2的栅极接触部512。此外,正面金属化部570的第二部分570-2将第二有源器件510-2的源极/漏极区域的正面接触部514耦合到过孔560。
如图7B中示出的,层转移后工艺也开始于背面电介质层540的沉积。如图7C中示出的,层转移后工艺也继续于背面电介质层540和隔离层520的图案化和蚀刻,以暴露第一有源器件510-1的源极/漏极区域的背面。在本公开的该方面,层转移后工艺暴露第二有源器件510-2的体部。在图7D中,层转移后沉积/生长工艺被执行,以制造背面凸起的源极/漏极区域530和背面凸起的体部区域590。
在图7E中,层转移后金属化工艺被执行,以通过背面接触部532将背面金属化部550耦合到背面凸起的源极/漏极区域530。另外,背面金属化部550的第四部分550-4凭借过孔560耦合到正面金属化部570的第二部分。在这种配置中,背面金属化部550的第三部分550-3耦合到背面凸起的体部区域590的背面接触部592。在本公开的该方面,背面凸起的体部区域590被掺杂有与背面凸起的源极/漏极区域530的掺杂物不同的掺杂物。另外,第一有源器件510-1的背面凸起的体部区域590被掺杂有与第二有源器件510-2的背面凸起的体部区域590的掺杂物不同的掺杂物。
图8A至图8E是图示了根据本公开的各方面的工艺的横截面视图,该工艺用于有源器件的源极/漏极/体部区域与有源器件的背面延伸的源极/漏极/体部区域之间的自对准。如图8A中示出的,集成电路结构800以与图7A中示出的集成电路结构700的配置相类似的配置被示出。然而,在图8A中示出的配置中,在形成有源器件510(510-1和510-2)之后将处理衬底502接合到正面电介质层506的层转移工艺未被示出。另外,图8D中示出的集成电路结构的配置还包括将第一有源器件510-1的源极/漏极区域的正面接触部514耦合到第二有源器件510-2的栅极接触部512的正面金属化部570的第一部分570-1。此外,正面金属化部570的第二部分570-2将第二有源器件510-2的源极/漏极区域的正面接触部514耦合到过孔560。
如图8B中示出的,离子注入工艺被执行,以通过在背面电介质层540和隔离层520中注入离子,将杂质注入到背面电介质层540中。该注入从集成电路结构800的正面执行。特定掺杂物(例如,高剂量硼)可以用于破坏掩埋氧化物层(在其中产生缺陷)。如图8C中示出的,离子注入工艺被有源器件510的栅极阻挡。作为结果,注入的缺陷通常被限制到背面电介质层540和隔离层内的如下区域:这些区域靠近有源器件510的源极/漏区区域。
如图8D中示出的,层转移后掩模工艺通过以下被执行:沉积光致抗蚀剂594,并且暴露例如蚀刻不足的半导体(例如,硅(Si))层内的所注入的缺陷。如图8E中示出的,该工艺继续于对背面电介质层540和隔离层520的蚀刻,以暴露第一有源器件510-1的源极/漏极区域的背面和第二有源器件510-2的源极/漏极区域的背面。在本公开的该方面,注入的缺陷使得有源器件510的源极/漏极/体部区域与背面延伸的源极/漏极/体部区域之间的自对准成为可能。也就是说,背面蚀刻未到达栅极。替换地,注入的缺陷可以提供蚀刻停止层,并且降低蚀刻率以支撑背面凸起的源极/漏极/体部区域。
图9是图示了根据本公开的一方面的构造集成电路结构的方法900的工艺流程图,该集成电路结构包括具有背面延伸的源极/漏极/体部区域的有源器件。在框902中,晶体管使用由隔离层支撑的正面半导体层被制造。例如,如图6A中示出的,有源器件310使用由隔离层(例如,掩埋氧化物(BOX)层)支撑的正面半导体层(例如,绝缘体上硅(SOI)层)被制造。在图6A至图6E中示出的配置中,正面金属化部被制造在有源器件上的正面电介质层中。例如,如图6A中示出的,正面金属化部570耦合到正面过孔560,正面过孔560延伸穿过浅沟槽隔离(STI)区域和隔离层520。该工艺的用于制造晶体管的这一部分在层转移工艺之前执行。
例如,层转移工艺被执行,其中处理衬底502被键合到正面电介质层506,这如图6A中示出。层转移工艺还包括牺牲衬底的去除。如图3B中示出的,层转移工艺包括牺牲衬底301的去除。在本公开的该方面,凸起的背面源极/漏极/体部区域的制造作为层转移后工艺的一部分被执行。
再次参考图9,在框904中,晶体管的第一源极/漏极/体部区域的背面被暴露。例如,如图6B中示出的,层转移后的凸起的源极/漏极/体部形成工艺可以开始于背面电介质层540在隔离层520上的沉积。如图6C中示出的,有源器件510的源极/漏极区域的背面被暴露。在框906中,凸起的源极/漏极/体部区域被制造。例如,如图6D示出的,凸起的源极/漏极(S/D)区域耦合到有源器件510的源极/漏极区域的背面。凸起的源极/漏极区域可以从源极/漏极区域的背面朝向支撑隔离层520的背面电介质层540延伸。替换地,第二源极/漏极/体部区域的背面可以被暴露,以使得另一凸起的源极/漏极/体部区域的形成成为可能。
根据本公开的各方面,凸起的源极/漏极/体部区域可以作为非晶沉积工艺的一部分而外延地生长或制造。例如,如图6D中示出的,外延生长工艺可以包括:在有源器件510的凸起的源极/漏极区域的暴露的背面上选择性地生长背面半导体层。该外延生长工艺还包括:使背面半导体层经历退火工艺,以形成凸起的源极/漏极区域。一旦形成凸起的源极/漏极区域,背面电介质层540的表面和/或有源器件510的凸起的源极/漏极区域的蚀刻被执行。通过提供远离集成电路结构500的正面延伸的背面凸起的源极/漏极区域,避免了晶体管栅极与常规凸起的源极/漏极区域之间的寄生电容。
根据本公开的各方面,描述了层转移后生长/沉积工艺用于形成背面凸起的源极/漏极/体部区域。层转移后生长工艺可以涉及预清洁部分、生长部分和沉积后退火。沉积后退火可以是低温退火(例如,低于350°)或短时局部激光退火。另外,背面凸起的源极/漏极/体部区域可以具有或可以不具有单晶体结构。例如,背面凸起的源极/漏极/体部区域可以通过完全非晶沉积形成,随后是固相外延退火以形成单晶体结构。替换地,在不需要单晶材料时的情况下,多晶硅、硅合金、或其他类似的半导体化合物可以被沉积,以提供背面半导体层。
当外延生长工艺被用来形成背面半导体层时,低温外延生长可以使用丙硅烷来执行。归因于用于增强H(氢)解吸的特定生长机制,丙硅烷可以允许背面半导体层(例如,硅)在低于350℃的较低温度下的生长。相比之下,在低于500℃的温度下生长的常规半导体层是有缺陷的,而不论所使用的载气、压力和前体流。另外,外延生长的背面半导体层的厚度可以高于或低于该层生长在其上的晶片的表面。
在图9的框908中,背面金属化部被制造以耦合到凸起的源极/漏极区域。如图6E中示出的,背面接触部532被沉积在背面凸起的源极/漏极区域530上。另外,第二背面电介质层540-2被沉积在背面接触部532和第一背面电介质层540-1上。一旦被沉积,第二背面电介质层540-2就根据背面接触部532被图案化。第二背面电介质层540-2接着被蚀刻(例如,干式等离子体蚀刻和清洁工艺),以暴露背面接触部532的一部分。背面金属化部550然后被沉积在背面接触部532的暴露部分上,以接触有源器件510的源极/漏极区域。
根据本公开的另一方面,描述了一种集成电路结构,其包括在由隔离层支撑的正面半导体层上的晶体管。该晶体管包括第一源极/漏极/体部区域。集成电路结构还可以包括用于将晶体管的第一源极/漏极/体部区域的背面从隔离层朝向支撑隔离层的背面电介质层延伸的部件。集成电路结构可以进一步包括通过延伸部件耦合到第一源极/漏极/体部区域的背面的背面金属化部。该延伸部件可以是图5A和图5B中示出的凸起的源极/漏极区域。该延伸部件也可以是图7D和图7E中示出的凸起的体部区域。在另一方面,前述的部件可以是被配置为执行通过前述部件记载的功能的任何模块或任何装置。
遗憾的是,使用绝缘体上硅(SOI)技术对晶体管的成功制造可能涉及使用凸起的源极/漏极区域。常规地,凸起的源极/漏极使得凸起的源极/漏极区域与随后的金属化层之间的接触成为可能。另外,凸起的源极/漏极区域提供了用于载流子行进的通道。遗憾的是,具有凸起的源极/漏极区域的常规晶体管通常遭受凸起的源极/漏极区域问题。另外,常规的CMOS技术限于有源器件的正面上的外延生长。作为结果,本公开的各方面包括层转移后工艺,以使得背面半导体沉积/生长成为可能,以消除凸起的源极/漏极区域问题。
本公开的各方面描述了包括具有背面凸起的源极/漏极/体部区域的晶体管的集成电路结构,这些晶体管可以用作用于高品质(Q)因子RF应用的集成射频(RF)电路结构中的天线开关晶体管。在一种配置中,层转移后金属化被用于形成晶体管的背面凸起的源极/漏极/体部区域。层转移后工艺可以在晶体管的源极/漏极区域的背面上形成背面半导体层。背面半导体层可以从隔离层的第一表面延伸到第二表面,其中隔离层的第一表面支撑晶体管。
在这种配置中,层转移后工艺可以包括层沉积后工艺或层生长后工艺,用于在晶体管的源极/漏极区域的背面上形成背面半导体层。随后的退火工艺被应用到半导体层,以形成晶体管的背面凸起的源极/漏极区域。在这种配置中,晶体管的背面凸起的源极/漏极区域可以减小寄生电容,该寄生电容与使用常规的CMOS工艺制造的正面凸起的源极/漏极区域相关联。也就是说,源极/漏极区域延伸到晶体管的背面有助于阻止寄生电容在晶体管的体部和常规的正面凸起的源极/漏极区域之间的形成。
图10是示出了示例性无线通信系统1000的框图,其中可以有利地采用本公开的一方面。出于说明的目的,图10示出了三个远程单元1020、1030和1050以及两个基站1040。将认识到,无线通信系统可以具有更多的远程单元和基站。远程单元1020、1030和1050包括IC器件1025A、1025C和1025B,它们包括所公开的背面半导体生长。将认识到,其他设备也可以包括所公开的背面半导体生长,诸如基站、交换设备和网络装备。图10示出了从基站1040到远程单元1020、1030和1050的前向链路信号1080、以及从远程单元1020、1030和1050到基站1040的反向链路信号1090。
在图10中,远程单元1020被示出为移动电话,远程单元1030被示出为便携式计算机,并且远程单元1050被示出为无线本地环路系统中的固定位置远程单元。例如,远程单元可以是移动电话、手持个人通信系统(PCS)单元、诸如个人数字助理(PDA)之类的便携式数据单元、启用GPS的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、诸如仪表读取装备之类的固定位置数据单元、或者存储或取回数据或计算机指令的其他通信设备、或其组合。尽管图10图示了根据本公开的各方面的远程单元,但是本公开不限于这些示例性的所图示的单元。本公开的各方面可以适当地在包括所公开的RF器件的许多设备中被采用。
图11是图示了用于半导体组件(诸如上文所公开的RF器件)的电路、布局和逻辑设计的设计工作站的框图。设计工作站1100包括硬盘1101,其包含操作系统软件、支持文件、以及设计软件,诸如Cadence或OrCAD。设计工作站1100还包括显示器1102,以促进电路1110或半导体组件1112(诸如RF器件)的设计。存储介质1104被提供用于有形地存储电路设计1110或半导体组件1112。电路设计1110或半导体组件1112可以按诸如GDSII或GERBER之类的文件格式存储在存储介质1104上。存储介质1104可以是CD-ROM、DVD、硬盘、闪存、或其他适当的设备。此外,设计工作站1100包括驱动装置1103,以用于接受来自存储介质1104的输入或将输出写入存储介质1104。
存储介质1104上记录的数据可以指定逻辑电路配置、用于光刻掩模的图案数据、或用于串行写入工具(诸如电子束光刻)的掩模图案数据。数据可以进一步包括逻辑验证数据,诸如与逻辑仿真相关联的时序图或网络电路。在存储介质1104上提供数据通过减少用于设计半导体晶片的工艺数目,而促进电路设计1110或半导体组件1112的设计。
对于固件和/或软件实施方式,方法可以利用执行本文描述的功能的模块(例如,过程、功能等)来实施。有形地体现指令的机器可读介质可以在实施本文描述的方法时使用。例如,软件代码可以存储在存储器中并且由处理器单元执行。存储器可以实施在处理器单元内或者在处理器单元外部。如本文所使用的,术语“存储器”指代长期、短期、易失性、非易失性、或其他存储器的类型,并且不限于存储器的特定类型或存储器的特定数目,或存储器存储在其上的介质的类型。
如果实施在固件和/或软件中,则功能可以作为一个或多个指令或代码存储在计算机可读介质上。示例包括利用数据结构编码的计算机可读介质和利用计算机程序编码的计算机可读介质。计算机可读介质包括物理计算机存储介质。存储介质可以是可以由计算机访问的可用介质。通过示例而非限制的方式,这种计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储装置、磁盘存储装置或其他磁存储设备、或者如下的其他介质,其可以用于以指令或数据结构的形式存储所期望的程序代码,并且其可以由计算机访问;如本文所使用的,盘和碟包括紧致碟(CD)、激光碟、光碟、数字通用碟(DVD)、软盘和蓝光碟,其中盘通常磁性地再现数据,而碟利用激光光学地再现数据。上述的组合也应当被包括在计算机可读介质的范围内。
除了存储在计算机可读介质上之外,指令和/或数据可以作为通信装置中包括的传输介质上的信号被提供。例如,通信装置可以包括具有指示指令和数据的信号的收发器。指令和数据被配置为使一个或多个处理器实施权利要求中概述的功能。
尽管已经详细描述了本公开及其优点,但是应当理解,不脱离由所附权利要求限定的本公开的技术,本文中可以作出各种改变、替换和更改。例如,关系术语(诸如“上方”和“下方”)相对于衬底或电子设备被使用。当然,如果衬底或电子设备被倒置,则上方变为下方,并且反之亦然。另外,如果侧向取向,则上方和下方可以指代衬底或电子设备的侧面。此外,本申请的范围不旨在限于说明中描述的过程、机器、制造品和物质组成、部件、方法和步骤的特定配置。如本领域普通技术人员从本公开中将容易明白的,根据本公开,可以利用执行与本文描述的对应配置基本上相同的功能或实现基本相同的结果的目前已有的或以后开发的过程、机器、制造品、物质组成、部件、方法或步骤。因此,所附权利要求意图为在其范围内包括这样的过程、机器、制造品、物质组成、部件、方法或步骤。
Claims (27)
1.一种集成电路结构,包括:
晶体管,位于由隔离层支撑的正面半导体层上,所述晶体管包括第一源极/漏极/体部区域;
凸起的源极/漏极/体部区域,耦合到所述晶体管的所述第一源极/漏极/体部区域的背面,所述凸起的源极/漏极/体部区域从所述第一源极/漏极/体部区域的所述背面朝向支撑所述隔离层的背面电介质层延伸;以及
背面金属化部,耦合到所述凸起的源极/漏极/体部区域。
2.根据权利要求1所述的集成电路结构,其中所述凸起的源极/漏极/体部区域由外延生长的背面半导体材料组成。
3.根据权利要求1所述的集成电路结构,还包括耦合到所述晶体管的第二源极/漏极/体部区域的正面金属化部,所述正面金属化部在距所述背面金属化部的远端。
4.根据权利要求3所述的集成电路结构,其中所述正面金属化部包括后端制程(BEOL)互连部,所述BEOL互连部耦合到所述晶体管的所述第二源极/漏极/体部区域上的正面接触部,所述BEOL互连部位于正面电介质层内。
5.根据权利要求1所述的集成电路结构,其中所述晶体管包括射频(RF)开关。
6.根据权利要求1所述的集成电路结构,其中所述凸起的源极/漏极/体部区域掺杂有与所述晶体管的所述第一源极/漏极/体部区域的掺杂物不同的掺杂物。
7.根据权利要求1所述的集成电路结构,其中所述凸起的源极/漏极/体部区域与所述晶体管的所述第一源极/漏极/体部区域自对准。
8.根据权利要求1所述的集成电路结构,其中所述凸起的源极/漏极/体部区域延伸穿过所述隔离层到所述背面电介质层。
9.根据权利要求1所述的集成电路结构,被集成到射频(RF)前端模块中,所述RF前端模块被并入到以下至少一项中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、固定位置数据单元、移动电话、以及便携式计算机。
10.一种构造集成电路结构的方法,包括:
使用由隔离层支撑的正面半导体层来制造晶体管,所述晶体管包括第一源极/漏极/体部区域;
暴露所述第一源极/漏极/体部区域的背面;
制造耦合到所述晶体管的所述第一源极/漏极/体部区域的所述背面的凸起的源极/漏极/体部区域,所述凸起的源极/漏极/体部区域从所述第一源极/漏极/体部区域的所述背面朝向支撑所述隔离层的第一背面电介质层延伸;以及
制造耦合到所述凸起的源极/漏极/体部区域的背面金属化部。
11.根据权利要求10所述的方法,其中制造所述凸起的源极/漏极/体部区域包括:
将离子至少注入支撑所述隔离层的所述第一背面电介质层中,其中所述注入从所述集成电路结构的正面执行;
根据所述第一背面电介质层中的注入的缺陷,将所述第一背面电介质层图案化,所述注入的缺陷靠近所述晶体管的所述第一源极/漏极/体部区域的背面;以及
通过所述第一背面电介质层和所述隔离层,暴露所述晶体管的所述第一源极/漏极/体部区域的所述背面。
12.根据权利要求10所述的方法,其中制造所述凸起的源极/漏极/体部区域包括:在所述晶体管的所述第一源极/漏极/体部区域的所述背面上选择性地生长背面半导体层。
13.根据权利要求12所述的方法,还包括:对所述背面半导体层进行退火,以形成所述凸起的源极/漏极/体部区域。
14.根据权利要求10所述的方法,还包括:
在所述凸起的源极/漏极/体部区域上沉积背面硅化物;以及
在所述背面硅化物和所述第一背面电介质层上沉积第二背面电介质层。
15.根据权利要求10所述的方法,其中制造所述凸起的源极/漏极/体部区域包括:在所述第一源极/漏极/体部区域的所述背面的暴露部分上沉积背面半导体层。
16.根据权利要求10所述的方法,还包括:将所述集成电路结构集成到射频(RF)前端模块中,所述RF前端模块被并入到以下至少一项中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、固定位置数据单元、移动电话、以及便携式计算机。
17.一种集成电路结构,包括:
晶体管,位于由隔离层支撑的正面半导体层上,所述晶体管包括第一源极/漏极/体部区域;
用于将所述晶体管的所述第一源极/漏极/体部区域的背面从所述隔离层朝向支撑所述隔离层的背面电介质层延伸的部件;以及
背面金属化部,通过所述延伸部件耦合到第一源极/漏极/体部区域的所述背面。
18.根据权利要求17所述的集成电路结构,还包括耦合到所述晶体管的第二源极/漏极/体部区域的正面金属化部,所述正面金属化部在距所述背面金属化部的远端。
19.根据权利要求18所述的集成电路结构,其中所述正面金属化部包括后端制程(BEOL)互连部,所述BEOL互连部耦合到所述晶体管的所述第二源极/漏极/体部区域上的正面接触部,所述BEOL互连部位于正面电介质层内。
20.根据权利要求17所述的集成电路结构,其中所述晶体管包括RF开关。
21.根据权利要求17所述的集成电路结构,其中所述延伸部件与所述晶体管的所述第一源极/漏极/体部区域自对准。
22.根据权利要求17所述的集成电路结构,被集成到射频(RF)前端模块中,所述RF前端模块被并入到以下至少一项中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、固定位置数据单元、移动电话、以及便携式计算机。
23.一种射频(RF)前端模块,包括:
集成RF电路结构,包括位于由隔离层支撑的正面半导体层上的开关晶体管,所述开关晶体管包括:第一源极/漏极/体部区域;凸起的源极/漏极/体部区域,耦合到所述开关晶体管的所述第一源极/漏极/体部区域的背面,其中所述凸起的源极/漏极/体部区域从所述第一源极/漏极/体部区域的背面朝向支撑所述隔离层的背面电介质层延伸;以及背面金属化部,耦合到所述凸起的源极/漏极/体部区域;以及
天线,耦合到开关晶体管的输出。
24.根据权利要求23所述的集成RF电路结构,其中所述凸起的源极/漏极/体部区域由外延生长的背面半导体材料组成。
25.根据权利要求23所述的集成RF电路结构,其中所述凸起的源极/漏极/体部区域掺杂有与所述开关晶体管的所述第一源极/漏极/体部区域的掺杂物不同的掺杂物。
26.根据权利要求23所述的集成RF电路结构,其中所述凸起的源极/漏极/体部区域延伸穿过所述隔离层到所述背面电介质层。
27.根据权利要求23所述的RF前端模块,被并入到以下至少一项中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、固定位置数据单元、移动电话、以及便携式计算机。
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CN109643691B (zh) | 2023-09-01 |
BR112019002343A2 (pt) | 2019-06-18 |
JP7158373B2 (ja) | 2022-10-21 |
BR112019002343B1 (pt) | 2023-04-04 |
CA3030289A1 (en) | 2018-02-15 |
WO2018031175A1 (en) | 2018-02-15 |
US9780210B1 (en) | 2017-10-03 |
EP3497715A1 (en) | 2019-06-19 |
KR102505236B1 (ko) | 2023-03-02 |
JP2019525478A (ja) | 2019-09-05 |
KR20190036533A (ko) | 2019-04-04 |
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