JP7074683B2 - 導電パターン構造及びその製造方法、アレイ基板、表示装置 - Google Patents
導電パターン構造及びその製造方法、アレイ基板、表示装置 Download PDFInfo
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- JP7074683B2 JP7074683B2 JP2018549775A JP2018549775A JP7074683B2 JP 7074683 B2 JP7074683 B2 JP 7074683B2 JP 2018549775 A JP2018549775 A JP 2018549775A JP 2018549775 A JP2018549775 A JP 2018549775A JP 7074683 B2 JP7074683 B2 JP 7074683B2
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Description
該電解セル反応:
陽極:2Cl-1-2e-=Cl2(g)
陰極:Ni2++2e-=Ni
上記電気化学反応によって、銅金属単体を陰極とした電極にニッケル金属単体が形成され、すなわち、第1金属パターン(銅金属単体)に第2金属パターン(ニッケル金属単体)が形成される。
該電解セル反応:
陽極:Ni-2e-=Ni2+
陰極:Ni2++2e-=Ni
上記電気化学反応によって、銅金属単体を陰極とした電極にニッケル金属単体が形成され、すなわち、第1金属パターン(銅金属単体)に第2金属パターン(ニッケル金属単体)が形成される。
該電解セル反応:
陽極:2Cl-1-2e-=Cl2(g)
陰極:Ni2++2e-=Ni
上記電気化学反応によって、銅金属単体を陰極とした電極にニッケル金属単体が形成され、すなわち、第1金属パターン(銅金属単体)に第2金属パターン(ニッケル金属単体)が形成される。
該電解セル反応:
陽極:Ni-2e-=Ni2+
陰極:Ni2++2e-=Ni
上記電気化学反応によって、銅金属単体を陰極とした電極にニッケル金属単体が形成され、すなわち、第1金属パターン(銅金属単体)に第2金属パターン(ニッケル金属単体)が形成される。
(1)本開示の少なくとも一実施例による導電パターン構造では、第1金属パターンにその側面に被覆された第2金属パターンを形成することによって、第1金属パターンの側面の酸化を防止し、それにより、第1金属パターンの導電性低下の問題を避け、さらに製品の歩留まり低下の問題を避ける。
(2)本開示の少なくとも一実施例による導電パターン構造は、生産装置や外部環境への要件を低下させ、それにより導電パターン構造の製造プロセスの複雑性を低減させる。
(3)本開示の少なくとも一実施例による導電パターン構造は、生産コストを削減させる。
(1)本開示の実施例の図面中、本開示の実施例に関する構造だけが示されて、ほかの構造については通常の設計を参照すればよい。
(2)明瞭さから、本開示の実施例を説明する図中、層又は領域の厚さが拡大又は縮小されるものであり、すなわち、これら図面は実際な比例に応じて作成するものではない。 なお、たとえば、層、膜、領域又は基板のような素子が別の素子「上」又は「下」に位置すると記載される場合、該素子は別の素子「上」又は「下」に「直接」に位置し、又は、中間素子が存在する。
(3)矛盾がない場合、本開示の実施例及び実施例における特徴は互いに組み合わせて、新しい実施例を構成することができる。
30 アレイ基板
40 表示装置
101 第1緩衝層
102 低抵抗金属
103 第2緩衝層
201 第1金属パターン
202 第2金属パターン
203 緩衝層
204 第3金属パターン
301 ベース基板
302 ゲート
303 ゲート絶縁層
304 活性層
305 第1ソース・ドレイン電極
306 第2ソース・ドレイン電極
307 有機絶縁層
308 パッシベーション層
309 第1電極
310 第2電極
311 共通電極ライン
312 第1絶縁層
Claims (16)
- 導電パターン構造であって、
第1金属パターンと、第2金属パターンと、前記第1金属パターンの第1の主面にある緩衝層と、前記緩衝層から離れる前記第1金属パターンの第2の主面にある第3金属パターンと、を含み、
前記第2金属パターンは、前記第1金属パターンの側面、前記第3金属パターンの側面及び前記緩衝層の側面とのみ接触しており、前記第2金属パターンは、前記第1金属パターンの第1の主面及び第2の主面と接触しておらず、
前記第1金属パターンの金属材料の活性が前記第2金属パターンの金属材料の活性より弱い、導電パターン構造。 - 前記第1金属パターンの金属材料は、銅系金属及び銀系金属のうちの少なくとも1種を含む、請求項1に記載の導電パターン構造。
- 前記第2金属パターンの金属材料は、ニッケル、モリブデン、ニオブ、アルミニウム及びチタンのうちの少なくとも1種を含む、請求項1又は2に記載の導電パターン構造。
- 前記銅系金属は、Cu、CuMo、CuTi、CuMoW、CuMoNb又はCuMoTiを含み、前記銀系金属は、Ag、AgMo、AgTi、AgMoW、AgMoNb又はAgMoTiを含む、請求項2に記載の導電パターン構造。
- 前記銅系金属において、銅の質量百分率含有量が約90wt%~100wt%であり、前記銀系金属において、銀の質量百分率含有量が約90wt%~100wt%である、請求項2又は4に記載の導電パターン構造。
- 前記緩衝層の材料は、Mo、Nb、Ti、MoW、MoNb、MoTi、WNb、WTi、TiNb、窒化ケイ素、酸化ケイ素及び酸窒化ケイ素のうちの少なくとも1種を含む、請求項1に記載の導電パターン構造。
- 前記第3金属パターンの材料は、Mo、Nb、Ti、MoW、MoNb、MoTi、WNb、WTi及びTiNbのうちの少なくとも1種を含む、請求項1に記載の導電パターン構造。
- 請求項1~7のいずれかの1項に記載の導電パターン構造を含むアレイ基板。
- 請求項8に記載のアレイ基板を含む表示装置。
- 導電パターン構造の製造方法であって、
第1金属パターンを形成するステップと、
前記第1金属パターンの第1の主面に緩衝層を形成するステップと、
前記緩衝層から離れる前記第1金属パターンの第2の主面に第3金属パターンを形成するステップと、
第2金属パターンを形成するステップと、を含み、
前記第2金属パターンは、前記第1金属パターンの側面、前記第3金属パターンの側面及び前記緩衝層の側面とのみ接触しており、前記第2金属パターンは、前記第1金属パターンの第1の主面及び第2の主面と接触しておらず、
前記第1金属パターンの金属材料の活性が、前記第2金属パターンの金属材料の活性より弱い、導電パターン構造の製造方法。 - 前記第2金属パターンを形成するステップは、前記第1金属パターンが形成されていたベース基板を、第2金属イオンを含む溶液に入れて、前記第2金属パターンを形成するステップを含む、請求項10に記載の製造方法。
- 前記第1金属パターンの金属材料は、銅系金属及び銀系金属のうちの少なくとも1種を含む、請求項10又は11に記載の製造方法。
- 前記第2金属パターンの金属材料は、ニッケル、モリブデン、ニオブ、アルミニウム及びチタンのうちの少なくとも1種を含む、請求項12に記載の製造方法。
- 前記第2金属イオンを含む溶液は、ニッケル、モリブデン、ニオブ、アルミニウム又はチタンの塩化物、硝酸塩又は硫酸塩溶液を含む、請求項11に記載の製造方法。
- 前記緩衝層の材料は、Mo、Nb、Ti、MoW、MoNb、MoTi、WNb、WTi、TiNb、窒化ケイ素、酸化ケイ素及び酸窒化ケイ素のうちの少なくとも1種を含む、請求項10に記載の製造方法。
- 前記第3金属パターンの材料は、Mo、Nb、Ti、MoW、MoNb、MoTi、WNb、WTi及びTiNbのうちの少なくとも1種を含む、請求項10に記載の製造方法。
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JP2002093809A (ja) | 2000-09-14 | 2002-03-29 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003124216A (ja) | 2001-10-16 | 2003-04-25 | Sony Corp | 配線用シード膜および半導体装置の配線方法 |
JP2012204585A (ja) | 2011-03-25 | 2012-10-22 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2016520995A (ja) | 2013-03-20 | 2016-07-14 | 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co.,Ltd. | 薄膜トランジスタ及びその製造方法、アレイ基板、ディスプレイ |
US20150144952A1 (en) | 2013-11-27 | 2015-05-28 | Samsung Display Co., Ltd. | Display substrate, method of manufacturing the same, and display device including the same |
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US10790309B2 (en) | 2020-09-29 |
JP2020522118A (ja) | 2020-07-27 |
US20190280012A1 (en) | 2019-09-12 |
WO2018192210A1 (zh) | 2018-10-25 |
CN108735761A (zh) | 2018-11-02 |
EP3614426A4 (en) | 2020-12-09 |
EP3614426B1 (en) | 2024-08-07 |
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