JP7046200B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP7046200B2 JP7046200B2 JP2020537902A JP2020537902A JP7046200B2 JP 7046200 B2 JP7046200 B2 JP 7046200B2 JP 2020537902 A JP2020537902 A JP 2020537902A JP 2020537902 A JP2020537902 A JP 2020537902A JP 7046200 B2 JP7046200 B2 JP 7046200B2
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- 239000004065 semiconductor Substances 0.000 title claims description 92
- 239000011347 resin Substances 0.000 claims description 33
- 229920005989 resin Polymers 0.000 claims description 33
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
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Description
なお、各図面中において、同一符号は同一あるいは相当のものであることを示す。
図1は、実施の形態1による半導体モジュールを示す回路図である。半導体モジュール1は、複数の半導体スイッチング素子T1‐T4を少なくとも1つは内蔵している。図1は、モータ2を駆動するHブリッジ回路を示しており、半導体モジュール1は、モータ2、プラス(+)の電源3、グランド4を備えている。図1において、二重丸印は端子C1‐C6、B1、B2、G1、G2、M1、M2を示している。半導体スイッチング素子T1‐T4は、例えば電界効果トランジスタ(Field effect transistor:FET)である。図1に示すように、半導体モジュール1は、4個のFETによりブリッジ回路を構成し、上下アームの中間接続位置である小信号用の端子C5および端子C6、大電流用の端子M1および端子M2にはモータ2が接続される。
図2Aに示すように、大電流用の端子B1から銅板のベース11は、半導体モジュール1の内部へ伸びており、半導体スイッチング素子T1であるFETが装着されている。半導体スイッチング素子T1であるFETのゲート(図示なし)は、ワイヤボンディングによるワイヤJ3により小信号用の端子C1に接続されている。銅板のベース11は、半導体スイッチング素子T1であるFETのドレイン(図示なし)と直接接続され、一方、ソース(図示なし)はジャンパ線J1により電気的に配線されている。このジャンパ線J1も銅板のベース11と同様に銅板状で形成され大電流を流すのみならず、伝熱性にも優れている。
以上のように、実施の形態1による半導体モジュール1は、半導体スイッチング素子T1、T2、T3、T4、ベース11、ジャンパ線J1、J2等々を配置して接続した後、一点鎖線のモールド樹脂10で全体を覆われて封止されている。
各端子C1‐C6、B1、B2、G1、G2、M1、M2は、装置全体つまり半導体モジュール1の小型化のため近接して配列される。また、装置である半導体モジュール1の設置される環境、又はモールド樹脂10の材料、塗料等々によりトラッキングが発生する可能性があり、絶縁性の確保は装置である半導体モジュール1の正常な駆動のみならず、この半導体モジュール1を含んだ全体の装置、例えば電力変換装置の信頼性に影響する。
実施の形態1による半導体モジュール1において、小信号用の端子C2の近傍に設けた凹部12は外周9から略半円状に穿かれている。一方、凸部13は、端子G1の延在方向に向かって突出して形成されており、台形形状となっている。沿面距離は、端子の端部間の最短距離であるので、実施の形態1の半導体モジュール1では、凸部13は、大電流用の端子G1の厚み方向tに対向する部分が最も高く、端子の厚み方向tから離れるに従って徐々に低くなっている。つまり、凸部13の凸高さは、端子同士の対向部分8の距離に応じて可変させることも可能である。
実施の形態1による半導体モジュール1においては、凹部12または凸部13のどちらを設けた場合であっても、沿面距離を確保することに対する有意差は少ないが、別の条件によりどちらを設けるのかについて選択できる。例えば、モールド樹脂10の外周9に近接する位置までベース11等が設けられている場合は、凹部12を設ける余地がないため凸部13を設けた方が信頼性の高い半導体モジュール1が得られる。さらに、沿面距離をさらに伸ばす必要がある場合は、凹部12および凸部13を組合せて設けることも可能である。
図5Aは、実施の形態2による半導体モジュールの部分上面図であり、図5Bは、実施の形態2による半導体モジュールの部分側面図である。図5Aおよび図5Bは、実施の形態1と回路構成は同じであるが、別構成の半導体モジュール1aを示す。ここでは、図5Aおよび図5Bを用いて、複数の端子C10‐C13間の沿面距離の確保について説明する。
さらに横方向に隣接する端子間である、例えば端子C10と端子C11、端子C12と端子C13の間にも凸部16を設けられている。
また、実施の形態2による半導体モジュール1aにおいても、凸部15または凸部16は、半導体モジュール1aのモールド樹脂10と一体でなくてもよいが、一体であればモールド時の同一工程で形成することができるので、製造工程が簡略化できる効果を有する。また、実施の形態2による半導体モジュール1aにおいては、端子C10‐C13同士間の対向部分8を分断するように凹部(図示なし)を設けることもできる。実施の形態2の半導体モジュール1aでは、凹凸部をできる限りどちらかの形状に1本化して単純な構造とすることが可能である。
従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも1つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも1つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。
Claims (6)
- 半導体スイッチング素子と、
少なくともいずれかには前記半導体スイッチング素子が装着された複数のベースと、
前記半導体スイッチング素子および前記複数のベースを封止するモールド樹脂と、
前記複数のベースのそれぞれと一体的に形成され、前記モールド樹脂の外周側面から突出して設けられた複数の端子と、
前記複数の端子間の前記モールド樹脂の外周側面の一部に、前記複数の端子間の沿面距離を確保するような高さを有し、前記複数の端子間の対向部分を横切るように形成された凸部と、を備え、
前記複数の端子は、前記モールド樹脂の外周側面からジグザグ状に配置されて形成されており、
前記凸部は、ジグザグ状に配置された上下の前記複数の端子間に設けられ、横長形状を有する第1の凸部を有することを特徴とする半導体モジュール。 - 前記凸部は、横方向に隣接する前記複数の端子間に設けられた第2の凸部を有することを特徴とする請求項1に記載の半導体モジュール。
- 前記凸部は、前記モールド樹脂と同一材料であり、前記複数の端子と前記凸部とは接することなく隙間を有することを特徴とする請求項1または請求項2に記載の半導体モジュール。
- 前記凸部は、前記端子の延在方向に形成された山形形状であり、前記端子の厚み方向に対向する第1の部分を有しており、
前記凸部の高さは、前記端子の厚み方向から離れるにしたがって徐々に前記第1の部分よりも低く形成されたことを特徴とする請求項1から請求項3のいずれか1項に記載の半導体モジュール。 - 前記凸部は、傾斜面を有していることを特徴とする請求項1から請求項4のいずれか1項に記載の半導体モジュール。
- 前記複数の端子間の対向部分は、隣接した前記複数の端子の周囲の箇所同士を最短距離で結ぶ複数の線により挟まれた領域であり、
前記凸部は、前記領域を分断するように配置されたことを特徴とする請求項1から請求項5のいずれか1項に記載の半導体モジュール。
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