JP7023791B2 - オン－ダイターミネーションの制御方法及びこれを遂行するシステム - Google Patents

オン－ダイターミネーションの制御方法及びこれを遂行するシステム Download PDF

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JP7023791B2
JP7023791B2 JP2018102557A JP2018102557A JP7023791B2 JP 7023791 B2 JP7023791 B2 JP 7023791B2 JP 2018102557 A JP2018102557 A JP 2018102557A JP 2018102557 A JP2018102557 A JP 2018102557A JP 7023791 B2 JP7023791 B2 JP 7023791B2
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rank
memory
odt
activated
command
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JP2018200739A (ja
JP2018200739A5 (enExample
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永 訓 孫
始 弘 金
昶 ギョ 李
ジョン 煥 崔
慶 洙 河
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2018102557A 2017-05-29 2018-05-29 オン－ダイターミネーションの制御方法及びこれを遂行するシステム Active JP7023791B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20170066377 2017-05-29
KR10-2017-0066377 2017-05-29
KR10-2017-0089692 2017-07-14
KR1020170089692A KR20180130417A (ko) 2017-05-29 2017-07-14 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템

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JP2018200739A JP2018200739A (ja) 2018-12-20
JP2018200739A5 JP2018200739A5 (enExample) 2021-07-26
JP7023791B2 true JP7023791B2 (ja) 2022-02-22

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US (4) US10566038B2 (enExample)
JP (1) JP7023791B2 (enExample)
CN (2) CN108932960B (enExample)
DE (1) DE102018108554A1 (enExample)

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DE102018108554A1 (de) 2018-11-29
US20200243123A1 (en) 2020-07-30
US20180342274A1 (en) 2018-11-29
US10916279B2 (en) 2021-02-09
US10692554B2 (en) 2020-06-23
US11475930B2 (en) 2022-10-18
CN112951287A (zh) 2021-06-11
CN108932960A (zh) 2018-12-04
US10566038B2 (en) 2020-02-18
JP2018200739A (ja) 2018-12-20
US20210233575A1 (en) 2021-07-29
US20200135247A1 (en) 2020-04-30
CN112951287B (zh) 2022-02-25
CN108932960B (zh) 2021-06-01

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