DE102018010677B8 - Verfahren zum Betreiben eines dynamischen Low-Power-Double-Data-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM) - Google Patents

Verfahren zum Betreiben eines dynamischen Low-Power-Double-Data-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM)

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Publication number
DE102018010677B8
DE102018010677B8 DE102018010677.3A DE102018010677A DE102018010677B8 DE 102018010677 B8 DE102018010677 B8 DE 102018010677B8 DE 102018010677 A DE102018010677 A DE 102018010677A DE 102018010677 B8 DE102018010677 B8 DE 102018010677B8
Authority
DE
Germany
Prior art keywords
operating
access memory
data rate
direct access
double data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102018010677.3A
Other languages
German (de)
English (en)
Other versions
DE102018010677B4 (de
Inventor
Young-Hoon SON
Si-Hong Kim
Chang-kyo LEE
Jung-hwan Choi
Kyung-Soo Ha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170089692A external-priority patent/KR20180130417A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE102018010677B4 publication Critical patent/DE102018010677B4/de
Publication of DE102018010677B8 publication Critical patent/DE102018010677B8/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102018010677.3A 2017-05-29 2018-04-11 Verfahren zum Betreiben eines dynamischen Low-Power-Double-Data-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM) Active DE102018010677B8 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2017-0066377 2017-05-29
KR20170066377 2017-05-29
KR10-2017-0089692 2017-07-14
KR1020170089692A KR20180130417A (ko) 2017-05-29 2017-07-14 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템

Publications (2)

Publication Number Publication Date
DE102018010677B4 DE102018010677B4 (de) 2026-03-19
DE102018010677B8 true DE102018010677B8 (de) 2026-05-07

Family

ID=64109546

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102018010677.3A Active DE102018010677B8 (de) 2017-05-29 2018-04-11 Verfahren zum Betreiben eines dynamischen Low-Power-Double-Data-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM)
DE102018108554.0A Pending DE102018108554A1 (de) 2017-05-29 2018-04-11 Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE102018108554.0A Pending DE102018108554A1 (de) 2017-05-29 2018-04-11 Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt

Country Status (4)

Country Link
US (4) US10566038B2 (enExample)
JP (1) JP7023791B2 (enExample)
CN (2) CN112951287B (enExample)
DE (2) DE102018010677B8 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240321331A1 (en) * 2016-06-27 2024-09-26 SK Hynix Inc. Semiconductor devices
US10566038B2 (en) 2017-05-29 2020-02-18 Samsung Electronics Co., Ltd. Method of controlling on-die termination and system performing the same
KR101970319B1 (ko) * 2017-09-14 2019-08-13 주식회사 힘펠 전열교환기
US10424356B2 (en) 2017-11-22 2019-09-24 Micron Technology, Inc. Methods for on-die memory termination and memory devices and systems employing the same
KR102665412B1 (ko) 2018-03-27 2024-05-20 삼성전자주식회사 멀티-랭크들의 온-다이 터미네이션(odt) 셋팅을 최적화하는 방법 및 메모리 시스템
US10318464B1 (en) * 2018-06-28 2019-06-11 Montage Technology Co., Ltd. Memory system and method for accessing memory system
US10797700B2 (en) 2018-12-21 2020-10-06 Samsung Electronics Co., Ltd. Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device
KR20200086137A (ko) * 2019-01-08 2020-07-16 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
CN112817884B (zh) * 2019-11-15 2025-04-04 安徽寒武纪信息科技有限公司 一种存储器以及包括该存储器的设备
KR102778721B1 (ko) * 2019-12-05 2025-03-11 삼성전자주식회사 온-다이 터미네이션의 제어 방법 및 이를 수행하는 메모리 시스템
US20200133669A1 (en) * 2019-12-23 2020-04-30 Intel Corporation Techniques for dynamic proximity based on-die termination
KR102849551B1 (ko) * 2020-08-18 2025-08-22 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
US11810638B2 (en) * 2020-09-29 2023-11-07 Samsung Electronics Co., Ltd. Memory device including multiple memory chips and data signal lines and a method of operating the memory device
KR20220126833A (ko) 2021-03-09 2022-09-19 삼성전자주식회사 데이터 클럭의 동기화를 연장하는 메모리 장치의 동작 방법, 및 메모리 장치를 포함하는 전자 장치의 동작 방법
TWI809541B (zh) 2021-03-09 2023-07-21 南韓商三星電子股份有限公司 與記憶體控制器進行通訊的記憶體元件的操作方法、以及包括其之電子元件的操作方法
EP4399585A4 (en) * 2021-09-07 2025-07-09 Rambus Inc COMMON DATA STROBE ACROSS MULTIPLE MEMORY DEVICES
JP7513730B2 (ja) * 2022-03-25 2024-07-09 チャンシン メモリー テクノロジーズ インコーポレイテッド 制御方法、半導体メモリ及び電子機器
KR20250022229A (ko) 2022-03-25 2025-02-14 창신 메모리 테크놀로지즈 아이엔씨 제어 방법, 반도체 메모리 및 전자 기기
KR102815432B1 (ko) 2022-03-25 2025-05-29 창신 메모리 테크놀로지즈 아이엔씨 제어 방법, 반도체 메모리 및 전자 기기
US12142314B2 (en) * 2022-04-20 2024-11-12 Samsung Electronics Co., Ltd. Semiconductor die for controlling on-die-termination of another semiconductor die, and semiconductor devices including the same
US12333169B2 (en) 2022-04-25 2025-06-17 Samsung Electronics Co., Ltd. Memory system for optimizing on-die termination settings of multi-ranks, method of operation of memory system, and memory controller
KR20240039924A (ko) 2022-09-20 2024-03-27 삼성전자주식회사 다양한 동작 모드를 가지는 반도체 메모리 장치 및 메모리 모듈
CN118866040B (zh) * 2023-04-14 2025-10-03 长鑫存储技术有限公司 一种命令产生电路和存储器
US12554633B2 (en) * 2024-01-29 2026-02-17 SanDisk Technologies, Inc. Non-target on-die termination
CN118969051A (zh) * 2024-10-12 2024-11-15 博越微电子(江苏)有限公司 一种lpddr5x的全速自测方法及系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100182817A1 (en) 2009-01-22 2010-07-22 Elpida Memory, Inc. Memory system, semiconductor memory device, and wiring substrate
US8619492B2 (en) 2010-02-23 2013-12-31 Samsung Electronics Co., Ltd. On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100528164B1 (ko) 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
US7164600B2 (en) * 2004-12-10 2007-01-16 Micron Technology Inc Reducing DQ pin capacitance in a memory device
US7079441B1 (en) 2005-02-04 2006-07-18 Infineon Technologies Ag Methods and apparatus for implementing a power down in a memory device
US9171585B2 (en) * 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US7259585B2 (en) 2005-09-28 2007-08-21 International Business Machines Corporation Selective on-die termination for improved power management and thermal distribution
JP4930875B2 (ja) * 2005-09-29 2012-05-16 株式会社ハイニックスセミコンダクター オンダイターミネーション制御装置
KR100625298B1 (ko) * 2005-09-29 2006-09-15 주식회사 하이닉스반도체 온 다이 터미네이션 제어 장치
US7342411B2 (en) * 2005-12-07 2008-03-11 Intel Corporation Dynamic on-die termination launch latency reduction
US7372293B2 (en) * 2005-12-07 2008-05-13 Intel Corporation Polarity driven dynamic on-die termination
US7414426B2 (en) * 2005-12-07 2008-08-19 Intel Corporation Time multiplexed dynamic on-die termination
KR100738969B1 (ko) * 2006-08-16 2007-07-12 주식회사 하이닉스반도체 반도체 메모리의 온-다이 터미네이션 제어 장치 및 방법
JP2009252322A (ja) 2008-04-09 2009-10-29 Nec Electronics Corp 半導体メモリ装置
US8041865B2 (en) * 2008-08-04 2011-10-18 Qimonda Ag Bus termination system and method
US7944726B2 (en) 2008-09-30 2011-05-17 Intel Corporation Low power termination for memory modules
KR20110128858A (ko) * 2009-02-12 2011-11-30 모사이드 테크놀로지스 인코퍼레이티드 온-다이 터미네이션을 위한 터미네이션 회로
WO2010144624A1 (en) 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US8966208B2 (en) 2010-02-25 2015-02-24 Conversant Ip Management Inc. Semiconductor memory device with plural memory die and controller die
WO2011159465A2 (en) * 2010-06-17 2011-12-22 Rambus Inc. Balanced on-die termination
US8274308B2 (en) * 2010-06-28 2012-09-25 Intel Corporation Method and apparatus for dynamic memory termination
KR101841622B1 (ko) 2010-11-04 2018-05-04 삼성전자주식회사 온-다이 터미네이션 회로를 가지는 불휘발성 메모리 장치 및 그것의 제어 방법
US9201444B2 (en) * 2010-11-29 2015-12-01 Rambus Inc. Clock generation for timing communications with ranks of memory devices
KR101853874B1 (ko) * 2011-09-21 2018-05-03 삼성전자주식회사 메모리 장치의 동작 방법 및 상기 방법을 수행하기 위한 장치들
CN104025060B (zh) 2011-09-30 2017-06-27 英特尔公司 支持近存储器和远存储器访问的存储器通道
KR20140008745A (ko) * 2012-07-11 2014-01-22 삼성전자주식회사 자기 메모리 장치
US9747230B2 (en) * 2012-10-15 2017-08-29 Rambus Inc. Memory rank and ODT configuration in a memory system
KR20140072276A (ko) * 2012-11-29 2014-06-13 삼성전자주식회사 불휘발성 메모리 및 불휘발성 메모리의 동작 방법
US9542343B2 (en) * 2012-11-29 2017-01-10 Samsung Electronics Co., Ltd. Memory modules with reduced rank loading and memory systems including same
US9087570B2 (en) * 2013-01-17 2015-07-21 Micron Technology, Inc. Apparatuses and methods for controlling a clock signal provided to a clock tree
US9780782B2 (en) 2014-07-23 2017-10-03 Intel Corporation On-die termination control without a dedicated pin in a multi-rank system
US9230984B1 (en) 2014-09-30 2016-01-05 Sandisk Technologies Inc Three dimensional memory device having comb-shaped source electrode and methods of making thereof
CN104332176A (zh) * 2014-11-14 2015-02-04 福州瑞芯微电子有限公司 一种省掉内存odt引脚的方法和系统
US10255220B2 (en) * 2015-03-30 2019-04-09 Rambus Inc. Dynamic termination scheme for memory communication
JP2017027638A (ja) 2015-07-16 2017-02-02 京セラドキュメントソリューションズ株式会社 配線回路、制御装置、及び画像処理装置
US10141935B2 (en) * 2015-09-25 2018-11-27 Intel Corporation Programmable on-die termination timing in a multi-rank system
KR20170089692A (ko) 2016-01-27 2017-08-04 주식회사 스맥 전동식 건물 비상 탈출 장치
US10416896B2 (en) * 2016-10-14 2019-09-17 Samsung Electronics Co., Ltd. Memory module, memory device, and processing device having a processor mode, and memory system
US10490239B2 (en) * 2016-12-27 2019-11-26 Intel Corporation Programmable data pattern for repeated writes to memory
US10566038B2 (en) 2017-05-29 2020-02-18 Samsung Electronics Co., Ltd. Method of controlling on-die termination and system performing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100182817A1 (en) 2009-01-22 2010-07-22 Elpida Memory, Inc. Memory system, semiconductor memory device, and wiring substrate
US8619492B2 (en) 2010-02-23 2013-12-31 Samsung Electronics Co., Ltd. On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination

Also Published As

Publication number Publication date
US20180342274A1 (en) 2018-11-29
JP2018200739A (ja) 2018-12-20
JP7023791B2 (ja) 2022-02-22
US11475930B2 (en) 2022-10-18
CN112951287A (zh) 2021-06-11
CN108932960A (zh) 2018-12-04
US20200135247A1 (en) 2020-04-30
US20200243123A1 (en) 2020-07-30
CN112951287B (zh) 2022-02-25
US10566038B2 (en) 2020-02-18
US10692554B2 (en) 2020-06-23
CN108932960B (zh) 2021-06-01
US10916279B2 (en) 2021-02-09
DE102018108554A1 (de) 2018-11-29
DE102018010677B4 (de) 2026-03-19
US20210233575A1 (en) 2021-07-29

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