JP6982976B2 - 半導体デバイスの製造方法および半導体デバイス - Google Patents

半導体デバイスの製造方法および半導体デバイス Download PDF

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Publication number
JP6982976B2
JP6982976B2 JP2017083039A JP2017083039A JP6982976B2 JP 6982976 B2 JP6982976 B2 JP 6982976B2 JP 2017083039 A JP2017083039 A JP 2017083039A JP 2017083039 A JP2017083039 A JP 2017083039A JP 6982976 B2 JP6982976 B2 JP 6982976B2
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region
groove
semiconductor device
insulating film
forming
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Japanese (ja)
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JP2018180416A5 (enExample
JP2018180416A (ja
Inventor
伸明 柿沼
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Canon Inc
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Canon Inc
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Priority to JP2017083039A priority Critical patent/JP6982976B2/ja
Priority to US15/945,120 priority patent/US10332783B2/en
Publication of JP2018180416A publication Critical patent/JP2018180416A/ja
Publication of JP2018180416A5 publication Critical patent/JP2018180416A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2017083039A 2017-04-19 2017-04-19 半導体デバイスの製造方法および半導体デバイス Active JP6982976B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017083039A JP6982976B2 (ja) 2017-04-19 2017-04-19 半導体デバイスの製造方法および半導体デバイス
US15/945,120 US10332783B2 (en) 2017-04-19 2018-04-04 Method of manufacturing semiconductor device, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017083039A JP6982976B2 (ja) 2017-04-19 2017-04-19 半導体デバイスの製造方法および半導体デバイス

Publications (3)

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JP2018180416A JP2018180416A (ja) 2018-11-15
JP2018180416A5 JP2018180416A5 (enExample) 2020-07-02
JP6982976B2 true JP6982976B2 (ja) 2021-12-17

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US (1) US10332783B2 (enExample)
JP (1) JP6982976B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12349495B2 (en) 2020-02-21 2025-07-01 Canon Kabushiki Kaisha Semiconductor device and method for manufacturing semiconductor device
JP7585030B2 (ja) * 2020-02-21 2024-11-18 キヤノン株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136020A (ja) 1991-11-11 1993-06-01 Fujitsu Ltd 半導体装置の露光方法
US6033977A (en) 1997-06-30 2000-03-07 Siemens Aktiengesellschaft Dual damascene structure
TW457635B (en) 2000-04-21 2001-10-01 Ind Tech Res Inst Manufacturing process of copper structure
JP2006128543A (ja) * 2004-11-01 2006-05-18 Nec Electronics Corp 電子デバイスの製造方法
JP2006148003A (ja) * 2004-11-24 2006-06-08 Toshiba Corp 半導体装置の製造方法及び半導体装置
JP2007103723A (ja) 2005-10-05 2007-04-19 Renesas Technology Corp 半導体装置およびその製造方法
JP4699172B2 (ja) * 2005-10-25 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
JP5008929B2 (ja) 2006-09-11 2012-08-22 ソニーモバイルディスプレイ株式会社 液晶装置の製造方法
JP2010098095A (ja) * 2008-10-16 2010-04-30 Sony Corp 半導体装置及び半導体装置の製造方法
JP2010141093A (ja) 2008-12-11 2010-06-24 Sony Corp 半導体装置とその製造方法
JP2010165737A (ja) 2009-01-13 2010-07-29 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP2010165760A (ja) 2009-01-14 2010-07-29 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP6240443B2 (ja) 2012-09-17 2017-11-29 シチズンファインデバイス株式会社 液晶表示装置
JP2014102292A (ja) 2012-11-16 2014-06-05 Canon Inc フォトマスク、分割露光方法、および半導体デバイスの製造方法
WO2014109044A1 (ja) 2013-01-11 2014-07-17 ルネサスエレクトロニクス株式会社 半導体装置
US20170256506A1 (en) 2013-01-11 2017-09-07 Renesas Electronics Corporation Semiconductor device
JP5855695B2 (ja) 2014-03-24 2016-02-09 ルネサスエレクトロニクス株式会社 固体撮像素子の製造方法及び固体撮像素子
JP2016192467A (ja) 2015-03-31 2016-11-10 ルネサスエレクトロニクス株式会社 半導体装置

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Publication number Publication date
US20180308747A1 (en) 2018-10-25
JP2018180416A (ja) 2018-11-15
US10332783B2 (en) 2019-06-25

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