JP6828959B2 - リードフレームおよびその製造方法 - Google Patents

リードフレームおよびその製造方法 Download PDF

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Publication number
JP6828959B2
JP6828959B2 JP2017006178A JP2017006178A JP6828959B2 JP 6828959 B2 JP6828959 B2 JP 6828959B2 JP 2017006178 A JP2017006178 A JP 2017006178A JP 2017006178 A JP2017006178 A JP 2017006178A JP 6828959 B2 JP6828959 B2 JP 6828959B2
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Prior art keywords
recess
lead frame
shape
etching
plating layer
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Japanese (ja)
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JP2018117020A5 (enExample
JP2018117020A (ja
Inventor
柾樹 山口
柾樹 山口
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大口マテリアル株式会社
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Priority to JP2017006178A priority Critical patent/JP6828959B2/ja
Priority to TW107100604A priority patent/TW201841323A/zh
Priority to CN201810044232.5A priority patent/CN108461469A/zh
Priority to US15/873,226 priority patent/US10622286B2/en
Publication of JP2018117020A publication Critical patent/JP2018117020A/ja
Publication of JP2018117020A5 publication Critical patent/JP2018117020A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L2224/732Location after the connecting process
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    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L24/92Specific sequence of method steps

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2017006178A 2017-01-17 2017-01-17 リードフレームおよびその製造方法 Active JP6828959B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017006178A JP6828959B2 (ja) 2017-01-17 2017-01-17 リードフレームおよびその製造方法
TW107100604A TW201841323A (zh) 2017-01-17 2018-01-08 導線框及其製造方法
CN201810044232.5A CN108461469A (zh) 2017-01-17 2018-01-17 引线框及其制造方法
US15/873,226 US10622286B2 (en) 2017-01-17 2018-01-17 Lead frame and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017006178A JP6828959B2 (ja) 2017-01-17 2017-01-17 リードフレームおよびその製造方法

Publications (3)

Publication Number Publication Date
JP2018117020A JP2018117020A (ja) 2018-07-26
JP2018117020A5 JP2018117020A5 (enExample) 2019-09-05
JP6828959B2 true JP6828959B2 (ja) 2021-02-10

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US (1) US10622286B2 (enExample)
JP (1) JP6828959B2 (enExample)
CN (1) CN108461469A (enExample)
TW (1) TW201841323A (enExample)

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Publication number Priority date Publication date Assignee Title
JP6741356B1 (ja) * 2019-03-22 2020-08-19 大口マテリアル株式会社 リードフレーム
EP3879569A1 (en) * 2020-03-11 2021-09-15 Nexperia B.V. A leadless semiconductor package and method of manufacture
JP7617812B2 (ja) * 2021-05-24 2025-01-20 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
JP7677579B2 (ja) * 2021-12-22 2025-05-15 新光電気工業株式会社 リードフレーム、リードフレームの製造方法及び半導体装置の製造方法

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JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20040080025A1 (en) * 2002-09-17 2004-04-29 Shinko Electric Industries Co., Ltd. Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same
JP2007051336A (ja) * 2005-08-18 2007-03-01 Shinko Electric Ind Co Ltd 金属板パターン及び回路基板の形成方法
JP2009164232A (ja) 2007-12-28 2009-07-23 Mitsui High Tec Inc 半導体装置及びその製造方法並びにリードフレーム及びその製造方法
US7821113B2 (en) * 2008-06-03 2010-10-26 Texas Instruments Incorporated Leadframe having delamination resistant die pad
JP2009302209A (ja) * 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法
WO2010052973A1 (ja) * 2008-11-05 2010-05-14 株式会社三井ハイテック 半導体装置及びその製造方法
JP5195647B2 (ja) * 2009-06-01 2013-05-08 セイコーエプソン株式会社 リードフレームの製造方法及び半導体装置の製造方法
JP5626785B2 (ja) 2010-09-27 2014-11-19 Shマテリアル株式会社 半導体素子搭載用リードフレームおよびその製造方法
JP2012146782A (ja) 2011-01-11 2012-08-02 Sumitomo Metal Mining Co Ltd 半導体素子搭載用リードフレームの製造方法
JP2017103365A (ja) * 2015-12-02 2017-06-08 新光電気工業株式会社 リードフレーム及び電子部品装置とそれらの製造方法

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