JP6803249B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

Info

Publication number
JP6803249B2
JP6803249B2 JP2017014614A JP2017014614A JP6803249B2 JP 6803249 B2 JP6803249 B2 JP 6803249B2 JP 2017014614 A JP2017014614 A JP 2017014614A JP 2017014614 A JP2017014614 A JP 2017014614A JP 6803249 B2 JP6803249 B2 JP 6803249B2
Authority
JP
Japan
Prior art keywords
layer
wiring
adhesive layer
conductive paste
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017014614A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018125350A5 (https=
JP2018125350A (ja
Inventor
直 荒井
直 荒井
良和 平林
良和 平林
秀敏 荒井
秀敏 荒井
小平　正司
正司 小平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017014614A priority Critical patent/JP6803249B2/ja
Priority to US15/866,869 priority patent/US10290570B2/en
Publication of JP2018125350A publication Critical patent/JP2018125350A/ja
Publication of JP2018125350A5 publication Critical patent/JP2018125350A5/ja
Application granted granted Critical
Publication of JP6803249B2 publication Critical patent/JP6803249B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
JP2017014614A 2017-01-30 2017-01-30 配線基板及びその製造方法 Active JP6803249B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017014614A JP6803249B2 (ja) 2017-01-30 2017-01-30 配線基板及びその製造方法
US15/866,869 US10290570B2 (en) 2017-01-30 2018-01-10 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017014614A JP6803249B2 (ja) 2017-01-30 2017-01-30 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2018125350A JP2018125350A (ja) 2018-08-09
JP2018125350A5 JP2018125350A5 (https=) 2019-12-12
JP6803249B2 true JP6803249B2 (ja) 2020-12-23

Family

ID=62980186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017014614A Active JP6803249B2 (ja) 2017-01-30 2017-01-30 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US10290570B2 (https=)
JP (1) JP6803249B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10790236B2 (en) * 2018-04-05 2020-09-29 Shinko Electric Industries Co., Ltd. Wiring substrate and electronic device
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
TWI752820B (zh) * 2021-02-08 2022-01-11 欣興電子股份有限公司 電路板結構及其製作方法
EP4099807A1 (en) * 2021-06-01 2022-12-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier interconnection and manufacturing method
KR20230067265A (ko) * 2021-11-09 2023-05-16 삼성전기주식회사 인쇄회로기판
CN120413426A (zh) * 2025-04-24 2025-08-01 广东佛智芯微电子技术研究有限公司 多层金属化芯板堆叠混合键合方法及结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4459406B2 (ja) * 2000-07-27 2010-04-28 ソニーケミカル＆インフォメーションデバイス株式会社 フレキシブル配線板製造方法
JP4590088B2 (ja) 2000-11-22 2010-12-01 ソニーケミカル＆インフォメーションデバイス株式会社 フレキシブル基板素片、及び、多層フレキシブル配線板
US6573460B2 (en) * 2001-09-20 2003-06-03 Dpac Technologies Corp Post in ring interconnect using for 3-D stacking
CN100512604C (zh) * 2002-11-27 2009-07-08 住友电木株式会社 电路板、多层布线板及其制造方法
JP2004228322A (ja) * 2003-01-22 2004-08-12 Sumitomo Bakelite Co Ltd 多層フレキシブル配線板の製造方法
WO2004077560A1 (ja) * 2003-02-26 2004-09-10 Ibiden Co., Ltd. 多層プリント配線板
JP4075673B2 (ja) * 2003-04-22 2008-04-16 松下電工株式会社 多層プリント配線板用銅張り積層板、多層プリント配線板、多層プリント配線板の製造方法

Also Published As

Publication number Publication date
US10290570B2 (en) 2019-05-14
US20180218972A1 (en) 2018-08-02
JP2018125350A (ja) 2018-08-09

Similar Documents

Publication Publication Date Title
JP6858576B2 (ja) 半導体装置の製造方法
JP6803249B2 (ja) 配線基板及びその製造方法
JP6566879B2 (ja) 電子部品内蔵基板
US10720392B2 (en) Wiring substrate
JP6761064B2 (ja) 配線基板及びその製造方法
KR20150004749A (ko) 배선 기판 및 그 제조 방법, 반도체 패키지
JP2020155631A (ja) 配線基板及びその製造方法、半導体パッケージ
JP2017034059A (ja) プリント配線板、半導体パッケージおよびプリント配線板の製造方法
JP2018026437A (ja) 配線基板及びその製造方法
US10779406B2 (en) Wiring substrate
JP2015159197A (ja) 配線基板及びその製造方法
JP2010219477A (ja) 電子部品内蔵配線基板の製造方法
JP5007164B2 (ja) 多層配線板及び多層配線板製造方法
JP2009016377A (ja) 多層配線板及び多層配線板製造方法
JP6671256B2 (ja) 配線基板及びその製造方法
JP2010109180A (ja) 半導体装置内蔵基板の製造方法
US20230413452A1 (en) Laminated wiring board
US12482734B2 (en) Laminated wiring board
JP2008181920A (ja) 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法
JP2008181921A (ja) 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法
US12200871B2 (en) Component-containing substrate
US12133330B2 (en) Wiring substrate and semiconductor device
JP2018037633A (ja) プリント配線板およびプリント配線板の製造方法
JP2023142048A (ja) 配線基板の製造方法
JP2003243816A (ja) 配線基板およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191028

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191028

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200804

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200924

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20201117

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20201130

R150 Certificate of patent or registration of utility model

Ref document number: 6803249

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150