JP6757457B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6757457B2 JP6757457B2 JP2019216490A JP2019216490A JP6757457B2 JP 6757457 B2 JP6757457 B2 JP 6757457B2 JP 2019216490 A JP2019216490 A JP 2019216490A JP 2019216490 A JP2019216490 A JP 2019216490A JP 6757457 B2 JP6757457 B2 JP 6757457B2
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- 239000004065 semiconductor Substances 0.000 title claims description 285
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 63
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 46
- 239000012535 impurity Substances 0.000 claims description 45
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 230000002457 bidirectional effect Effects 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 335
- 229910000679 solder Inorganic materials 0.000 description 164
- 230000007547 defect Effects 0.000 description 34
- 239000010408 film Substances 0.000 description 25
- 239000011800 void material Substances 0.000 description 24
- 239000000463 material Substances 0.000 description 17
- 210000000746 body region Anatomy 0.000 description 15
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- 239000007769 metal material Substances 0.000 description 10
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- 239000004020 conductor Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000000704 physical effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
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- 238000002161 passivation Methods 0.000 description 4
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910001416 lithium ion Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 230000007423 decrease Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
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Description
702<2.33×tsi+10.5×tag+8.90×tni<943
の関係式が成立する。
[1.半導体装置の構造]
以下、本実施の形態に係る半導体装置1の構造について説明する。本開示に係る半導体装置1は、半導体基板に2つの縦型MOS(Metal Oxide Semiconductor)トランジスタを形成した、フェイスダウン実装が可能なCSP(Chip Size Package:チップサイズパッケージ)型のマルチトランジスタチップである。上記2つの縦型MOSトランジスタは、パワートランジスタであり、いわゆる、トレンチMOS型FET(Field Effect Transistor)である。
図1に示す半導体装置1において、例えば、第1導電型をN型、第2導電型をP型として、ソース領域14、ソース領域24、半導体基板32、および低濃度不純物層33はN型半導体であり、かつ、ボディ領域18およびボディ領域28はP型半導体であってもよい。
図3は、半導体装置1の、スマートホンやタブレットの充放電回路への応用例を示す回路図であり、半導体装置1は、制御IC2から与えられる制御信号に応じて、電池3から負荷4への放電動作および負荷4から電池3への充電動作を制御する。このようにスマートホンやタブレットの充放電回路として、半導体装置1が適用される場合、充電時間短縮や急速充電実現の制約から、オン抵抗は、20V耐圧仕様として、2.2〜2.4mΩ以下が求められる。
半導体装置1は、ゲート電極19、ソース電極11、ゲート電極29、およびソース電極21が、実装基板の実装面と対向するようにフェイスダウン配置され、はんだなどの接合材を介してリフローにより半導体装置1に一定の圧力(例えば実装基板と半導体装置1との間隔が80μmとなるように)を加えながら実装基板に実装される。
Ni層を付加することで、半導体装置1の反り抑制に効果があるが、低オン抵抗化のためにAg層を50μmまで厚くし、かつ、半導体装置1の反り抑制のためにNi層を30μmまで厚くすると、半導体装置1の重量が大きくなる。半導体装置1の重量が大きくなると、半導体装置1の反りとは別の課題として、半導体装置1の実装時に接合不良を引き起こし易くなる。半導体装置1をフェイスダウン実装する場合、半導体装置1の重量が過度に大きくなれば、同一の実装条件であってもはんだを押し付ける力が大きくなる。その結果、はんだがソース電極11およびソース電極21、ならびに実装基板に形成された基板電極の範囲からはみ出し、ショート不良を引き起こす可能性が高くなる。
第1膜厚換算重量=2.33×tsi+10.5×tag+8.90×tni (式1)
第2膜厚換算重量(mg)
=0.0067×(2.33×tsi+10.5×tag+8.90×tni) (式2)
(1)電極外周から外部へのはんだはみ出しによる不具合
(2)はんだはみ出しの一種だが、はみ出したはんだが電極外周よりも外部へ飛び出してボール状に浮遊したり、半導体装置の側面部分で半球状に固着したりする不具合
(3)本来は所定の領域全体に行き渡ることが望ましいはんだが、一部の領域では行き渡らない不具合。これについては、ボイド率およびボイド発生率としてカウントした。
ボイド率(%)=ボイド面積/電極面積 (式3)
(A)はんだはみ出し:隣接する電極との間隔の半分を超えてはみ出す場合は不良と判定
(B)はんだボール、側面付着:発生が認められれば不良と判定
(C)ボイド率:半導体装置に備わるすべての電極について個々にボイド率を算出し、標準規格IPC−7095に則り、ボイド率がClassIの区分からも外れる33%以上となるものは不良と判定
(i)Ag層またはNi層が薄いほど、実測重量は小さく反り量は大きく、ボイド率が高いが、はんだはみ出し不良、はんだボール、および側面付着不良は見られない。
(ii)Ag層またはNi層が厚いほど、実測重量は大きく、反り量は小さく、はんだはみ出し不良および側面付着不良の発生率が高いが、ボイド不良は見られない。
702 <2.33×tsi+10.5×tag+8.90×tni<943 (式4)
790≦2.33×tsi+10.5×tag+8.90×tni (式5)
0.0067×(2.33×tsi+10.5×tag+8.90×tni)/Sa<3.12
0.0067×(2.33×tsi+10.5×tag+8.90×tni)/3.12<Sa (式10)
以上、本開示の1つまたは複数の態様に係る半導体装置について、実施の形態に基づいて説明したが、本開示は、この実施の形態に限定されるものではない。本開示の趣旨を逸脱しない限り、当業者が思いつく各種変形を本実施の形態に施したものや、異なる実施の形態における構成要素を組み合わせて構築される形態も、本開示の1つまたは複数の態様の範囲内に含まれてもよい。
2 制御IC
3 電池
4 負荷
10 トランジスタ(第1の縦型MOSトランジスタ)
11、11a、11b、11c、11d、21、21a、21b、21c、21d ソース電極
12、13、22、23 部分
14、24 ソース領域
15、25 ゲート導体
16、26 ゲート絶縁膜
18、28 ボディ領域
19、29 ゲート電極
20 トランジスタ(第2の縦型MOSトランジスタ)
30、31 金属層
30a、30b、31a、31b、40a、40b 主面
32 半導体基板
33 低濃度不純物層
34 層間絶縁層
35 パッシベーション層
40 半導体層
90C 境界線
91、92 長辺
93、94 短辺
Claims (7)
- フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
互いに背向する第1主面および第2主面を有する半導体層と、
互いに背向する第3主面および第4主面を有し、前記第3主面が前記第2主面に接触して形成され、銀からなり、厚さが30μm以上かつ60μmより薄い第1の金属層と、
互いに背向する第5主面および第6主面を有し、前記第5主面が前記第4主面に接触して形成され、ニッケルからなる第2の金属層と、
前記半導体層内の第1の領域に形成された第1の縦型MOSトランジスタと、
前記第1の領域と前記第1主面に沿った方向で隣接する、前記半導体層内の第2の領域に形成された第2の縦型MOSトランジスタと、を有し、
前記半導体層は、
前記第1主面および前記第2主面のうちの前記第2主面側に配置され、第1導電型の不純物を含むシリコンからなる半導体基板と、
前記第1主面および前記第2主面のうちの前記第1主面側に配置され、前記半導体基板に接触して形成され、前記半導体基板の前記第1導電型の不純物の濃度より低い濃度の前記第1導電型の不純物を含む低濃度不純物層と、を有し、
前記第1の縦型MOSトランジスタは前記低濃度不純物層の表面に第1のソース電極および第1のゲート電極を有し、
前記第2の縦型MOSトランジスタは前記低濃度不純物層の表面に第2のソース電極および第2のゲート電極を有し、
前記第1のソース電極および前記第1のゲート電極と、前記第2のソース電極および前記第2のゲート電極とは、前記半導体層を平面視した場合に、前記半導体層の長辺を2分する境界線に対して線対称の位置に形成され、
前記半導体基板は、前記第1の縦型MOSトランジスタの第1のドレイン領域および前記第2の縦型MOSトランジスタの第2のドレイン領域の共通ドレイン領域として機能し、
前記第1のソース電極から前記第1のドレイン領域、前記第1の金属層および前記第2のドレイン領域を経由した前記第2のソース電極までの双方向経路を主電流経路とし、
前記半導体層の長辺長と短辺長の比は1.73以下であり、
前記第1のソース電極および前記第2のソース電極における各電極の面積と周辺長との比は0.127以下であり、
前記第1のソース電極、前記第1のゲート電極、前記第2のソース電極、および前記第2のゲート電極の各面積の総和は2.61mm2以下であり、
前記第1のソース電極および前記第2のソース電極の各短辺長は0.3mm以下であり、
前記第1のソース電極および前記第2のソース電極は、各々複数の電極からなり、
前記平面視において、前記第1のソース電極および前記第2のソース電極を構成する前記複数の電極の長手方向は、前記半導体層の長辺と平行であり、前記第1のソース電極を構成する前記複数の電極はストライプ状に配置され、前記第2のソース電極を構成する前記複数の電極はストライプ状に配置され、
前記第1のソース電極および前記第2のソース電極を構成する前記複数の電極の各々の長辺長は、0.85mm以上かつ1.375mm以下である
半導体装置。 - 前記第1のゲート電極および前記第2のゲート電極の各々の最大幅は、0.25mm以下であり、
前記平面視において、前記第1のゲート電極は、前記第1のソース電極よりも前記半導体層の短辺側に、前記第1のソース電極と離間して形成されており、前記第2のゲート電極は、前記第2のソース電極よりも前記半導体層の短辺側に、前記第2のソース電極と離間して形成されている
請求項1に記載の半導体装置。 - 前記第1のソース電極および前記第2のソース電極は、各々複数の電極からなり、
前記第1のソース電極を構成する複数の電極および前記第2のソース電極を構成する複数の電極の少なくとも一方のうち、前記境界線側に形成された電極の面積は、前記半導体層の短辺側に形成された電極の面積より大きい
請求項1に記載の半導体装置。 - 前記第1のソース電極を構成する複数の電極および前記第2のソース電極を構成する複数の電極の少なくとも一方の各々の電極は、前記境界線側から前記短辺側に向かうにつれて小さい
請求項3に記載の半導体装置。 - フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
互いに背向する第1主面および第2主面を有する半導体層と、
互いに背向する第3主面および第4主面を有し、前記第3主面が前記第2主面に接触して形成され、銀からなり、厚さが30μm以上かつ60μmより薄い第1の金属層と、
互いに背向する第5主面および第6主面を有し、前記第5主面が前記第4主面に接触して形成され、ニッケルからなる第2の金属層と、
前記半導体層内の第1の領域に形成された第1の縦型MOSトランジスタと、
前記第1の領域と前記第1主面に沿った方向で隣接する、前記半導体層内の第2の領域に形成された第2の縦型MOSトランジスタと、を有し、
前記半導体層は、
前記第1主面および前記第2主面のうちの前記第2主面側に配置され、第1導電型の不純物を含むシリコンからなる半導体基板と、
前記第1主面および前記第2主面のうちの前記第1主面側に配置され、前記半導体基板に接触して形成され、前記半導体基板の前記第1導電型の不純物の濃度より低い濃度の前記第1導電型の不純物を含む低濃度不純物層と、を有し、
前記第1の縦型MOSトランジスタは前記低濃度不純物層の表面に第1のソース電極および第1のゲート電極を有し、
前記第2の縦型MOSトランジスタは前記低濃度不純物層の表面に第2のソース電極および第2のゲート電極を有し、
前記第1のソース電極および前記第1のゲート電極と、前記第2のソース電極および前記第2のゲート電極とは、前記半導体層を平面視した場合に、前記半導体層の長辺を2分する境界線に対して線対称の位置に形成され、
前記半導体基板は、前記第1の縦型MOSトランジスタの第1のドレイン領域および前記第2の縦型MOSトランジスタの第2のドレイン領域の共通ドレイン領域として機能し、
前記第1のソース電極から前記第1のドレイン領域、前記第1の金属層および前記第2のドレイン領域を経由した前記第2のソース電極までの双方向経路を主電流経路とし、
前記半導体層の長辺長と短辺長の比は1.73以下であり、
前記第1のソース電極および前記第2のソース電極における各電極の面積と周辺長との比は0.127以下であり、
前記第1のソース電極、前記第1のゲート電極、前記第2のソース電極、および前記第2のゲート電極の各面積の総和は2.61mm 2 以下であり、
前記第1のソース電極および前記第2のソース電極の各短辺長は0.3mm以下であり、
前記第1のソース電極および前記第2のソース電極は、各々複数の電極からなり、
前記第1のソース電極を構成する複数の電極および前記第2のソース電極を構成する複数の電極の少なくとも一方のうち、前記境界線側に配置された電極とその隣り合う電極との間隔は、前記半導体層の短辺側に配置された電極とその隣り合う電極との間隔より狭い
半導体装置。 - 前記第1のソース電極を構成する複数の電極および前記第2のソース電極を構成する複数の電極の少なくとも一方における隣り合う電極の間隔は、前記境界線側から前記短辺側に向かうにつれて広い
請求項5に記載の半導体装置。 - フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
互いに背向する第1主面および第2主面を有する半導体層と、
互いに背向する第3主面および第4主面を有し、前記第3主面が前記第2主面に接触して形成され、銀からなり、厚さが30μm以上かつ60μmより薄い第1の金属層と、
互いに背向する第5主面および第6主面を有し、前記第5主面が前記第4主面に接触して形成され、ニッケルからなる第2の金属層と、
前記半導体層内の第1の領域に形成された第1の縦型MOSトランジスタと、
前記第1の領域と前記第1主面に沿った方向で隣接する、前記半導体層内の第2の領域に形成された第2の縦型MOSトランジスタと、を有し、
前記半導体層は、
前記第1主面および前記第2主面のうちの前記第2主面側に配置され、第1導電型の不純物を含むシリコンからなる半導体基板と、
前記第1主面および前記第2主面のうちの前記第1主面側に配置され、前記半導体基板に接触して形成され、前記半導体基板の前記第1導電型の不純物の濃度より低い濃度の前記第1導電型の不純物を含む低濃度不純物層と、を有し、
前記第1の縦型MOSトランジスタは前記低濃度不純物層の表面に第1のソース電極および第1のゲート電極を有し、
前記第2の縦型MOSトランジスタは前記低濃度不純物層の表面に第2のソース電極および第2のゲート電極を有し、
前記第1のソース電極および前記第1のゲート電極と、前記第2のソース電極および前記第2のゲート電極とは、前記半導体層を平面視した場合に、前記半導体層の長辺を2分する境界線に対して線対称の位置に形成され、
前記半導体基板は、前記第1の縦型MOSトランジスタの第1のドレイン領域および前記第2の縦型MOSトランジスタの第2のドレイン領域の共通ドレイン領域として機能し、
前記第1のソース電極から前記第1のドレイン領域、前記第1の金属層および前記第2のドレイン領域を経由した前記第2のソース電極までの双方向経路を主電流経路とし、
前記半導体層の長辺長と短辺長の比は1.73以下であり、
前記第1のソース電極および前記第2のソース電極における各電極の面積と周辺長との比は0.127以下であり、
前記第1のソース電極、前記第1のゲート電極、前記第2のソース電極、および前記第2のゲート電極の各面積の総和は2.61mm 2 以下であり、
前記第1のソース電極および前記第2のソース電極の各短辺長は0.3mm以下であり、
前記第1のソース電極および前記第2のソース電極は、各々複数の電極からなり、
前記第1のソース電極を構成する複数の電極および前記第2のソース電極を構成する複数の電極の少なくとも一方の各々の面積は、前記第1のゲート電極および前記第2のゲート電極を構成する各電極の面積より小さく、
前記少なくとも一方の前記複数の電極の各々とその隣り合う電極との間隔は、前記第1のゲート電極および前記第2のゲート電極を構成する各電極の幅より狭い
半導体装置。
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