TWI420620B - 功率裝置晶片級封裝及其製法 - Google Patents

功率裝置晶片級封裝及其製法 Download PDF

Info

Publication number
TWI420620B
TWI420620B TW096129303A TW96129303A TWI420620B TW I420620 B TWI420620 B TW I420620B TW 096129303 A TW096129303 A TW 096129303A TW 96129303 A TW96129303 A TW 96129303A TW I420620 B TWI420620 B TW I420620B
Authority
TW
Taiwan
Prior art keywords
layer
power
power bus
array
integrated circuit
Prior art date
Application number
TW096129303A
Other languages
English (en)
Other versions
TW200818417A (en
Inventor
Hang Jiang Hunt
Original Assignee
Monolithic Power Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=39049829&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TWI420620(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Monolithic Power Systems Inc filed Critical Monolithic Power Systems Inc
Publication of TW200818417A publication Critical patent/TW200818417A/zh
Application granted granted Critical
Publication of TWI420620B publication Critical patent/TWI420620B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

功率裝置晶片級封裝及其製法 【相關申請案】
本申請要求於2006年8月9日提交的美國臨時申請No.60/836,746的優先權，其全部內容合併在此作為參考。
本發明涉及半導體裝置封裝技術，特別涉及利用倒裝互連的晶片(chip)級封裝。
在現有的晶片級封裝技術中，晶片級封裝的典型尺寸已減小到相當接近矽裸片(die)的尺寸。與此同時，在包含積體電路，諸如大功率開關模式電壓調節器電路(功率器件)的現代裸片晶片中，對高電流、低電壓的需求繼續增加。因此，裸片晶片製造商面臨著在高電流處理能力與這種功率器件尺寸之間的取捨問題。即，要達到高電流的處理能力，器件的尺寸必須既厚且大，以處理大功率和使功率器件能夠散熱。而另一方面，為了減小功率器件的尺寸，每個功率器件處理的電流通常減少。
圖1A示出在裸片尺寸與其電流處理能力之間取捨的現有技術半導體晶片100的俯視圖。現有技術半導體晶片100包括：襯底101、絕緣層102、焊盤103和接觸區域104的陣列。襯底101還包括預製的積體電路，例如大功率開關模式電壓調節器積體電路和金屬傳導通路(未圖示)。絕緣層102，如二氧化矽(SiO2 )或氮化矽(Si3 N4 )膜，設置在襯底101和焊盤103之上。焊盤103可以包括大功率 開關模式電壓調節器積體電路的源極、汲極和柵極。在焊盤103正上方的絕緣層102上形成多個開口，從而形成接觸區104的陣列。
圖1B描述了圖1A的現有技術半導體晶片100沿著接觸區104縱向(Y-方向)的截面圖。如圖所示，現有技術半導體晶片100包括具有焊盤103的襯底101，該襯底101被絕緣層102覆蓋。絕緣層102包括焊盤103上方的多個開口，該開口形成接觸區104。圖1C為圖1A的現有技術半導體晶片100沿著接觸區104橫向(X-方向)的截面圖。如圖所示，每個傳統的金屬接觸區104橫向長度(X-方向)等於其縱向長度(Y-方向)。當運載高電流的開關模式電壓調節器積體電路用於半導體晶片100時，功效因高互連電阻產生的高導通損耗導致的散熱而被降低。在高電流和高功效級別上，在積體電路裝置中有三個主要地方的互連電阻可以減小：電路封裝、元件和互連。其中，電路封裝和互連是影響高互連電阻最重要的兩個因素。這在汲源導通電阻(RDS(ON) )因半導體製造工藝提高而明顯減小的情況下尤為突出。因此，對於如今消費電子的性能和操作來說，包含實現低互連電阻的大功率電晶體的晶片級封裝十分重要。
在對高電流處理能力的要求持續提高時，半導體晶片100和它的晶片級封裝不能進一步減小互連電阻。這是因為裝有半導體晶片100的現有半導體晶片級封裝不能減小互連電阻，而這隨著輸出電流量的增大變得越來越重要。 而且，隨著半導體晶片100和接觸區104的減小，焊盤103相應的電流密度增大。而高電流密度會因接觸區104的鋁粒子電遷移到襯底101而引起器件故障。甚至，電遷移現象還可能造成包含半導體晶片100的現有晶片級封裝出現斷路情況。
本發明的目的在於提供一種用於大功率積體電路的晶片級封裝，該封裝包括半導體晶片，具有電連接到所述大功率積體電路的電源匯流排陣列，以及多條多層凸點下金屬化電源匯流排，互相平行設置並且穿越所述半導體晶片的整個長度，所述多條多層凸點下金屬化電源匯流排電連接到所述電源匯流排陣列，並且還包括具有使互連球設置其上的幾何形狀的厚金屬層。
本發明的另一個目的在於提供一種用於大功率積體電路的晶片級封裝的方法。該方法包括在半導體晶片上形成積體電路；並且形成電源匯流排陣列，所述電源匯流排陣列與所述積體電路電連接；形成多層凸點下金屬化電源匯流排，該電源匯流排包括位於所述電源匯流排陣列中互相平行的每條電源匯流排上方的厚金屬層，所述多層凸點下金屬化電源匯流排與所述積體電路通過所述電源匯流排陣列電連接；並且在所述多層凸點下金屬化電源匯流排上形成互連球陣列。
這裏對多個優先方案實施例進行了具體的描述，實施 例見附圖。雖然本發明使用實施例進行描述，但應該理解本發明表述範圍不僅局限於實施例描述的內容。本發明旨在覆蓋權利要求書中定義的屬於本發明精神和範圍的代替技術，修改技術和其他等同技術。此外，在下述的詳細說明中描述了很多的具體細節，旨在促進對本發明的深入理解，當然，本領域的普通技術人員應能很清楚的瞭解，本發明可以脫離其中某些具體細節而符合本發明精神。另外，為了使本發明說明書主題清晰，涉及到的本領域熟知的方法、流程、部件和電路未進行具體描述。
參見圖2A、圖2B、圖2C，示出了本發明大功率電晶體積體電路的結構和佈局。
參見圖2A，示出了包含大功率電晶體積體電路的半導體晶片200的俯視圖。該大功率積體電路包含直接位於襯底201上的電源匯流排203的陣列。在一種實施方式中，電源匯流排203陣列是襯底201上金屬層的一部分。襯底201包括一個預製的大功率積體電路，如雙擴散金屬氧化物半導體(DMOS)開關模式電壓調節器(圖中未表示)。在本發明的一種實施方式中，大功率積體電路包含電晶體組206的陣列。每個電晶體組206形成於兩條電源匯流排203之間。在圖2A描述的實施例中，頂部電源匯流排203表示電晶體組206的汲極金屬，底部電源匯流排203表示電晶體組206的源極金屬。在本發明的一種實施方式中，每條電源匯流排203基本上穿越襯底201的整個長度並且彼此平行。之後，絕緣層202覆蓋襯底201的整個區域和 電源匯流排203陣列。在絕緣層202上沿每條電源匯流排203的長度方向刻蝕開口，以形成接觸區域204陣列。
現在參見圖2B，示出沿圖2A中的半導體晶片200的寬度方向(Y方向)的截面圖。確切地說，圖2B顯示了半導體晶片200的全部垂直層結構，該半導體晶片包含襯底201，襯底201上有預製的大功率積體電路，並被絕緣層202覆蓋，該絕緣層在電源匯流排203陣列上具有開口。每個開口限定了接觸區域204。從Y方向來看，每條電源匯流排的寬度遠小於襯底201的尺寸。本發明的一個實施例中，接觸區域204的寬度(Y方向)大約為20到200微米。
圖2C描述了圖2A中半導體晶片200沿長度方向(X方向)的截面圖。圖2C示出除每條電源匯流排203的長度之外，和圖2B中的半導體晶片200一樣的結構層。每條電源匯流排203的長度完全穿越襯底201的長度。在本發明的一個實施例中，電源匯流排203的長度在200到2000微米之間。在製造過程中，本發明中含電源匯流排203陣列的半導體晶片200可以用傳統工藝製造。
由於上述結構和尺寸，接觸區域204陣列增大了大功率積體電路的總體有效接觸面，因而降低了互連電阻，提高了襯底201上預製積體電路的大電流運載能力。
現在參見圖3A，示出本發明另一個實施例的半導體晶片300的截面圖。如圖所示，半導體晶片300包括設置於襯底301之上的電源匯流排302陣列，覆蓋電源匯流排302 陣列的絕緣層303，設置於絕緣層303之上的可選的第一介電層304，設置於第一介電層304上的第一多層凸點下金屬化(UBM)電源匯流排30612 、覆蓋於多層UBM電源匯流排30612 和第一介電層204之上的第二介電層307、沉積於第二介電層307上的互連球陣列308。互連球陣列308為多層UBM電源匯流排30612 提供電接觸和機械接觸。在本發明的一種實施方式中，多層UBM電源匯流排30612 還包括作為粘合層的中間凸點下金屬化(UBM)層3061 和厚金屬層3062 。
圖3A中的襯底301可由矽(Si)，砷化鎵(GaAs)或其他可用於製造大功率積體電路的材料構成。此外，電源匯流排302陣列設置於襯底301上。在一種實施方式中，電源匯流排陣列形成大功率積體電路的汲極金屬和源極金屬。絕緣層303可為氮化矽(Si3 N4 )或氧化矽(SiO2 )層，典型厚度為約0.5微米到2微米，並充分覆蓋襯底301，並被剝離以形成開口。開口由熟知的光刻工藝刻蝕得到，開口沿每條電源匯流排302橫向分佈，形成接觸區域311。在本發明的一種實施方式中，可選的厚度為2微米到10微米的介質多聚物層可沉積在絕緣層301上。在本發明一種實施方式中，每條多層UBM電源匯流排30612 包括中間層凸點下金屬化(UBM)3061 和厚銅層3062 。中間層UBM層3061 和厚銅層3062 具有較大的面積使得它超出接觸區域311向外延展。厚銅層3062 遠比中間UBM層3061 厚。厚銅層3062 厚度在5-30微米之間，這取決於裸片300設計 厚度和工藝的最大容許值。中間UBM層3061 為薄鈦/銅層，厚度為0.2-1微米。在另一種實施方式中，厚銅層3062 可由銅(Cu)和鉻(Cr)合金構成。在本發明的一個實施方案中，在銅層3062 上覆蓋一層鎳(Ni)/金(Gold)層用於防止厚銅層3062 的氧化。
第一介電層304和第二介電層307可採用聚醯亞胺或苯並環丁烯(BCB)類材料，介電層304和307的厚度約為5-10微米。第二介電層307上的開口位於厚銅層3062 之上，形成焊接潤濕區域，其上將沉積互連球308。在一種實施方式中，互連球308為焊料(Pb/Sn)球，直徑在150到650微米之間，採用傳統電鍍、焊膏或者焊球放置方法。
圖3B是晶片級封裝300B的俯視圖，其包含了圖3A中所示的半導體晶片300。從圖中可見，接觸區域311陣列暴露出並由開口限定。在本實施例中，在電源匯流排302上方絕緣層303(未圖示)上刻蝕了數目、長度不等的開口，以形成接觸區域311。比如，第一行和第二行各含有四個接觸區域311，而第三行有六個接觸區域311。虛線表示的大面積的厚金屬層3062 位於接觸區域311上方。在一種實施方式中，在厚金屬層3062 上製造了應力釋放凹槽或刻痕310用於熱和機械應力的釋放。採用應力釋放凹槽310避免中間UBM層3061 下與應力有關的斷裂和移位。如圖中所示，互連球308可位於接觸盤311正上方或多層UBM電源匯流排30612 的擴展部分上方，沉積於厚金屬層3062 上。
圖3A至圖3B中描述的具有上述結構的晶片級封裝300B通過熟知的積體電路和晶片級封裝工藝製造。因此，通過電源匯流排302電耦合到包含厚金屬層3062 的大而厚的平行多層UBM電源匯流排30612 ，晶片級封裝300B具有大電流運載能力和低互連電阻。
圖4A是本發明一個大功率器件400實施例的俯視圖，其中大功率器件400包含附著在引線框上的晶片級封裝。在本方案中，術語倒裝連接是指將半導體倒裝裸片(如晶片級封裝)倒裝焊在襯底(如引線框結構)上的方法，其中半導體倒裝裸片通過互連球連接到襯底上。
大功率器件400含有引線框401、封在保護成型材料406中的半導體倒裝裸片410。有一點要提出的是，半導體倒裝裸片可以是包含互連球或球柵陣列(BGA)的任何一種封裝形式。圖4A所示的實施例中，半導體倒裝裸片410是一晶片級封裝411，該封裝和圖3A和圖3B中描述的晶片級封裝300B類似。引線框401含有至少兩個電氣引線：第一電氣引線401A和第二電氣引線402B。第一電氣引線401A包含了單邊伸展的梳齒式結構404A。第二電氣引線402B也包含了單邊伸展的梳齒式結構404B。第一電氣引線402A和第二電氣引線402B並排放置，使得梳齒式結構404A和和404B共面並排列成交錯的圖案(交叉指形)。每一梳齒式結構(404A和404B)的表面上形成有將互連球連接到引線框401上的接觸盤415的圖案。因此，晶片級封裝411通過第一電氣引線402A和第二電氣引線402B形 成機械接觸和電接觸。
圖4B是大功率器件400沿軸AB的截面圖。如圖所示，晶片級封裝401通過互連球308連接到梳齒式金屬結構404A上。沿軸AB，只有第一電氣引線402A的梳齒式結構404A可見，第二電氣引線402B的梳齒式結構404B位於梳齒式結構402A下方不可見(因為402A和402B共面)。晶片級封裝411具有有源正面411T和相應的反面411B。反面411B不是有源面，不含積體電路。正面411T是有源面，含有多層UBM電源匯流排30612 。如圖4B所示，引線框401和晶片級封裝411被成型化合物材料406包封，留出第一電氣引線402A和第二電氣引線402B在外底面上，和外部電路(未圖示)接觸。在當前實施方式中，引線框401結構可以為無引線封裝，如雙邊無引線扁平封裝(DFN)或四邊無引線扁平封裝(QFN)。需要提出，本發明中的引線框結構401還可以包含在其他使用引線結構的封裝，如小外形塑膠封裝(SOIC)或薄型小外形塑膠封裝(TSSOP)。
含梳齒式金屬結構404A和404B並相互交叉的引線框401和其他與本發明相關器件屬於美國專利“一種大功率器件倒裝焊引線框和製造方法”的解釋範疇，該專利於2006年8月24日受理，專利申請號為60840237，合併在此作為參考。
圖4A和圖4B中引線框結構401降低了總體電路電阻(RTOT )，因此降低了高電流引起的熱量。更準確的說，引 線框401的總電阻等於器件電阻(RDS(ON) )、互連電阻(RINT )和封裝電阻(RP )的和：RTOT =RINT +RDS(ON) +RP 。並排交叉的梳齒式結構404A和404B降低了封裝電阻(RP )。互連球415T1 ,415T2 ，和415T3 的應用進一步降低了互連電阻(RINT )和器件電阻(RDS(ON) )。此外，厚的梳齒式銅結構404A和404B可以使晶片級封裝411運載大電流。
圖5是具有大電流運載能力、低互連電阻的大功率積體電路晶片級封裝的工藝過程500。工藝過程500包括：在半導體晶片上製作大功率積體電路；在大功率積體電路上製作電源匯流排陣列；製作平行的多層凸點下金屬化(UBM)電源匯流排，其包括位於電源匯流排陣列中相互平行的每條電源匯流排上的厚金屬層，其中多層UBM電源匯流排電連接到大功率積體電路；最後，在多層UBM電源匯流排上形成互連球陣列。
步驟501：在襯底上製作大功率積體電路。將無缺陷的矽晶圓沿水準和垂直方向切割，形成一組裸片。晶圓的表面經過淨化和化學拋光。然後，通過傳統的表面工藝將大功率積體電路如大功率金屬氧化物半導體場效應電晶體(MOSFET)開關模式電壓調節器製作到裸片上。在一種實施方式中，大功率MOSFET開關模式電壓調節器被分割成低位元開關單元陣列和高位開關單元陣列。每個開關單元由圖2中的一個電晶體組206組成。
步驟502：製作電源匯流排。步驟502由圖2A至2C中的電源匯流排203陣列或圖3A、圖3B中的電源匯流排 302陣列實現。
步驟503：在開口上形成包括預定厚度和幾何形狀的厚金屬(例如銅)層的多層UBM焊盤，通過圖3A和3B中詳細描述的多層UBM電源匯流排30612 實現步驟503。另外，步驟503的多層UBM電源匯流排可以通過化學蒸汽沉積作用(CVD)、等離子加強化學蒸汽沉積作用(PECVD)或者包括反應濺射法或蒸發過程的物理蒸汽沉積作用(PVD)形成。
最後，步驟504：互連球以預定的間隔和距離設置在多層UBM電源匯流排上。預定的間距由工業標準決定。更具體的說，第二非焊錫絕緣層首先覆蓋在第一介電層和多層UBM電源匯流排的厚銅UBM層上。第二介電層和厚金屬層上設置開口，使得互連球可以被安放、流回和冷卻，以便接觸外部器件。互連球和電線連接相比具有較低的互連阻抗。在一個實施例中，互連球可以是焊錫球，通過焊錫球放置或者以屏印刷焊錫膏方式設置在多層UBM電源匯流排上。在另外一個實施例中，互連球可以是鍍金的球。
因此，本發明提供一種用於半導體裝置，尤其是大功率積體電路的封裝，具有較低互連阻抗和最優的熱流性能，具有出眾的熱性能的晶片級封裝。本發明中的封裝概念與晶片級封裝尺寸概念一致，是指封裝尺寸是其裸片尺寸的1.8倍。通過對引線框進行設計使得其能夠幫助晶片處理大電流和減少互連層。
顯然，根據上述的啟示對本發明進行一些修改和變換 是可能的。因此，可以理解在權利要求書範圍內，本發明可以以說明書具體描述以外的其他方式實施。當然，也可以理解，前面的公開僅僅與本發明的優選實施方式相關，他人可以做出未與權利要求書覆蓋的保護範圍和保護精神有所區別的各種修改。這種修改是可以預見的，對於本領域普通技術人員來說它們顯然未超出與權利要求定義的本發明保護的範圍和精神。
100、200、300‧‧‧半導體晶片
101、201、301‧‧‧襯底
102、202、303‧‧‧絕緣層
103、‧‧‧焊盤
104、204、311‧‧‧接觸區域
203、302、30612 ‧‧‧電源匯流排
206‧‧‧電晶組體
300B、411‧‧‧晶片級封裝
304‧‧‧第一介電層
307‧‧‧第二介電層
3061 ‧‧‧金屬化(UBM)層
3062 ‧‧‧厚銅層
308、415T1 、415T2 、415T3 ‧‧‧互連球
310‧‧‧凹槽
400‧‧‧大功率器件
401‧‧‧引線框
402A‧‧‧第一電氣引線
402B‧‧‧第二電氣引線
404A、404B‧‧‧梳齒式結構
406‧‧‧成型材料
410‧‧‧半導體倒裝裸片
415‧‧‧接觸盤
500‧‧‧工藝過程
以下附圖作為說明書的一部分，與說明書一起，對本發明具體實施方式進行闡釋，用於本發明原理的解釋。
圖1A是表示現有技術半導體晶片的俯視圖，該半導體晶片的金屬連接區陣列中每個連接區的長度(X-方向)和寬度(Y-方向)基本相等。
圖1B是表示圖1A中的現有技術半導體晶片Y-方向的橫截面視圖，顯示了襯底、絕緣層、焊盤、和接觸區。
圖1C是表示圖1A中的現有技術半導體晶片X-方向的橫截面視圖，顯示了襯底、絕緣層、焊盤、和金屬接觸區。
圖2A為根據本發明一個實施例的裸片水平面的俯視圖，該裸片的電源匯流排陣列電連接於電晶體組。
圖2B是根據本發明一個實施例的圖2A中的半導體晶片的Y-方向的橫截面視圖，顯示了襯底、絕緣層、電源匯流排陣列和接觸區。
圖2C是根據本發明一個實施例的圖2A中的半導體晶片的X-方向的橫截面視圖，顯示了襯底、絕緣層、電源匯流排。
圖3A是根據本發明一個實施例的半導體晶片的示意性截面圖，該半導體晶片具有襯底、絕緣層、電源匯流排、第一介電層、具有幾何形狀，延伸到定義接觸區的開口邊緣之外的多層凸點下金屬化(UBM)電源匯流排、第二介電層、設置在多層UBM電源匯流排延伸部分上的互連球。
圖3B為根據本發明的一個實施例的裝有圖3A中的半 導體晶片的晶片級封裝的俯視圖，該晶片級封裝具有電源匯流排陣列，從電源匯流排的可以設置互連球的一邊延伸的平行多層UBM電源匯流排。
圖4A為根據本發明一個實施例的引線框結構的俯視圖，包括具有多層UBM電源匯流排陣列和電源匯流排陣列的晶片級封裝。
圖4B為根據本發明一個實施例的表示圖4A中的沿著AB軸方向的引線框封裝的局部示意圖。
圖5為根據本發明一個實施例的用於大功率積體電路的晶片級封裝的製作流程圖。
200‧‧‧半導體晶片
201‧‧‧襯底
202‧‧‧絕緣層
203‧‧‧電源匯流排
204‧‧‧接觸區域
206‧‧‧電晶體組

Claims (21)

  1. 一種晶片級封裝，用於大功率積體電路，包括：半導體晶片，具有電連接到所述大功率積體電路的電源匯流排陣列，以及多條多層凸點下金屬化電源匯流排，互相平行設置並且穿越所述半導體晶片的整個長度，所述多條多層凸點下金屬化電源匯流排電連接到所述電源匯流排陣列，並且還包括具有使互連球設置其上的幾何形狀的厚金屬層。
  2. 如申請專利範圍第1項所述的晶片級封裝，還包括位於所述大功率積體電路上的絕緣層，所述絕緣層包括至少一個限定接觸區域的開口，在所述接觸區域所述多條多層凸點下金屬化電源匯流排與所述電源匯流排陣列電接觸。
  3. 如申請專利範圍第2項所述的晶片級封裝，還包括位於所述絕緣層上的第一介電層，所述第一介電層用於對所述絕緣層提供壓力釋放。
  4. 如申請專利範圍第3項所述的晶片級封裝，還包括直接設置在所述多條多層凸點下金屬化電源匯流排上的第二介電層，所述第二介電層具有第二開口，所述互連球位於該第二開口中且固定於所述厚金屬層上。
  5. 如申請專利範圍第2項所述的晶片級封裝，其中所述多條多層凸點下金屬化電源匯流排的每條電源匯流排還包括位於每個所述接觸區域和所述絕緣層之上的中 間凸點下金屬化層，所述中間凸點下金屬化層與所述大功率積體電路通過所述開口電連接。
  6. 如申請專利範圍第5項所述的晶片級封裝，其中所述中間凸點下金屬化層包含鈦/銅合金，且具有亞微米厚度。
  7. 如申請專利範圍第2項所述的晶片級封裝，其中所述多條多層凸點下金屬化電源匯流排的每條電源匯流排延伸到超過所述開口的邊緣，其表面面積遠大於每個所述接觸區域的面積。
  8. 如申請專利範圍第7項所述的晶片級封裝，其中所述多條多層凸點下金屬化電源匯流排的每條電源匯流排包括多個位於其表面上的壓力釋放槽。
  9. 如申請專利範圍第1項所述的晶片級封裝，其中所述厚金屬層包含銅材料，且具有5微米-30微米之間的厚度。
  10. 如申請專利範圍第1項所述的晶片級封裝，其中所述互連球的每個球包括焊接球，每個焊接球具有50微米-650微米之間的直徑。
  11. 如申請專利範圍第1項所述的晶片級封裝，其中所述互連球具有300微米-1000微米之間的間距。
  12. 如申請專利範圍第1項所述的晶片級封裝，其中所述大功率積體電路還包括：電晶體組陣列，每個所述電晶體組還包括多個電晶體，以及 所述電源匯流排陣列中的每條電源匯流排還包括汲極電源匯流排和源極電源匯流排，所述汲極電源匯流排電連接所述電晶體組中所述多個電晶體的所有汲極，所述源極電源匯流排電連接所述電晶體組中所述多個電晶體的所有源極，所述多條多層凸點下金屬化電源匯流排平行設置在所述汲極電源匯流排和所述源極電源匯流排上方，用於與所述大功率積體電路連通。
  13. 如申請專利範圍第12項所述的晶片級封裝，其中所述多個電晶體中的每個電晶體包括雙擴散金屬氧化物半導體(DMOS)。
  14. 一種形成晶片級封裝的方法，包括：在半導體晶片上形成積體電路；並且形成電源匯流排陣列，所述電源匯流排陣列與所述積體電路電連接；形成多層凸點下金屬化電源匯流排，該電源匯流排包括位於所述電源匯流排陣列中互相平行的每條電源匯流排上方的厚金屬層，所述多層凸點下金屬化電源匯流排與所述積體電路通過所述電源匯流排陣列電連接；及在所述多層凸點下金屬化電源匯流排上形成互連球陣列。
  15. 如申請專利範圍第14項所述的方法，還包括：在所述半導體晶片上設置絕緣層；並且在所述絕緣層上方直接蝕刻至少一個開口，以產生接 觸區域陣列。
  16. 如申請專利範圍第14項所述的方法，還包括：在所述多層凸點下金屬化電源匯流排的表面上形成多個壓力釋放槽。
  17. 如申請專利範圍第14項所述的方法，還包括：在形成所述多層凸點下金屬化電源匯流排之前，在所述電源匯流排陣列上形成中間凸點下金屬化層；並且在所述厚金屬層上形成多個互連凸點。
  18. 如申請專利範圍第16項所述的方法，還包括：在所述絕緣層上直接形成第一介電層；及在所述第一介電層和所述多層凸點下金屬化電源匯流排上直接形成第二介電層，其中所述第二介電層包括多個開口，所述多個互連凸點位於所述開口中。
  19. 一種大功率積體電路器件，包括：晶片級封裝，包括半導體晶片，該半導體晶片具有電連接到大功率積體電路的電源匯流排陣列和互相平行設置並且穿越所述半導體晶片的整個長度的多條多層凸點下金屬化電源匯流排，所述多條多層凸點下金屬化電源匯流排與所述電源匯流排陣列電連接，並且還包括具有使互連球設置其上的幾何形狀的厚金屬層；及引線框封裝，具有至少兩個電氣引線，每個電氣引線具有多個梳齒式結構，對所述至少兩個電氣引線進行排列使得所述多個梳齒式結構形成交叉指形圖案，在 所述交叉指形圖案處所述晶片級封裝被所述互連球連接。
  20. 如申請專利範圍第19項所述的大功率積體電路器件，其中所述多條多層凸點下金屬化電源匯流排的每條電源匯流排還包括中間凸點下金屬化層。
  21. 如申請專利範圍第19項所述的大功率積體電路器件，其中所述大功率積體電路還包括：電晶體組陣列，每個所述電晶體組還包括多個電晶體；及所述電源匯流排陣列中的每條電源匯流排還包括汲極電源匯流排和源極電源匯流排，所述汲極電源匯流排電連接所述電晶體組中所述多個電晶體的所有汲極，所述源極電源匯流排電連接所述電晶體組中所述多個電晶體的所有源極，所述多層凸點下金屬化電源匯流排平行設置在所述汲極電源匯流排和所述源極電源匯流排上方，用於與所述功率積體電路連通。
TW096129303A 2006-08-09 2007-08-08 功率裝置晶片級封裝及其製法 TWI420620B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83674606P 2006-08-09 2006-08-09
US11/835,232 US7944048B2 (en) 2006-08-09 2007-08-07 Chip scale package for power devices and method for making the same

Publications (2)

Publication Number Publication Date
TW200818417A TW200818417A (en) 2008-04-16
TWI420620B true TWI420620B (zh) 2013-12-21

Family

ID=39049829

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096129303A TWI420620B (zh) 2006-08-09 2007-08-08 功率裝置晶片級封裝及其製法

Country Status (3)

Country Link
US (1) US7944048B2 (zh)
CN (1) CN101202266B (zh)
TW (1) TWI420620B (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7999364B2 (en) * 2006-08-24 2011-08-16 Monolithic Power Systems, Inc. Method and flip chip structure for power devices
US7882482B2 (en) * 2007-10-12 2011-02-01 Monolithic Power Systems, Inc. Layout schemes and apparatus for high performance DC-DC output stage
US7705476B2 (en) * 2007-11-06 2010-04-27 National Semiconductor Corporation Integrated circuit package
US20090160039A1 (en) * 2007-12-20 2009-06-25 National Semiconductor Corporation Method and leadframe for packaging integrated circuits
US8085553B1 (en) 2007-12-27 2011-12-27 Volterra Semiconductor Corporation Lead assembly for a flip-chip power switch
US7989953B1 (en) 2007-12-28 2011-08-02 Volterra Semiconductor Corporation Flip chip power switch with under bump metallization stack
US9070670B2 (en) 2009-01-29 2015-06-30 International Rectifier Corporation Electrical connectivity of die to a host substrate
US8278769B2 (en) * 2009-07-02 2012-10-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Compound semiconductor device and connectors
US8400784B2 (en) * 2009-08-10 2013-03-19 Silergy Technology Flip chip package for monolithic switching regulator
CN102034823B (zh) * 2009-09-30 2013-01-02 意法半导体研发(深圳)有限公司 用于spu和stog良好性能的功率晶体管的布局和焊盘布图规划
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20110241125A1 (en) * 2010-03-31 2011-10-06 Semtech Corporation Power Semiconductor Device with Low Parasitic Metal and Package Resistance
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US8581343B1 (en) * 2010-07-06 2013-11-12 International Rectifier Corporation Electrical connectivity for circuit applications
US8692360B1 (en) * 2010-07-06 2014-04-08 International Rectifier Corporation Electrical connectivity for circuit applications
JP2012064899A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置およびその製造方法
US9093433B2 (en) * 2010-11-18 2015-07-28 Microchip Technology Incorporated Using bump bonding to distribute current flow on a semiconductor power device
US8513814B2 (en) * 2011-05-02 2013-08-20 International Business Machines Corporation Buffer pad in solder bump connections and methods of manufacture
US8836029B2 (en) * 2012-02-29 2014-09-16 Smsc Holdings S.A.R.L. Transistor with minimized resistance
CN102842564B (zh) * 2012-09-12 2014-06-25 矽力杰半导体技术(杭州)有限公司 集成开关电源的倒装封装装置及其倒装封装方法
US10109609B2 (en) 2014-01-13 2018-10-23 Infineon Technologies Austria Ag Connection structure and electronic component
US9812380B2 (en) * 2014-05-22 2017-11-07 Microchip Technology Incorporated Bumps bonds formed as metal line interconnects in a semiconductor device
US9537338B2 (en) 2014-09-16 2017-01-03 Navitas Semiconductor Inc. Level shift and inverter circuits for GaN devices
US9613891B2 (en) * 2015-02-24 2017-04-04 Navitas Semiconductor, Inc. Electronic packages for flip chip devices
EP3124962B1 (en) * 2015-07-29 2022-09-28 Sensirion AG Gas sensor array and a method for manufacturing thereof
DE102016122162B4 (de) * 2016-11-17 2022-05-05 Infineon Technologies Ag Halbleitervorrichtung mit metallisierungsstrukturen auf gegenüberliegenden seiten eines halbleiterbereichs, halbleiterschaltanordnung und verfahren
US10074597B2 (en) * 2017-01-20 2018-09-11 Infineon Technologies Austria Ag Interdigit device on leadframe for evenly distributed current flow
CN112204719A (zh) * 2018-03-29 2021-01-08 维斯普瑞公司 晶圆级制造具有平面网格阵列接口的设备的系统和方法
US20210249339A1 (en) * 2020-02-10 2021-08-12 Delta Electronics, Inc. Package structures
US11315857B2 (en) * 2020-02-10 2022-04-26 Delta Electronics, Inc. Package structures
CN112713126A (zh) 2020-12-30 2021-04-27 成都芯源系统有限公司 多裸片封装结构、芯片及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187615B1 (en) * 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US20050062156A1 (en) * 2003-06-03 2005-03-24 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738051A (ja) * 1993-07-19 1995-02-07 Hitachi Ltd レジンモールド電子装置およびその製造方法
EP0734059B1 (en) * 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
JPH10135270A (ja) * 1996-10-31 1998-05-22 Casio Comput Co Ltd 半導体装置及びその製造方法
JPH11136111A (ja) * 1997-10-30 1999-05-21 Sony Corp 高周波回路
US6927471B2 (en) * 2001-09-07 2005-08-09 Peter C. Salmon Electronic system modules and method of fabrication
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187615B1 (en) * 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US20050062156A1 (en) * 2003-06-03 2005-03-24 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures

Also Published As

Publication number Publication date
CN101202266A (zh) 2008-06-18
US7944048B2 (en) 2011-05-17
US20080035959A1 (en) 2008-02-14
CN101202266B (zh) 2012-08-08
TW200818417A (en) 2008-04-16

Similar Documents

Publication Publication Date Title
TWI420620B (zh) 功率裝置晶片級封裝及其製法
US8329508B2 (en) Semiconductor die packages using thin dies and metal substrates
JP4308671B2 (ja) ワイヤボンドパッドを有する半導体装置とその製作方法
US20070187823A1 (en) Semiconductor device
US7768065B2 (en) Semiconductor device
US8592984B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
TWI395277B (zh) 晶圓水準的晶片級封裝
EP1176640A2 (en) Contact structure of an integrated power circuit
WO2015157845A1 (en) Embedded packaging for devices and systems comprising lateral gan power transistors
US20200343207A1 (en) Semiconductor device and method of manufacturing the same
KR20070104919A (ko) 플립 칩 장치를 제조하기 위한 구조 및 방법
US6597065B1 (en) Thermally enhanced semiconductor chip having integrated bonds over active circuits
US12021002B2 (en) Warpage control of semiconductor die
US8587135B2 (en) Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electrode edge spacing
US7045831B2 (en) Semiconductor device
JP2011077187A (ja) 半導体装置
US20220254703A1 (en) Semiconductor Device
JP2016219749A (ja) 半導体装置および半導体装置の製造方法
JP7290960B2 (ja) 半導体装置
JP6945037B2 (ja) 半導体装置の製造方法
JPH05152476A (ja) 半導体集積回路装置及びその製造方法及び電子計算機
TW202420447A (zh) 晶粒封裝結構及其形成方法
JPS61194744A (ja) 半導体装置
CN116435276A (zh) 半导体封装结构及其制作方法