CN101202266B - 芯片级封装及其制造方法和大功率集成电路器件 - Google Patents

芯片级封装及其制造方法和大功率集成电路器件 Download PDF

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CN101202266B
CN101202266B CN2007101405433A CN200710140543A CN101202266B CN 101202266 B CN101202266 B CN 101202266B CN 2007101405433 A CN2007101405433 A CN 2007101405433A CN 200710140543 A CN200710140543 A CN 200710140543A CN 101202266 B CN101202266 B CN 101202266B
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power bus
power
integrated circuit
wafer
metallization
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CN101202266A (zh
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蒋航
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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    • H01L2924/181—Encapsulation

Abstract

本发明公开了一种芯片级封装及其制造方法和大功率集成电路器件，所述芯片级封装包括半导体裸片，具有电连接到所述大功率集成电路的电源总线阵列，以及多条多层凸点下金属化电源总线，互相平行设置并且穿越所述半导体裸片的整个长度，所述多条多层凸点下金属化电源总线电连接到所述电源总线阵列，并且还包括具有使互连球设置其上的几何形状的厚金属层。

Description

芯片级封装及其制造方法和大功率集成电路器件
技术领域
本发明涉及半导体器件封装技术，特别涉及利用倒装互连的芯片(chip)级封装。
背景技术
在现有的芯片级封装技术中，芯片级封装的典型尺寸已减小到相当接近硅裸片(die)的尺寸。与此同时，在包含集成电路，诸如大功率开关模式电压调节器电路(功率器件)的现代裸片芯片中，对高电流、低电压的需求继续增加。因此，裸片芯片制造商面临着在高电流处理能力与这种功率器件尺寸之间的取舍问题。即，要达到高电流的处理能力，器件的尺寸必须既厚且大，以处理大功率和使功率器件能够散热。而另一方面，为了减小功率器件的尺寸，每个功率器件处理的电流通常减少。
图1A示出在裸片尺寸与其电流处理能力之间取舍的现有技术半导体裸片100的俯视图。现有技术半导体裸片100包括：衬底101、绝缘层102、焊盘103和接触区域104的阵列。衬底101还包括预制的集成电路，例如大功率开关模式电压调节器集成电路和金属传导通路(未图示)。绝缘层102，如二氧化硅(SiO2)或氮化硅(Si3N4)膜，设置在衬底101和焊盘103之上。焊盘103可以包括大功率开关模式电压调节器集成电路的源极、漏极和栅极。在焊盘103正上方的绝缘层102上形成多个开口，从而形成接触区104的阵列。
图1B描述了图1A的现有技术半导体裸片100沿着接触区104纵向(Y-方向)的截面图。如图所示，现有技术半导体裸片100包括具有焊盘103的衬底101，该衬底101被绝缘层102覆盖。绝缘层102包括焊盘103上方的多个开口，该开口形成接触区104。图1C为图1A的现有技术半导体裸片100沿着接触区104横向(X-方向)的截面图。如图所示，每个传统的金属接触区104横向长度(X-方向)等于其纵向长度(Y-方向)。当运载高电流的开关模式电压调节器集成电路用于半导体裸片100时，功效因高互连电阻产生的高导通损耗导致的散热而被降低。在高电流和高功效级别上，在集成电路装置中有三个主要地方的互连电阻可以减小：电路封装、元件和互连。其中，电路封装和互连是影响高互连电阻最重要的两个因素。这在漏源导通电阻(RDS(ON))因半导体制造工艺提高而明显减小的情况下尤为突出。因此，对于如今消费电子的性能和操作来说，包含实现低互连电阻的大功率晶体管的芯片级封装十分重要。
在对高电流处理能力的要求持续提高时，半导体裸片100和它的芯片级封装不能进一步减小互连电阻。这是因为装有半导体裸片100的现有半导体芯片级封装不能减小互连电阻，而随着输出电流量的增大，减小互连电阻变得越来越重要。而且，随着半导体裸片100和接触区104的减小，焊盘103相应的电流密度增大。而高电流密度会因接触区104的铝粒子电迁移到衬底101而引起器件故障。甚至，电迁移现象还可能造成包含半导体裸片100的现有芯片级封装出现断路情况。
发明内容
因此本发明的目的在于提供一种能够进一步减小互连电阻的芯片级封装。
为实现上述目的，本发明公开了一种用于大功率集成电路的芯片级封装，该封装包括半导体裸片，具有电连接到所述大功率集成电路的电源总线阵列，以及多条多层凸点下金属化电源总线，互相平行设置并且穿越所述半导体裸片的整个长度，所述多条多层凸点下金属化电源总线电连接到所述电源总线阵列，并且还包括具有使互连球设置其上的几何形状的厚金属层。
为实现上述目的，本发明还公开了一种用于大功率集成电路的芯片级封装的方法。该方法包括在半导体裸片上形成集成电路；并且形成电源总线阵列，所述电源总线阵列与所述集成电路电连接；形成多层凸点下金属化电源总线，该电源总线包括位于所述电源总线阵列中互相平行的每条电源总线上方的厚金属层，所述多层凸点下金属化电源总线与所述集成电路通过所述电源总线阵列电连接；并且在所述多层凸点下金属化电源总线上形成互连球阵列。
为实现上述目的，本发明还公开了一种大功率集成电路器件。该器件包括芯片级封装和引线框封装。其中所述芯片级封装包括半导体裸片，该半导体裸片具有电连接到大功率集成电路的电源总线阵列和互相平行设置并且穿越所述半导体裸片的整个长度的多条多层凸点下金属化电源总线，所述多条多层凸点下金属化电源总线与所述电源总线阵列电连接，并且还包括具有使互连球设置其上的几何形状的厚金属层；所述引线框封装具有至少两个电气引线，每个电气引线具有多个梳齿式结构，对所述至少两个电气引线进行排列使得所述多个梳齿式结构形成交叉指形图案，在所述交叉指形图案处所述芯片级封装被所述互连球连接。
本发明的优点在于，所提供的半导体器件的芯片级封装、方法及其大功率集成电路器件具有较低互连阻抗和最优的热流性能。
附图说明
图1A是表示现有技术半导体裸片的俯视图，该半导体裸片的金属连接区阵列中每个连接区的长度(X-方向)和宽度(Y-方向)基本相等。
图1B是表示图1A中的现有技术半导体裸片Y-方向的横截面视图，显示了衬底、绝缘层、焊盘、和接触区。
图1C是表示图1A中的现有技术半导体裸片X-方向的横截面视图，显示了衬底、绝缘层、焊盘、和金属接触区。
图2A为根据本发明一个实施例的裸片水平面的俯视图，该裸片的电源总线阵列电连接于晶体管组。
图2B是根据本发明一个实施例的图2A中的半导体裸片的Y-方向的横截面视图，显示了衬底、绝缘层、电源总线阵列和接触区。
图2C是根据本发明一个实施例的图2A中的半导体裸片的X-方向的横截面视图，显示了衬底、绝缘层、电源总线。
图3A是根据本发明一个实施例的半导体裸片的示意性截面图，该半导体裸片具有衬底、绝缘层、电源总线、第一介电层、具有几何形状，延伸到定义接触区的开口边缘之外的多层凸点下金属化(UBM)电源总线、第二介电层、设置在多层UBM电源总线延伸部分上的互连球。
图3B为根据本发明的一个实施例的装有图3A中的半导体裸片的芯片级封装的俯视图，该芯片级封装具有电源总线阵列，从电源总线的可以设置互连球的一边延伸的平行多层UBM电源总线。
图4A为根据本发明一个实施例的引线框结构的俯视图，包括具有多层UBM电源总线阵列和电源总线阵列的芯片级封装。
图4B为根据本发明一个实施例的表示图4A中的沿着AB轴方向的引线框封装的局部示意图。
图5为根据本发明一个实施例的用于大功率集成电路的芯片级封装的制作流程图。
具体实施方式
这里对多个优先方案实施例进行了具体的描述，实施例见附图。虽然本发明使用实施例进行描述，但应该理解本发明表述范围不仅局限于实施例描述的内容。本发明旨在覆盖权利要求书中定义的属于本发明精神和范围的代替技术，修改技术和其他等同技术。此外，在下述的详细说明中描述了很多的具体细节，旨在促进对本发明的深入理解，当然，本领域的普通技术人员应能很清楚的了解，本发明可以脱离其中某些具体细节而符合本发明精神。另外，为了使本发明说明书主题清晰，涉及到的本领域熟知的方法、流程、部件和电路未进行具体描述。
参见图2A、图2B、图2C，示出了本发明大功率晶体管集成电路的结构和布局。
参见图2A，示出了包含大功率晶体管集成电路的半导体裸片200的俯视图。该大功率集成电路包含直接位于衬底201上的电源总线203的阵列。在一种实施方式中，电源总线203阵列是衬底201上金属层的一部分。衬底201包括一个预制的大功率集成电路，如双扩散金属氧化物半导体(DMOS)开关模式电压调节器(图中未表示)。在本发明的一种实施方式中，大功率集成电路包含晶体管组206的阵列。每个晶体管组206形成于两条电源总线203之间。在图2A描述的实施例中，顶部电源总线203表示晶体管组206的漏极金属，底部电源总线203表示晶体管组206的源极金属。在本发明的一种实施方式中，每条电源总线203基本上穿越衬底201的整个长度并且彼此平行。之后，绝缘层202覆盖衬底201的整个区域和电源总线203阵列。在绝缘层202上沿每条电源总线203的长度方向刻蚀开口，以形成接触区域204阵列。
现在参见图2B，示出沿图2A中的半导体裸片200的宽度方向(Y方向)的截面图。确切地说，图2B显示了半导体裸片200的全部垂直层结构，该半导体裸片包含衬底201，衬底201上有预制的大功率集成电路，并被绝缘层202覆盖，该绝缘层在电源总线203阵列上具有开口。每个开口限定了接触区域204。从Y方向来看，每条电源总线的宽度远小于衬底201的尺寸。本发明的一个实施例中，接触区域204的宽度(Y方向)大约为20到200微米。
图2C描述了图2A中半导体裸片200沿长度方向(X方向)的截面图。图2C示出除每条电源总线203的长度之外，和图2B中的半导体裸片200一样的结构层。每条电源总线203的长度完全穿越衬底201的长度。在本发明的一个实施例中，电源总线203的长度在200到2000微米之间。在制造过程中，本发明中含电源总线203阵列的半导体裸片200可以用传统工艺制造。
由于上述结构和尺寸，接触区域204阵列增大了大功率集成电路的总体有效接触面，因而降低了互连电阻，提高了衬底201上预制集成电路的大电流运载能力。
现在参见图3A，示出本发明另一个实施例的半导体裸片300的截面图。如图所示，半导体裸片300包括设置于衬底301之上的电源总线302阵列，覆盖电源总线302阵列的绝缘层303，设置于绝缘层303之上的可选的第一介电层304，设置于第一介电层304上的第一多层凸点下金属化(UBM)电源总线30612、覆盖于多层UBM电源总线30612和第一介电层304之上的第二介电层307、沉积于第二介电层307上的互连球阵列308。互连球阵列308为多层UBM电源总线30612提供电接触和机械接触。在本发明的一种实施方式中，多层UBM电源总线30612还包括作为粘合层的中间凸点下金属化(UBM)层3061和厚金属层3062。在一种实施方式中，第一介电层304用于对绝缘层303提供应力释放。
图3A中的衬底301可由硅(Si)，砷化镓(GaAs)或其他可用于制造大功率集成电路的材料构成。此外，电源总线302阵列设置于衬底301上。在一种实施方式中，电源总线阵列形成大功率集成电路的漏极金属和源极金属。绝缘层303可为氮化硅(Si3N4)或氧化硅(SiO2)层，典型厚度为约0.5微米到2微米，并充分覆盖衬底301，并被剥离以形成开口。开口由熟知的光刻工艺刻蚀得到，开口沿每条电源总线302横向分布，形成接触区域311。在本发明的一种实施方式中，可选的厚度为2微米到10微米的介质多聚物层可沉积在绝缘层301上。在本发明一种实施方式中，每条多层UBM电源总线30612包括中间层凸点下金属化(UBM)3061和厚铜层3062。中间层UBM层3061和厚铜层3062具有较大的面积使得它超出接触区域311向外延展。厚铜层3062远比中间UBM层3061厚。厚铜层3062厚度在5-30微米之间，这取决于裸片300设计厚度和工艺的最大容许值。中间UBM层3061为薄钛/铜层，厚度为0.2-1微米。在另一种实施方式中，厚铜层3062可由铜(Cu)和铬(Cr)合金构成。在本发明的一个实施方案中，在铜层3062上覆盖一层镍(Ni)/金(Gold)层用于防止厚铜层3062的氧化。
第一介电层304和第二介电层307可采用聚酰亚胺或苯并环丁烯(BCB)类材料，介电层304和307的厚度约为5-10微米。第二介电层307上的开口位于厚铜层3062之上，形成焊接润湿区域，其上将沉积互连球308。在一种实施方式中，互连球308为焊料(Pb/Sn)球，直径在150到650微米之间，采用传统电镀、焊膏或者焊球放置方法。
图3B是芯片级封装300B的俯视图，其包含了图3A中所示的半导体裸片300。从图中可见，接触区域311阵列暴露出并由开口限定。在本实施例中，在电源总线302上方绝缘层303(未图示)上刻蚀了数目、长度不等的开口，以形成接触区域311。比如，第一行和第二行各含有四个接触区域311，而第三行有六个接触区域311。虚线表示的大面积的厚金属层3062位于接触区域311上方。在一种实施方式中，在厚金属层3062上制造了应力释放凹槽或刻痕310用于热和机械应力的释放。采用应力释放凹槽310避免中间UBM层3061下与应力有关的断裂和移位。如图中所示，互连球308可位于接触盘311正上方或多层UBM电源总线30612的扩展部分上方，沉积于厚金属层3062上。
图3A-图3B中描述的具有上述结构的芯片级封装300B通过熟知的集成电路和芯片级封装工艺制造。因此，通过电源总线302电耦合到包含厚金属层3062的大而厚的平行多层UBM电源总线30612，芯片级封装300B具有大电流运载能力和低互连电阻。
图4A是本发明一个大功率器件400实施例的俯视图，其中大功率器件400包含附着在引线框上的芯片级封装。在本方案中，术语倒装连接是指将半导体倒装裸片(如芯片级封装)倒装焊在衬底(如引线框结构)上的方法，其中半导体倒装裸片通过互连球连接到衬底上。
大功率器件400含有引线框401、封在保护成型材料406中的半导体倒装裸片410。有一点要提出的是，半导体倒装裸片可以是包含互连球或球栅阵列(BGA)的任何一种封装形式。图4A所示的实施例中，半导体倒装裸片410是一芯片级封装411，该封装和图3A和图3B中描述的芯片级封装300B类似。引线框401含有至少两个电气引线：第一电气引线402A和第二电气引线402B。第一电气引线402A包含了单边伸展的梳齿式结构404A。第二电气引线402B也包含了单边伸展的梳齿式结构404B。第一电气引线402A和第二电气引线402B并排放置，使得梳齿式结构404A和和404B共面并排列成交错的图案(交叉指形)。每一梳齿式结构(404A和404B)的表面上形成有将互连球连接到引线框401上的接触盘415的图案。因此，芯片级封装411通过第一电气引线402A和第二电气引线402B形成机械接触和电接触。
图4B是大功率器件400沿轴AB的截面图。如图所示，芯片级封装401通过互连球308连接到梳齿式金属结构404A上。沿轴AB，只有第一电气引线402A的梳齿式结构404A可见，第二电气引线402B的梳齿式结构404B位于梳齿式结构402A下方不可见(因为402A和402B共面)。芯片级封装411具有有源正面411T和相应的反面411B。反面411B不是有源面，不含集成电路。正面411T是有源面，含有多层UBM电源总线30612。如图4B所示，引线框401和芯片级封装411被成型化合物材料406包封，留出第一电气引线402A和第二电气引线402B在外底面上，和外部电路(未图示)接触。在当前实施方式中，引线框401结构可以为无引线封装，如双边无引线扁平封装(DFN)或四边无引线扁平封装(QFN)。需要提出，本发明中的引线框结构401还可以包含在其它使用引线结构的封装，如小外形塑料封装(SOIC)或薄型小外形塑料封装(TSSOP)。
含梳齿式金属结构404A和404B并相互交叉的引线框401和其它与本发明相关器件属于美国专利“一种大功率器件倒装焊引线框和制造方法”的解释范畴，该专利于2006年8月24日受理，专利申请号为60840237，合并在此作为参考。
图4A和图4B中引线框结构401降低了总体电路电阻(RTOT)，因此降低了高电流引起的热量。更准确的说，引线框401的总电阻等于器件电阻(RDS (ON))、互连电阻(RINT)和封装电阻(RP)的和：RTOT＝RINT+RDS(ON)+RP。并排交叉的梳齿式结构404A和404B降低了封装电阻(RP)。互连球415T1，415T2，和415T3的应用进一步降低了互连电阻(RINT)和器件电阻(RDS(ON))。此外，厚的梳齿式铜结构404A和404B可以使芯片级封装411运载大电流。
图5是具有大电流运载能力、低互连电阻的大功率集成电路芯片级封装的工艺过程500。工艺过程500包括：在半导体裸片上制作大功率集成电路；在大功率集成电路上制作电源总线阵列；制作平行的多层凸点下金属化(UBM)电源总线，其包括位于电源总线阵列中相互平行的每条电源总线上的厚金属层，其中多层UBM电源总线电连接到大功率集成电路；最后，在多层UBM电源总线上形成互连球阵列。
步骤501：在衬底上制作大功率集成电路。将无缺陷的硅晶圆沿水平和垂直方向切割，形成一组裸片。晶圆的表面经过净化和化学抛光。然后，通过传统的表面工艺将大功率集成电路如大功率金属氧化物半导体场效应晶体管(MOSFET)开关模式电压调节器制作到裸片上。在一种实施方式中，大功率MOSFET开关模式电压调节器被分割成低位开关单元阵列和高位开关单元阵列。每个开关单元由图2A中的一个晶体管组206组成。
步骤502：制作电源总线。步骤502由图2A-2C中的电源总线203阵列或图3A、图3B中的电源总线302阵列实现。
步骤503：在开口上形成包括预定厚度和几何形状的厚金属(例如铜)层的多层UBM焊盘，通过图3A和3B中详细描述的多层UBM电源总线30612实现步骤503。另外，步骤503的多层UBM电源总线可以通过化学蒸汽沉积作用(CVD)、等离子加强化学蒸汽沉积作用(PECVD)或者包括反应溅射法或蒸发过程的物理蒸汽沉积作用(PVD)形成。
最后，步骤504：互连球以预定的间隔和距离设置在多层UBM电源总线上。预定的间距由工业标准决定。更具体的说，第二非焊锡绝缘层首先覆盖在第一介电层和多层UBM电源总线的厚铜UBM层上。第二介电层和厚金属层上设置开口，使得互连球可以被安放、流回和冷却，以便接触外部器件。互连球和电线连接相比具有较低的互连阻抗。在一个实施例中，互连球可以是焊锡球，通过焊锡球放置或者以屏印刷焊锡膏方式设置在多层UBM电源总线上。在另外一个实施例中，互连球可以是镀金的球。
因此，本发明提供一种用于半导体器件，尤其是大功率集成电路的封装，具有较低互连阻抗和最优的热流性能，具有出众的热性能的芯片级封装。本发明中的封装概念与芯片级封装尺寸概念一致，是指封装尺寸是其裸片尺寸的1.8倍。通过对引线框进行设计使得其能够帮助芯片处理大电流和减少互连层。
显然，根据上述的启示对本发明进行一些修改和变换是可能的。因此，可以理解在权利要求书范围内，本发明可以以说明书具体描述以外的其他方式实施。当然，也可以理解，前面的公开仅仅与本发明的优选实施方式相关，他人可以做出未与权利要求书覆盖的保护范围和保护精神有所区别的各种修改。这种修改是可以预见的，对于本领域普通技术人员来说它们显然未超出与权利要求定义的本发明保护的范围和精神。

Claims (20)

1.一种用于大功率集成电路的芯片级封装，包括：
半导体裸片，具有电连接到所述大功率集成电路的电源总线阵列，以及
多条多层凸点下金属化电源总线，互相平行设置并且穿越所述半导体裸片的整个长度，所述多条多层凸点下金属化电源总线电连接到所述电源总线阵列，并且所述多条多层凸点下金属化电源总线还包括具有使互连球设置其上的几何形状的厚金属层，其中所述厚金属层包含铜材料且具有5微米-30微米之间的厚度。
2.根据权利要求1所述的芯片级封装，还包括位于所述大功率集成电路上的绝缘层，所述绝缘层包括至少一个限定接触区域的开口，在所述接触区域所述多条多层凸点下金属化电源总线与所述电源总线阵列电接触。
3.根据权利要求2所述的芯片级封装，还包括位于所述绝缘层上的第一介电层，所述第一介电层用于对所述绝缘层提供应力释放。
4.根据权利要求3所述的芯片级封装，还包括直接设置在所述多条多层凸点下金属化电源总线上的第二介电层，所述第二介电层具有第二开口，所述互连球位于该第二开口中且固定于所述厚金属层上。
5.根据权利要求2所述的芯片级封装，其中所述多条多层凸点下金属化电源总线的每条电源总线还包括位于每个所述接触区域和所述绝缘层之上的中间凸点下金属化层，所述中间凸点下金属化层与所述大功率集成电路通过所述开口电连接。
6.根据权利要求5所述的芯片级封装，其中所述中间凸点下金属化层包含钛/铜合金，且具有亚微米厚度。
7.根据权利要求2所述的芯片级封装，其中所述多条多层凸点下金属化电源总线的每条电源总线延伸到超过所述开口的边缘，其表面面积远大于每个所述接触区域的面积。
8.根据权利要求7所述的芯片级封装，其中所述多条多层凸点下金属化电源总线的每条电源总线包括多个位于其表面上的应力释放槽。
9.根据权利要求1所述的芯片级封装，其中所述互连球的每个球包括焊接球，每个焊接球具有50微米-650微米之间的直径。
10.根据权利要求1所述的芯片级封装，其中所述互连球具有300微米-1000微米之间的间距。
11.根据权利要求1所述的芯片级封装，其中所述大功率集成电路还包括：
晶体管组阵列，每个所述晶体管组还包括多个晶体管，以及
所述电源总线阵列中的每条电源总线还包括漏极电源总线和源极电源总线，所述漏极电源总线电连接所述晶体管组中所述多个晶体管的所有漏极，所述源极电源总线电连接所述晶体管组中所述多个晶体管的所有源极，所述多条多层凸点下金属化电源总线平行设置在所述漏极电源总线和所述源极电源总线上方，用于与所述大功率集成电路连通。
12.根据权利要求11所述的芯片级封装，其中所述多个晶体管中的每个晶体管包括双扩散金属氧化物半导体。
13.一种形成芯片级封装的方法，包括：
在半导体裸片上形成大功率集成电路；并且
形成电源总线阵列，所述电源总线阵列与所述大功率集成电路电连接；
形成互相平行设置并且穿越所述半导体裸片整个长度的多条多层凸点下金属化电源总线，该电源总线包括位于所述电源总线阵列中互相平行的每条电源总线上方的厚金属层，其中所述厚金属层包含铜材料且具有5微米-30微米之间的厚度，所述多层凸点下金属化电源总线与所述大功率集成电路通过所述电源总线阵列电连接；并且
在所述多层凸点下金属化电源总线上形成互连球阵列。
14.根据权利要求13所述的方法，还包括：
在所述半导体裸片上设置绝缘层；并且
在所述绝缘层上方直接蚀刻至少一个开口，以产生接触区域阵列。
15.根据权利要求13所述的方法，还包括：
在所述多层凸点下金属化电源总线的表面上形成多个应力释放槽。
16.根据权利要求13所述的方法，还包括：
在形成所述多层凸点下金属化电源总线之前，在所述电源总线阵列上形成中间凸点下金属化层；并且
在所述厚金属层上形成多个互连凸点。
17.根据权利要求14所述的方法，还包括：
在所述绝缘层上直接形成第一介电层；并且
在所述第一介电层和所述多层凸点下金属化电源总线上直接形成第二介电层，其中所述第二介电层包括多个开口，所述互连球阵列中的互连球位于所述第二介电层的所述多个开口中。
18.一种大功率集成电路器件，包括：
芯片级封装，包括半导体裸片，该半导体裸片具有电连接到大功率集成电路的电源总线阵列和互相平行设置并且穿越所述半导体裸片的整个长度的多条多层凸点下金属化电源总线，所述多条多层凸点下金属化电源总线与所述电源总线阵列电连接，并且还包括具有使互连球设置其上的几何形状的厚金属层，其中所述厚金属层包含铜材料且具有5微米-30微米之间的厚度；并且
引线框封装，具有至少两个电气引线，每个电气引线具有多个梳齿式结构，对所述至少两个电气引线进行排列使得所述多个梳齿式结构形成交叉指形图案，在所述交叉指形图案处所述芯片级封装被所述互连球连接。
19.根据权利要求18所述的大功率集成电路器件，其中所述多条多层凸点下金属化电源总线的每条电源总线还包括中间凸点下金属化层。
20.根据权利要求18所述的大功率集成电路器件，其中所述大功率集成电路还包括：
晶体管组阵列，每个所述晶体管组还包括多个晶体管；并且
所述电源总线阵列中的每条电源总线还包括漏极电源总线和源极电源总线，所述漏极电源总线电连接所述晶体管组中所述多个晶体管的所有漏极，所述源极电源总线电连接所述晶体管组中所述多个晶体管的所有源极，所述多层凸点下金属化电源总线平行设置在所述漏极电源总线和所述源极电源总线上方，用于与所述大功率集成电路连通。
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