TWI423415B - 具有低阻值基材與低損耗功率之半導體結構 - Google Patents

具有低阻值基材與低損耗功率之半導體結構 Download PDF

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TWI423415B
TWI423415B TW100103795A TW100103795A TWI423415B TW I423415 B TWI423415 B TW I423415B TW 100103795 A TW100103795 A TW 100103795A TW 100103795 A TW100103795 A TW 100103795A TW I423415 B TWI423415 B TW I423415B
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semiconductor
conductive
substrate
conductive material
hole
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TW201234552A (en
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Chih Cheng Hsieh
Hsiu Wen Hsu
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Niko Semiconductor Co Ltd
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Description

具有低阻值基材與低損耗功率之半導體結構
本發明係關於一種半導體結構，尤其是一種低損耗功率之半導體結構。
對於功率金氧半導體的應用而言，最主要的重點在於其電氣規格優劣與散熱能力，而影響其最大的參數為汲極與源極之導通電阻Rds(ON)，一般而言，Rds(ON)大致上包含晶片本身的導通電阻與封裝時所形成的阻抗，因此如何降低兩者的阻值，已成為重要的課題。一般傳統垂直型之功率金氧半導體，如第一圖所示，其基材101之厚度佔整體晶片之九成以上，然而其基材阻值佔整體晶片阻值之比重，會隨著功率金氧半導體之製程電壓降低而增加，例如，600伏特之製程，其基材阻值約佔整個晶片阻值3~5%，至於30伏特以下之製程，其基材阻值會大幅增加至佔整個晶片阻值約15~30%。於是，降低基材阻值，一直以來為低壓製程之功率半導體之努力方向。傳統降低基材阻值之作法，會使用晶片減薄技術，將功率金氧半導體晶片之厚度由7~12mil以機械方式磨薄至2~4mil後，如第二圖減薄基材之垂直型功率金氧半導體結構所示，再將減薄之晶片，進行後續之半導體封裝製程，但如此薄之晶片，在後續之製程與運送過程中，造成破片的機率大幅增加，為了保護好如此薄的晶片，在每一道過程中，都必須要增加額外的處理程序與設備來保護晶片避免晶片破裂，因而導致成本大幅提升。再者，在封裝打線過程中，晶片必須承受瞬間應力，如此薄之晶片，容易潛在著微形破裂的風險，造成產品可用壽命大幅降低。因而如何有效改善功率半導體元件使其擁有低導通電阻(Low Rds(ON))，並進一步降低成本，且能有效的降低裂片之風險，已成了急需解決之問題。
因此，尋找一個低汲極與源極間電阻(Low Rds)之半導體結構，以克服習知技術之種種缺失，是本技術領域一個重要之課題。
本發明之主要目的在於以矽穿孔技術來降低汲極與源極間之電阻，進而減少功率半導體運作過程中能量的損耗。
本發明提供一種半導體結構。此半導體結構包括一半導體單元，一第一導電結構，一第一導電物質與一第二導電結構。其中，半導體單元具有一基材，此基材位於半導體單元之一側並且具有至少一個孔洞。第一導電物質，位於上述之孔洞內，以填滿或不填滿孔洞之方式存在。第一導電結構，位於半導體單元之側邊之一表面。第二導電結構，位於半導體單元之不同於半導體基材之另一側表面。本發明利用基材孔洞裡低阻值之第一導電物質，取代原本高阻值之基材，因此能有效降低基材之電阻(Low Rds)，進而降低半導體結構導通時之功率損耗，此外，基材裡之第一導電物質，能把半導體結構操作時，內部產生之熱，傳導到外部之第一導電結構，以達到良好之散熱效果，使得半導體結構擁有更久之使用壽命與更低之功率耗損。再者，本發明在不增加額外設備的情形下，可延續使用目前封裝廠產能之優勢，進一步降低功率損耗與潛藏的裂片風險。
第三(A)圖顯示本發明之低損耗功率半導體結構之第一實施例。如第三(A)圖所示，一半導體單元300具有一基材301，至少一孔洞302於基材301內，其中孔洞302可以矽穿孔(TSV)之方式完成。一導電物質303位於孔洞302內，一導電結構304位於基材301與導電物質303之表面。此導電結構304，即做為此功率半導體之一汲極電極。一源極電極308與一閘極電極309位於半導體單元300之一表面310。透過孔洞302中的導電結構304來部分或全部取代阻抗值較大的基材301，可達到降低半導體單元300之阻值之優點。
第三(A)至第三(C)圗為本發明低損耗功率半導體結構之第一實施例之製作方法。如第三(B)圖所示，首先，提供一半導體單元300，該半導體單元300具有一半導體磊晶層311與該基材301，並將該半導體單元300固定於一晶圓載具312。然後，將此固定完成之晶圓載具結構，進行該半導體單元300之該基材301研磨製程。該半導體磊晶層311厚度a約為10um，，該基材301基材厚度b約為750um。為了清楚說明本發明，圖示比例並非實際比例縮小，因此標上數值，藉以說明實際之比例關係。如第三(C)圖所示，先將該半導體單元之該基材301厚度b研磨至約170um，然後，將光阻圖型化(未圖示)，定義出基材301之至少一孔洞302之相對位置。接下來，利用蝕刻方式進行矽穿孔製程，製作出該孔洞302，該孔洞302之底部至半導體磊晶層311之距離c約為30um，接著沉積一導電物質303於孔洞302內，該導電物質303可以將孔洞302部份填滿或全部填滿。該孔洞302之形狀，依矽穿孔之方式而有不同，並不限制於本說明書所圖示之形狀。上述該孔洞302之底部至半導體磊晶層311之距離c亦可為零。最後，如第三(A)圖所示，將晶圓載具(未圖示)移除，接著沉積一金屬導電結構304於該基材301與該導電物質303之表面。
第四(A)圖顯示本發明之低損耗功率半導體結構之第二實施例。其中與第一實施例之差異處，在一導電物質403與一導電結構404為同一導電物質。其製作方法之差異為，該導電物質403與該導電結構404於同一步驟形成，皆於光阻(未圖示)與晶圓載具(未圖示)移除後，同時沉積一導電物質403於基材401之表面與孔洞402內，可藉由控制導電物質403之沉積時間，來調整該導電物質403是否填滿於孔洞402內。上述該導電物質，可為金屬TiNiAg合金或是純銅，並以蒸鍍方式完成，本案提出較佳效果之金屬，但使用金屬之種類，並不限定於以上所述之金屬。
第四(B)圖顯示本發明之低損耗功率半導體結構之第三實施例。其中與第二實施例之差異處，在於孔洞內導電物質與導電結構之形成。一導電物質403存於孔洞402內，一導電結構404位於基材401與導電物質403之表面。上述之導電物質404可為大於5微米(μm)之金屬銅，導電物質403可為約0.15微米(μm)之金屬鈦Ti，此金屬鈦層可用來防止金屬銅擴散到半導體磊晶層411。雖金屬鈦層可不用填滿於孔洞402，但仍以填滿孔洞所裸露之半導體磊晶層411之表面為佳。
第五圖顯示本發明之低損耗功率半導體結構之第四實施例。其中與第一實施例之差異處，在於一通道之形成。如第五圖所示，一通道512於半導體單元500內，一導電物質513於通道512內，藉此透過通道512連接一導電結構504。一汲極電極514位於導電物質513上，藉由導電物質513電性連結至導電結構504。其中，汲極電極514可以省略，而直接以導電物質513當成汲極使用。汲極電極514之位置，可部分或全部於半導體單元之表面510上，有達到電性連接到導電物質513之作用即可，因此汲極電極514之面積大小可根據實際電路設計調整，可大於或小於導電物質之面積，並不侷限於本圖示所示之結構。上述通道512可以矽穿孔(TSV)之方式完成，且導電物質513、汲極電極514與導電結構504可為相同之金屬。
第六圖顯示本發明之低損耗功率半導體結構之第四實施例之封裝結構。將完成矽穿孔之半導體結構，以晶片級封裝CSP(Chip Scale Package)之方式完成封裝。晶片級封裝結構包括一保護層615來隔絕半導體單元600與外界接觸，避免受到外在之環境污染(例如：氧化或濕氣)，亦可做為電性絕緣之用。一金屬層(Under Bump Metallurgy)616，位在於汲極電極614、源極電極608與閘極電極609上，一銅棒617位於金屬層616上，銅棒617上存在一錫鉛凸塊618。此封裝結構之底部存在一導電結構624，此導電結構可為厚度大於5微米(μm)之金屬銅，可將半導體結構內部之熱，傳導至外部，有助於散熱，亦可於導電結構外加上一層絕緣層，防止此結構運用於電路時，發生短路之情況。於此封裝結構上，亦可直接加裝散熱片幫助散熱，來降低功率元件運作時之溫度。
第七(A)圖至第七(D)圖顯示第六圖所示的封裝結構之汲極電極、源極電極與閘極電極位置之設計編排方式。如第七(A)圖所示，汲極電極714配置於兩側邊，源極電極708與閘極電極709配置於汲極電極714之間，閘極電極709為單一，源極電極708為兩個以承受大電流之應用。如第七(B)圖所示，汲極電極714配置於側邊，源極電極708與閘極電極709配置於汲極電極714之間，源極電極708為單一但具有大於閘極電極709之面積。上述之汲極電極714亦可只存在於單一側邊。如第七(C)圖所示，亦可將汲極電極714配置於四週，源極電極與閘極電極則與第七(A)圖或第七(B)圖相同。如第七(D)圖所示，上述之汲極電極亦配置於離邊緣之一距離存在。
第八圖顯示本發明之低損耗功率半導體結構之第一實施至第三實施例之封裝結構。將完成矽穿孔之半導體單元300，以傳統之封裝方式完成封裝，其利用銀膠固定於導線架819上，最後，用銲線820把源極電極821與閘極電極822連結到封裝結構之接腳823。
此發明之低損耗功率半導體結構，利用基材孔洞裡之低阻值導電物質，取代原本高阻值之基材，因此能有效之降低基材之電阻(Low Rds)，並大幅降低功率損耗，此外，基材裡之導電物質，更能把功率半導體操作時，內部產生之熱，傳導到外部之導電結構或導線架，以達到良好之散熱效果，使得功率半導體擁有更久之使用壽命與更低之功率耗損。此發明之結構也可以應用在其他功能性之半導體與積體電路(IC)，只要擁有基材並且擁有兩個以上之電極(包含兩個電極)皆適用，如第九圖所示，此為IGBT(雙極電晶體)元件，於其基材上形成孔洞902，再將導電物質903形成於孔洞之中，形成本發明之結構，亦可降低其功率損耗與元件操作時之溫度。
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單之等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。另外本發明之任一實施例或申請專利範圍不須達成本發明所揭露之全部目之或優點或特點。此外，摘要部分和標題僅是用來輔助專利文件搜尋之用，並非用來限制本發明之權利範圍。
309,609,709‧‧‧閘極電極
308,608,708,821,822‧‧‧源極電極
514,614,714‧‧‧汲極電極
300,500,600‧‧‧半導體單元
101,301,401‧‧‧基材
302,402,902‧‧‧孔洞
303,513,403,903‧‧‧導電物質
304,504,404,624‧‧‧導電結構
310,510‧‧‧半導體單元之一表面
311,411‧‧‧半導體磊晶層
312‧‧‧晶圓載具
512‧‧‧通道
615‧‧‧保護層
616‧‧‧一金屬層(Under Bump Metallurgy)
617‧‧‧銅棒
618‧‧‧錫鉛凸塊
819‧‧‧導線架
820‧‧‧銲線
823‧‧‧封裝結構之接腳
第一圖顯示先前技術之傳統垂直型金氧半導體結構。
第二圖顯示先前技術之減薄基材之垂直型功率金氧半導體結構。
第三(A)圖顯示本發明之低損耗功率半導體結構之第一實施例。
第三(A)至第三(C)圗顯示本發明低損耗功率半導體結構之第一實施例之製作方法。
第四(A)圖顯示本發明之低損耗功率半導體結構之第二實施例。
第四(B)圖顯示本發明之低損耗功率半導體結構之第三實施例。
第五圖顯示本發明之低損耗功率半導體結構之第四實施例。
第六圖顯示本發明之低損耗功率半導體結構之第四實施之封裝結構。
第七(A)圖至第七(D)圖顯示本發明之汲極電極、源極電極與閘極電極位置之設計編排方式。
第八圖顯示本發明之低損耗功率半導體結構之第一實施至第三實施例之封裝結構。
第九圖顯示本發明之應用於IGBT(雙極電晶體)元件
500．．．半導體單元
504．．．導電結構
510．．．半導體單元之一表面
512．．．通道
513．．．導電物質
514．．．汲極電極

Claims (8)

  1. 一種半導體結構，包括：一半導體單元，具有一基材，該基材位於該半導體單元之一側並具有至少一個孔；一第一導電結構，位於該半導體單元之該側之一表面，其中該第一導電結構係作為該半導體單元上之一汲極電極；一第一導電物質，位於該基材之該孔內並與該第一導電結構電性連接；一第二導電結構，位於該半導體單元之一另一側之一表面，其中該第二導電結構係作為該半導體單元上之一源極電極；以及一第三導電結構，位於該半導體單元之該另一側之該表面，其中該第三導電結構係作為該半導體單元上之一閘極電極；其中該孔位於第一導電結構與第二導電結構之間。
  2. 如申請專利範圍第1項之半導體結構，其中，該半導體單元，更包括：一第四導電結構，位於該半導體單元之該另一側之該表面；一通道，位於該半導體單元內；以及一第二導電物質，位於該通道內，透過該通道以電性連結該第一導電結構與該第四導電結構。
  3. 如申請專利範圍第1項之半導體結構，其中，以矽穿孔(TSV)之方式形成該基材之該孔。
  4. 如申請專利範圍第2項之半導體結構，其中，以矽穿孔(TSV)之方式形成該通道。
  5. 如申請專利範圍第2項之半導體結構，其中該半導體單元以晶片型封裝方式(CSP)進行封裝，以形成一封裝結構。
  6. 如申請專利範圍第5項之半導體結構，更包括一散熱模組於該封裝結構上。
  7. 如申請專利範圍第2項之半導體結構，其中，第一導電物質與第二導電物質可為相同之物質。
  8. 如申請專利範圍第1項之半導體結構，其中，第一導電物質 與第一導電結構可為相同之物質。
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