TWI578470B - 半導體裝置和半導體裝置的製造方法 - Google Patents

半導體裝置和半導體裝置的製造方法 Download PDF

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TWI578470B
TWI578470B TW102104383A TW102104383A TWI578470B TW I578470 B TWI578470 B TW I578470B TW 102104383 A TW102104383 A TW 102104383A TW 102104383 A TW102104383 A TW 102104383A TW I578470 B TWI578470 B TW I578470B
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layer
copper
solder material
semiconductor device
connection terminal
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TW102104383A
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English (en)
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TW201349416A (zh
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宇野哲史
土屋秀昭
橫川慎二
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瑞薩電子股份有限公司
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Publication of TW201349416A publication Critical patent/TW201349416A/zh
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Description

半導體裝置和半導體裝置的製造方法
本發明係有關半導體裝置和半導體裝置的製造方法，並且，係有關例如半導體晶片以覆晶方式而被連接至互連基板的半導體裝置以及半導體裝置的製造方法。
覆晶(flip-chip)連接是半導體晶片之安裝型式的其中之一。覆晶連接係致使半導體晶片的主動表面面對互連基板，然後半導體晶片的電極墊及互連基板的端子經由銲材而彼此連接。近年來，為了設法解決電極墊的小型化，已發展出其中之Cu柱係形成於電極墊上，並且銅柱及電極墊藉由銲材而彼此連接之結構。此處，關於銲材，已使用其中並未使用鉛之以錫為基礎的銲材。
另一方面，W.H.WU及其它三人於2009年發表於Journal of ELECTRONIC MATERIALS,Vol.38,NO.12之：「The influence of Current Direction on the Cu-Ni Cross-Interaction in Cu/Sn/Ni Diffusion Couples」一文中，顯示 當錫(Sn)係配置在銅與鎳之間時檢測電遷移的結果。在此文獻中，觀看相片，吾人知道銅與鎳之間的距離約為60至80μm。在此情況下，報告指出因電遷移而在錫中形成有空洞(void)。
當銅柱係設在電極墊上時，由於電遷移，銅從銅柱擴散至以錫為基礎的銲材。當銅擴散至以錫為基礎的銲材時，形成銅及錫的合金，這導致在銲材中形成空洞。當在銲材中形成空洞時，銲材高度有可能會斷裂開。從本說明書的說明及附圖中，將清楚地看出其它問題及新特徵。
在一個實施例中，提供包含電極墊的半導體晶片。銅柱形成在電極墊上。此外，互連基板的連接端子係由含銅的金屬所形成。銅柱及連接端子經由含錫的銲材層而彼此相連接。鎳層係形成在銅柱與銲材層之間或是銲材層與連接端子之間。在銅柱與連接端子之間的上表面之間的距離係等於或小於20μm。
根據此實施例，能夠防止用以連接銅柱至互連基板的連接端子之銲材斷裂開。
INT‧‧‧互連基板
NIL‧‧‧鎳層
PAD‧‧‧電極墊
PIL‧‧‧銅柱
RES‧‧‧光阻膜
SB‧‧‧銲球
SC‧‧‧半導體晶片
SD‧‧‧半導體裝置
SEED‧‧‧層疊膜
SLL‧‧‧聚醯亞胺層
SOL‧‧‧銲材層
TER‧‧‧連接端子
UFR‧‧‧填充樹脂
從配合附圖的某些較佳實施例之下述說明中，將更清楚本發明的上述及其它目的、優點、及特點，其中：圖1是剖面視圖，顯示半導體裝置的配置。
圖2A及2B是平面視圖，顯示半導體晶片。
圖3A及3B是平面視圖，顯示半導體晶片。
圖4是圖1之剖面A-A’的放大視圖。
圖5A及5B顯示圖4中所示的半導體裝置的製造方法。
圖6A及6B顯示圖4中所示的半導體裝置的製造方法。
圖7顯示圖4中所示的半導體裝置的製造方法。
圖8A及8B顯示當在銅柱及連接端子上都設置有鎳層時銲材層的結構變化。
圖9是圖8B的接續。
圖10A及10B顯示實施例的功效。
圖11是剖面視圖，顯示圖4的修改實例。
圖12是剖面視圖，顯示根據第二實施例之半導體裝置中半導體晶片及互連基板的連接結構。
圖13是剖面視圖，顯示圖12的修改實例。
圖14是剖面相片，顯示立即在銅柱及連接端子經由銲材層而彼此連接之後的狀態。
圖15是剖面相片，顯示在銅柱及連接端子之間充電預定時間之後的狀態。
圖16是剖面視圖，顯示圖12的修改實例。
圖17是剖面視圖，顯示圖11的修改實例。
圖18是圖形，顯示銲材層的厚度L與空洞發生率之間的關係。
於此，現在參考說明的實施例來說明本發明。習於此技藝者將瞭解，使用本發明的揭示，能完成很多替代的實施例，並且本發明不限於為了說明目的而顯示之實施例。
於下，將參考附圖來說明本發明的實施例。在所有圖式中，類似的元件以類似的代號及符號來予以表示，且將不重複其說明。
(第一實施例)
圖1是剖面視圖，其顯示根據第一實施例之半導體裝置SD的配置。半導體裝置SD包含半導體晶片SC及互連基板INT。舉例而言，半導體晶片SC是邏輯電路及記憶體電腦具體被實施於其中的晶片，但是，可以僅包含邏輯電路，並且可僅包含記憶體電路。此外，半導體晶片SC包含CoC(晶片上的晶片)結構，其中，多個半導體晶片是疊層的或是SIP(封裝系統)結構。
半導體晶片SC係覆晶地安裝於互連基板INT上。半導體晶片SC包含銅柱PIL，並且經由銅柱PIL而被連接至互連基板INT。半導體晶片SC及互連基板INT的連接部份藉由填充樹脂UFR來予以密封。互連基板INT在與有半導體晶片SC安裝於上的表面相對立側之上的表面上包含銲球SB。銲球SB經由互連基板INT之內的互連及銅柱PIL而被連接至半導體晶片SC的內部電路。
圖2A及2B是平面視圖，其顯示半導體晶片SC，並且顯示銅柱PIL的佈局的第一實例。在圖式中所示的實例中，銅柱PIL係沿著半導體晶片SC的邊緣來予以配置。具體而言，在圖2A中所示的實例中，銅柱PIL僅配置在沿著半導體晶片SC的邊緣的區域中。另一方面，在圖2B中所示的實例中，除了沿著半導體晶片SC的邊緣之區域配置之外，銅柱PIL也被均勻配置在內側的部份中。
圖3A及3B是平面視圖，其顯示半導體晶片SC，並且顯示銅柱PIL的佈局之第二實例。在圖式中所示的實例中，銅柱PIL以矩陣方式而被配置在半導體晶片SC的整個表面上。具體而言，在圖3A中所示的實例中，銅柱PIL係配置在半導體晶片SC的整個表面上。另一方面，在圖3B中所示的實例中，銅柱PIL並未被配置在半導體晶片SC的一部份上。同時，在圖3A及3B中所示的實例中，銅柱PIL係均勻地配置。但是，在區域的一部份上之銅柱PIL的配置間隔係不同於在其它區域上之銅柱PIL的配置間隔。
圖4是圖1的剖面A-A’的放大視圖。半導體晶片SC包含電極墊PAD。銅柱PIL係形成在電極墊PAD上。此外，互連基板INT包含連接端子TER。連接端子TER含有銅。舉例而言，連接端子TER係由銅所形成，並且係形成為例如陸面形狀。但是，連接端子TER可以不被形成為陸面形狀。銅柱PIL及連接端子TER經由銲材層SOL而彼此相連接。銲材層SOL含有錫。或者，鎳層 NIL係形成於銅柱PIL與連接端子TER之間。銲材層SOL的厚度之最小值L係等於或小於20μm。
具體而言，半導體晶片SC包含多層互連層。電極墊PAD係形成於多層互連層的最高層中。保護絕緣膜(鈍化膜)係形成在多層互連層的最上層中。保護絕緣膜包含氧化矽膜、氮化矽膜、及氧氮化矽膜的至少其中之一。用於曝露電極墊PAD的開口係形成在保護絕緣膜中。聚醯亞胺層SLL係形成於保護絕緣膜上。聚醯亞胺層SLL包含在電極墊PAD上的開口。障壁層及晶種層的層疊膜SEED依此次序而被形成於開口之內及電極墊PAD上。障壁層是用來防止銅擴散至電極墊PAD及保護絕緣膜之層，並且係由例如TiN所形成。晶種層是用以致使銅柱PIL藉由電鍍而生長的晶種層，並且係由例如銅所形成。
如上所述，藉由電鍍法來形成銅柱PIL。銅柱PIL的上表面在形狀上可以幾乎是平坦的，並且，凹部及凸部的至少其中之一可被形成於其上。
在實施例中，鎳層NIL係形成於銅柱PIL上。藉由電鍍法來形成鎳層NIL，並且，鎳的含量係等於或大於99重量%。舉例而言，鎳層NIL的厚度係等於或大於0.1μm且等於或小於10μm。
銲材層SOL含有錫，並且不含鉛。舉例而言，在銲層SOL中的錫的含量係等於或大於90重量%，並且，較佳等於或大於95%。銲材層SOL係由例如SnAg所形成。銅柱PIL的上表面及連接端子TER的上表面常常都包含不規則 性。基於此理由，銲材層SOL的厚度常常會變得不均勻。銲材層SOL的厚度的最小值L係等於或小於20μm，較佳等於或小於15μm，且更佳等於或小於11μm。同時，最小值L較佳等於或大於5μm。
圖5A至圖7是剖面視圖，其顯示半導體裝置SD的製造方法的實例。首先，在半導體晶圓上形成元件隔離膜。藉此，元件形成區被隔離。使用例如STI法，但是，可以使用LOCOS法來予以形成，以形成元件隔離膜。接著，閘極絕緣膜及閘極電極形成在位於元件形成區中的半導體晶圓上。閘極絕緣膜可以是氧化矽膜，並且可以是高介電常數膜(舉例而言，矽酸鉿膜)，其介電常數係高於氧化矽膜的介電常數。當閘極絕緣膜是氧化矽膜時，閘極電極係由多晶矽膜所形成。此外，當閘極絕緣膜是高介電常數膜時，閘極電極係由金屬膜(舉例而言，TiN)及多晶矽膜的疊層膜所形成。此外，當閘極電極係由多晶矽所形成時，在形成閘極電極的製程中，多晶矽電阻可以被形成於元件隔離膜上。
接著，源極和汲極的擴充區係形成位在元件形成區中的半導體晶圓上。接著，側壁形成在閘極電極的側壁上。接著，作為源極和汲極的雜質區形成在位於元件形成區中的半導體晶圓上。依此方式，MOS電晶體被形成在半導體晶圓上。
接著，多層互連層係形成在元件隔離膜及MOS電晶體上。電極墊PAD係形成在最上互連層中。接著，保護 絕緣膜(鈍化膜)係形成在多層互連層上。位於電極墊PAD上的開口係形成在保護絕緣膜中。
接著，如圖5A中所示，聚醯亞胺層SLL係形成於保護絕緣膜及電極墊PAD上。接著，藉由使聚醯亞胺層SLL曝光及顯影，在聚醯亞胺層SLL中形成位於電極墊PAD上的開口。接著，舉例而言，藉由濺射法，將障壁層及晶種層的層疊膜SEED形成在聚醯亞胺層SLL上及開口之內。障壁層的一部份係連接至電極墊PAD。
接著，在層疊膜SEED上形成光阻膜RES，並且，將光阻膜RES曝光及顯影。藉此，在光阻膜RES中形成開口。此開口係位於致使銅柱PIL生長的區域中，並且，具體而言，當在平面視圖中來予以觀視時，係形成為包含在內側上的電極墊PAD。
接著，如圖5B中所示，藉由在曝露於層疊膜SEED上的光阻膜RES的開口之內的部份上電鍍，而造成銅生長。藉此，形成銅柱PIL。
接著，如圖6A所示，使用光阻膜RES作為掩罩，藉由電鍍，在銅柱PIL上，依此次序，生長鎳層NIL及銲材層SOL。
接著，如圖6B所示，移除光阻膜RES，並且，進一步移除其中的銅柱PIL並非由層疊膜SEED所形成之部份。
之後，藉由將半導體晶圓切割，半導體晶片SC被切開。
此外，如圖7所示，製備互連基板INT。在互連基板INT的連接端子TER上，形成小的厚度的銲材層SOL。接著，使半導體晶片SC的銅柱PIL面對互連基板INT的連接端子TER，並且，半導體晶片SC以覆晶方式而被連接至互連基板INT。
同時，在處於晶圓狀態的半導體晶片SC以覆晶方式而被連接至互連基板INT之後，藉由晶粒切割，半導體晶片SC及互連基板INT可被切開。
接著，將參考圖8A、8B、9及10來說明實施例的操作及功效。首先，考慮其中鎳層NIL並未被形成於銅柱PIL及連接端子TER上的情況。電流在銅柱PIL與連接端子TER之間雙向地流動。基於此理由，當使用半導體裝置SD時，可觀量的銅從銅柱PLL及連接端子TER被擴散至銲材層SOL中。當可觀量的銅被擴散至銲材層SOL時，擴散出的銅與銲材層SOL內的錫相結合而形成Cu3Sn。Cu3Sn的體積係小於錫單獨存在的情況中的體積。基於此理由，當形成Cu3Sn時，形成克肯岱爾(Kirkendall)空洞。在此情況中，銲材層SOL高度有可能會斷裂開。
接著，參考圖8A、8B及9，考慮鎳層NIL係形成在銅柱PIL及連接端子TER上的情況。在此情況中，即使當銅從銅柱PIL擴散至銲材層SOL時，銅被鎳層NIL所阻擋。此外，即使當銅從連接端子擴散至銲材層SOL時，銅仍被鎳層NIL所阻擋。基於此理由，由於鎳層NIL 的存在，銅及錫的合金不會被形成在銲材層SOL內。
但是，如圖8A所示，鎳及錫的合金，亦即，Ni3Sn的形成從Ni層NIL與銲材層SOL之間的介面作為啟始點而進行。鎳層NIL的全部在某時間點變成Ni3Sn。然後，這與其中鎳層NIL並未被形成在銅柱PIL及連接端子TER上的情況係處於相同的狀態，因此，如圖8B所示，可觀量的銅從銅柱PIL及連接端子TER擴散出。基於此理由，如圖9所示，由於形成Cu3Sn而形成克肯岱爾(Kirkendall)空洞，因此，銲材層SOL高度有可能會斷裂開。
此外，當使用半導體裝置SD時，在銲材層SOL之內的Sn因電遷移而移動於離開Ni3Sn的方向上。基於此理由，在銲材層SOL與Ni3Sn未反應的部份之間的介面形成因錫的電遷移而造成的空洞。在此情況中，銲材層SOL可能在此介面中斷裂開。
另一方面，如圖10A及10B中所示，在實施例中，Ni層NIL係形成在銅柱PIL與連接端子TER之間。基於此理由，Ni3Sn層生長於鎳層NIL與銲材層SOL之間，並且，與此同時地，銅從在連接端子TER與銅柱PIL之間其中並未形成鎳層NIL的其中一者(在圖式中所示的實例中為連接端子TER)擴散出來而進入銲材層SOL中。一部份之擴散出的銅聚集在銲材層SOL與Ni3Sn層之間的介面處，但是，其量係少的。基於此理由，Cu6Sn5層係形成在Ni3Sn層與銲材層SOL之間的介面中。同時，考 慮鎳被包含在Cu6Sn5層中。
另一方面，Cu3Sn層係形成在銲材層SOL與在連接端子TER與銅柱PIL之間其中並未形成有鎳層NIL的其中一者(在圖式中所示的實例中為連接端子TER)之間的介面中。但是，由於銅從連接端子TER或是銅柱PIL中的僅其中之一擴散至銲材層SOL中，所以，銅變短。基於此理由，Cu3Sn層在某時間點切換至Cu6Sn5層。也就是說，在Cu3Sn層首先被形成在銲材層SOL與連接端子TER及銅柱PIL之間並未形成有鎳層NIL的其中一者(在圖式中所示的實例中為連接端子TER)之間之後，Cu6Sn5層被形成在銲材層SOL側上。
之後，當使用半導體裝置SD時，Cu6Sn5層從銅柱PIL側及連接端子TER側生長至銲材層SOL中。Cu6Sn5層比Cu3Sn層消耗量更少。此外，銲材層SOL的厚度的最小值係等於或小於20μm。基於此理由，如圖10B所示，至少一部份的銅柱PIL及至少一部份的連接端子TER經由Cu3Sn層、Cu6Sn5層、及Ni3Sn層相層疊的合金層、及鎳層NIL而彼此相連接。在使用半導體裝置SD的情況之下，此合金層是熱及電穩定的。基於此理由，銅柱PIL及連接端子TER的連接結構在藉由合金層及鎳層NIL而被連接之後變得穩定，因此，斷開的機率低。隨著銲材層SOL的厚度的最小值變得愈小(舉例而言，等於或小於15μm，進一步等於或小於12μm)，此效果變得顯著。
圖18是圖形，其顯示銲材層SOL的厚度L與空洞發 生率之間的關係。在此圖形中，測試條件係設定於175℃的溫度、200mA的電流量、2,000小時的電流時間。當銲材層SOL的厚度是7μm、10μm、11μm、及12μm時，沒有樣品發生空洞(0%)。另一方面，當銲材層SOL的厚度是16μm時，20%的樣品發生空洞，當銲材層SOL的厚度是22μm時，60%的樣品發生空洞。因此，可知銲材層SOL的厚度係等於或小於20μm，較佳等於或小於15μm，更佳等於或小於12μm。
同時，在實施例中，如圖11所示，鎳層NIL係形成在連接端子TER上而不是銅柱PIL上。在此情況中，也取得上述效果。
同時，如圖17所示，連接端子TER從互連基板INT的最上方樹脂層凸出。因此，能夠進一步降低銲材層SOL的最薄部份的厚度。同時，在此情況中，鎳層NIL係形成在連接端子TER的上表面及橫向側上。
(第二實施例)
圖12是剖面視圖，其顯示根據第二實施例的半導體裝置SD中的互連基板INT及半導體晶片SC的連接結構。根據實施例之半導體裝置SD具有與根據第一實施例之半導體裝置SD相同的配置，但是半導體晶片SC的銅柱PIL的形狀除外。
首先，銅柱PIL的上表面係形成為凸狀。凸狀的高度，亦即，上表面(鎳層NIL係形成於其上的表面)的高 度差係等於或大於5μm且等於或小於10μm。
此外，在平行於銅柱PIL的電極墊PAD的表面中的剖面面積隨著距離電極墊PAD的距離增加而增加。
藉由改變第一實施例中圖5至7中所示的光阻膜RES的開口的形狀而實施上述銅柱PIL的形狀。具體而言，在平行於銅柱PIL的電極墊PAD的表面中光阻膜RES的開口的剖面面積隨著距離電極墊PAD的距離增加而增加。
此外，至少連接端子TER的橫向側的上部份被連接至銲材層SOL。
同時，在圖12中所示的實例中，鎳層NIL係形成在銅柱PIL上。但是，如圖13所示，鎳層NIL可被形成在連接端子TER上。
此外，如圖16所示，連接端子TER從互連基板INT的最上方的樹脂層凸出。因此，能夠進一步降低銲材層SOL的最薄部份的厚度。同時，在此情況中，鎳層NIL係形成在連接端子TER的橫向側及上表面上。
在實施例中，也可取得與第一實施例相同的效果。此外，銅柱PIL的上表面係形成為凸狀。基於此原因，銲材層SOL的厚度的最小值很容易被做得更小。
圖14及15是具有圖12中所示的結構之樣品的剖面相片。圖14顯示立即在銅柱PIL與連接端子TER經由銲材層SOL而彼此相連接之後的狀態。銲材層SOL在銅柱PIL側的介面及連接端子TER側的介面中均包含Cu6Sn5層。這被視為是被形成在對銲材層SOL執行回熔 (reflow)的製程中。
圖15顯示在銅柱PIL與連接端子TER之間充電預定時間後的狀態。在圖式中所示的實例中，Cu6Sn5層生長，並且連接鎳層NIL及連接端子TER。在此狀態中，銲材層SOL並未斷裂。
同時，如圖16所示，連接端子TER的上端從互連基板INT的表面凸出。因此，能夠進一步降低銲材層SOL的最薄部份的厚度。
如上所述，雖然根據實施例而具體說明本發明人所實施的發明，但是，無須多言，本發明不限於上述實施例，在不悖離本發明的精神及範圍之下，可以作各種改變及修改。
SC‧‧‧半導體晶片
SEED‧‧‧層疊膜
PAD‧‧‧電極墊
SLL‧‧‧聚醯亞胺層
PIL‧‧‧銅柱
NIL‧‧‧鎳層
SOL‧‧‧銲材層
TER‧‧‧連接端子
INT‧‧‧互連基板
L‧‧‧厚度

Claims (13)

  1. 一種半導體裝置，包括：半導體晶片；以及互連基板，該半導體晶片係覆晶式地安裝於該互連基板之上，其中，該半導體晶片包含：電極墊，及銅柱，係形成在該電極墊之上，該互連基板包含由含有銅的金屬所製成的連接端子，該銅柱及該連接端子經由含錫的銲材層而彼此相連接，鎳層係形成在該銅柱與該銲材層之間的介面和在該銲材層與該連接端子之間的介面的其中一介面中，並且不被形成在另一介面上，而且該銲材層之最薄部分的厚度係等於或小於20μm且等於或大於5μm。
  2. 如申請專利範圍第1項之半導體裝置，其中，該銲材層包含銅及錫的合金層，並且該銅柱的至少一部份及該連接端子的至少一部份經由該合金層而彼此相連接。
  3. 如申請專利範圍第1項之半導體裝置，其中，該銲材層包含銅及錫的合金層，並且，當使電流在該電極墊與該連接端子之間流動時，該合金層生長，而使得該銅柱的至少一部份及該連接端子的至少一部份經由該合金層而彼 此相連接。
  4. 如申請專利範圍第2項之半導體裝置，其中，該合金層包含Cu6Sn5層。
  5. 如申請專利範圍第4項之半導體裝置，其中，該合金層在與該鎳層的介面中包含Ni3Sn層，並且，在該另一介面中包含Cu3Sn層。
  6. 如申請專利範圍第1項之半導體裝置，其中，該銲材層之該最薄部分的該厚度係等於或小於15μm。
  7. 如申請專利範圍第1項之半導體裝置，其中，該銲材層之該最薄部分的該厚度係等於或小於12μm。
  8. 一種半導體裝置，包括：半導體晶片；以及互連基板，該半導體晶片係覆晶式地安裝於該互連基板之上，其中，該半導體晶片包含：電極墊，銅柱，係形成在該電極墊之上，該銅柱的上表面係形成為凸狀，以及銲材層，係形成在該銅柱之上，該銲材層含有錫，該互連基板係由含有銅的金屬所製成，並且包含連接至該銲材層的連接端子，鎳層係形成在該銅柱與該銲材層之間的介面和在該銲材層與該連接端子之間的介面的其中一介面中，並且 不被形成在另一介面上，並且該銲材層包含銅及錫的合金層，而且該銅柱的至少一部份及該連接端子的至少一部份經由該合金層而彼此相連接。
  9. 如申請專利範圍第8項之半導體裝置，其中，該合金層包含Cu6Sn5層。
  10. 如申請專利範圍第9項之半導體裝置，其中，該合金層在與該鎳層的介面中包含Ni3Sn層，並且，在該另一介面中包含Cu3Sn層。
  11. 如申請專利範圍第1項之半導體裝置，其中，該銅柱的上表面係形成為凸狀。
  12. 如申請專利範圍第11項之半導體裝置，其中，該凸狀的高度係等於或大於5μm且等於或小於10μm。
  13. 一種半導體裝置的製造方法，包括：以覆晶方式而將半導體晶片安裝在互連基板中，其中，該半導體晶片包含：電極墊，銅柱，係形成在該電極墊之上，該銅柱的上表面係形成為凸狀，以及銲材層，係形成在該銅柱之上，該銲材層含有錫，該互連基板係由含有銅的金屬所製成，並且包含連接至該銲材層的連接端子，鎳層係形成在該銅柱與該銲材層之間的介面和在該銲材層與該連接端子之間的介面的其中一介面中，並且 不被形成在另一介面上，並且該銲材層之最薄部分的厚度係等於或小於20μm。
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