TWI509776B - 堆疊半導體裝置及其製造方法 - Google Patents
堆疊半導體裝置及其製造方法 Download PDFInfo
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- TWI509776B TWI509776B TW102127224A TW102127224A TWI509776B TW I509776 B TWI509776 B TW I509776B TW 102127224 A TW102127224 A TW 102127224A TW 102127224 A TW102127224 A TW 102127224A TW I509776 B TWI509776 B TW I509776B
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Description
本發明係有關於一種半導體技術,特別為有關於一種堆疊半導體裝置及其製造方法。
被動電子裝置(例如,電容或電感)有時與互補型金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)晶片整合。傳統上,當需要大的電容或電感時,需要使用大尺寸的被動裝置。因此,僅有可能透過外部的電性路徑(例如,焊線接合)內連接上述裝置。再者,當使用較大尺寸的晶片時,需要較長的電性路徑。
傳統的被動裝置或互補型金屬氧化物半導體的整合具有一些缺點。第一,由於電性路徑較長所產生的電性寄生(electrical parasitics)效應會使晶片的效能變差,特別是模塑成型之後。第二,由於需要接合墊將被動裝置焊線接合至互補型金屬氧化物半導體晶片,因此難以縮減系統尺寸。第三,由於被動裝置必須單獨接合至互補型金屬氧化物半導體晶片,因此降低了精密度,而進一步增加了縮減系統尺寸的難度。第四,多個被動裝置與一個互補型金屬氧化物半導體晶片的精密裝配需要多個步驟,使得製造成本增加。
本發明實施例揭示一種堆疊半導體裝置的製造方法,包括提供一第一基板,具有一第一電子裝置及位於第一電子裝置上的一第一接合墊,第一電子裝置電性連接至第一接合墊。提供一第二基板,具有一第二電子裝置及位於第二電子裝置上的一第二接合墊,第二電子裝置電性連接至第二接合墊。將第一基板及第二基板接合在一起,其中第一接合墊及第二接合墊電性內連接。在接合之後,形成一基板通孔電極,從相對於第一接合墊的第一基板的一表面,穿透第一基板至第一接合墊。
本發明實施例揭示一種堆疊半導體裝置的製造方法,包括提供一第一基板,具有一第一電子裝置及位於第一電子裝置上的一第一接合墊。在第一基板上的第一接合墊上沉積一第一絕緣層。在第一絕緣層內形成一第一凹口,第一凹口具有一底部表面低於第一接合墊的一底部表面。提供一第二基板,具有一第二電子裝置及位於第二電子裝置上的一第二接合墊。在第二基板上的第二接合墊上沉積一第二絕緣層。在第二絕緣層內形成一第二凹口,以暴露出第二接合墊的一部份。將第一凹口對準於第二凹口,且將第一絕緣層接合至第二絕緣層。在接合之後,形成一基板通孔電極,其從相對於第一接合墊的第一基板的一表面,穿透第一基板至第一凹口。
本發明實施例揭示一種堆疊半導體裝置,包括一第一基板。一第一接合墊位於第一基板上。一第二基板包括一第二電子裝置形成於其上。一第二接合墊位於第二基板上的第
二電子裝置上,第二接合墊電性連接第二電子裝置。一第二絕緣層位於具有一上表面的第二接合墊上,且第二絕緣層接合至第一基板的第一接合墊。一基板通孔電極從相對於第一接合墊的一表面穿透第一基板且穿透第二絕緣層的上表面至第二接合墊。
10‧‧‧方法
12、14、16、18、20、22‧‧‧步驟
100、200‧‧‧裝置
110‧‧‧裝置基板
111、130‧‧‧基板
112‧‧‧溝槽電容
114、115、126‧‧‧絕緣層
116‧‧‧導電部件
116a、142‧‧‧下表面
116b‧‧‧最下層的表面/接合墊
120‧‧‧互補型金屬氧化物半導體之金屬層/接合墊
122‧‧‧導電接合材料/接合墊
124‧‧‧互補型金屬氧化物半導體裝置之晶圓
128‧‧‧互補型金屬氧化物半導體
132、133‧‧‧基板通孔電極
134‧‧‧金屬引線
136‧‧‧導電凸塊
138‧‧‧鈍化保護材料
140‧‧‧凹口
144‧‧‧上表面
第1圖係繪示出根據本發明一實施例之半導體裝置的製造方法的流程圖。
第2A至2D圖係繪示出根據本發明一實施例之第1圖的方法中各個步驟期間的半導體裝置的剖面示意圖。
第3A至3D圖係繪示出根據本發明另一實施例之第1圖的方法中的各個步驟期間的另一半導體裝置的剖面示意圖。
以下揭示內容提供了許多不同的實施例或範例,以實現本發明不同的特徵。以下描述特定的部件及設置方式,以簡化本發明。理所當然地,此僅作為範例,而並非用以限定本發明。例如,第一特徵部件描述為位於第二特徵部件“上”或“上方”(或類似的描述方式),可包括第一及第二特徵部件直接接觸的實施例,也可包括額外的特徵部件介於第一及第二特徵部件之間的實施例。另外,為了簡化及清楚表示,本發明的各種實施例中可能使用重複的標號及/或標示文字,但並不表示各種實施例及/或構造之間的關係。再者,為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關
係,可使用空間相關用語,例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外,空間相關用語涵蓋使用或操作中的裝置的不同方位。例如,若翻轉圖式中的裝置,描述為位於其他元件或特徵部件“下方”或“在...之下”的元件,將定位為位於其他元件或特徵部件“上方”。因此,範例的用語“下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如,旋轉90度或者位於其他方位),並對應地解讀所使用的空間相關用語的描述。
第1圖係繪示出根據本發明一實施例之半導體裝置的晶圓級製造方法10的步驟的流程圖。方法10可製造堆疊半導體裝置(例如,互補型金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)裝置)。在步驟12中,提供一第一基板,其包括一個或多個第一電子裝置形成於第一基板上。在本實施例中,第一基板為塊體(bulk)矽基板。本發明所屬技術領域中具有通常知識者可以理解,基板可由矽或陶瓷所構成,且電子裝置可為被動裝置(例如,電容、電感或電阻等)或主動裝置。可使用各種微製造技術(例如,微影製程、蝕刻製程或膜層沉積製程),在基板上製造電子裝置。再者,在另一實施例中,裝置基板內不具有主動裝置。然而,在另一實施例中,裝置基板內可具有主動裝置(例如,二極體或電晶體)。
在步驟14中,在第一基板上形成一個或多個接合墊。在步驟16中,提供一第二基板,其具有一第二電子裝置(例如,互補型金屬氧化物半導體裝置)。在本實施例中,第二基板也為塊體矽基板,然而也可使用如上述第一基板的其他基
板。在步驟18中,在第二基板上形成一個或多個接合墊。在步驟20中,第一基板及第二基板互相對準並接合,因此可減少組裝的步驟。在本實施例中,可精確地對準裝置基板(即,第一基板)及互補型金屬氧化物半導體裝置之晶圓(即,第二基板),誤差小於10μm,因此可控制晶片內連接所產生的電性寄生效應。再者,在本實施例中,晶圓接合的方法為導電晶圓接合法(例如,融熔接合(fusion bond)、共晶接合(eutectic bond)及/或混成接合(hybrid bond)),用以將基板接合至互補型金屬氧化物半導體裝置。在另一實施例中,接合方法包括非導電晶圓接合法。在進一步的實施例中,第2D圖中的接合方法可使用導電晶圓接合法,而第3D圖中的接合方法可使用非導電晶圓接合法或導電晶圓接合法。然而,本發明所屬技術領域中具有通常知識者可以理解,也可使用其他接合方法。
之後,在步驟22中,形成一個或多個基板通孔電極(through-substrate-via,TSV),以連接第一電子裝置及第二電子裝置。因此,接合導電晶圓及/或基板通孔電極用以內連接第一裝置基板及第二裝置基板。在使用導電晶圓的界面作為內連接結構的實施例中,可使用鍺對鋁,鋁對鋁,銅對銅或其他接合材料。再者,基板通孔電極可用以提供晶片的內部及外部連接。
第2A至2D圖係繪示出第1圖中根據本發明實施例之半導體裝置的晶圓級製造方法10的各個階段中的裝置100的局部或全部的剖面示意圖。裝置100可包括整合了一基板的積體電路裝置,特別是互補型金屬氧化物半導體裝置,該基板具
有設置於其中的一個或多個被動裝置。在本實施例中所使用的被動裝置為溝槽電容。然而,本發明所屬技術領域中具有通常知識者可以理解,任何類型或組合的其他被動裝置(例如,電感或電阻)也可設置於基板中。在本實施例中,互補型金屬氧化物半導體裝置及被動裝置透過導電晶圓接合界面而內連接。為了清楚表示進而更加理解本發明的概念,因此簡化了第2A至2D圖的圖式。可在裝置100中增加額外的特徵部件,且在裝置100的其他實施例中,可替換或省略以下所述的某些特徵部件。
請參照第2A圖,裝置100包括一裝置基板110。在本實施例中,裝置基板110包括一基板111,基板111具有複數個溝槽電容112,透過任何合適的製程而設計及形成於基板111內。基板111為半導體基板(例如,矽或陶瓷基板)。半導體基板可另外或額外地包括一半導體元素(包括鍺)、一半導體化合物(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦(indium antimonide))、一半導體合金(包括矽鍺、磷化鎵砷(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)及/或磷砷化鎵銦(GaInAsP))或其組合。再者,基板110也可為絕緣體上覆半導體層(semiconductor on insulator,SOI)。
在所示實施例中,基板111可進一步包括各種膜層,其未分開繪示且結合而形成各種微電子元件,微電子元件可包括電晶體(例如,金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistors,
MOSFETs)),且電晶體包括互補型金屬氧化物半導體電晶體、雙極性接面電晶體(bipolar junction transistors,BJTs)、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體(p-channel and/or n-channel field-effect transistors,PFETs/NFETs)、電阻、二極體、電容、電感、保險絲、其他合適的元件或其組合。各種膜層可包括高介電常數的介電層、閘極層、硬式罩幕層、界面層、蓋層、擴散/阻障層、介電層、導電層、其它合適的膜層或其組合。基板111的各種膜層也可包括各種摻雜區域、隔離特徵部件、其他特徵部件或其組合。再者,上述微電子元件可互相內連接,以形成基板111的一部分(例如,邏輯裝置、記憶體裝置(例如,靜態隨機存取記憶體(static random access memory,SRAM)、射頻(radio frequency,RF)裝置、輸入/輸出(input/output,I/O)裝置、系統晶片(system-on-chip,SoC)裝置、其他合適的類型的裝置或其組合。
裝置基板110包括設置於基板111上的一絕緣層114。在本實施例中,絕緣層114由氧化矽材料所構成。然而,本發明所屬技術領域中具有通常知識者可以理解,可使用各種其他的絕緣材料。複數個導電部件116設置於絕緣層114內。導電部件116包括水平及垂直方向的內連接結構,例如接觸窗(contact)及/或介層窗(via)及例如導電線。導電部件116內所使用的金屬可包括鋁、鋁矽銅合金、銅、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物或其組合。用來形成導電部件116的製程可包括物理氣相沉積(physical vapor deposition,PVD)製程、化學氣相沉積(chemical vapor deposition,CVD)製程或
其組合。
用來形成各種導電部件116的其他製造技術可包括微影製程及蝕刻製程,以圖案化導電材料,而形成垂直及水平方向的內連接結構。其他的製程可包括熱退火,以形成金屬矽化物。導電部件116內所使用的金屬矽化物可包括矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合。另外,導電部件116可為多層銅內連接結構,其包括銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物或其組合。用來形成銅內連接結構的製程可包括物理氣相沉積製程、化學氣相沉積製程或其組合。可以理解導電部件116的數量、材料、大小及/或所繪示的尺寸並不受限制,因此,導電部件116可包括任何數量、材料、大小及/或尺寸,且取決於裝置100的設計需求。
請參照第2B圖,以下將說明導電晶圓接合界面的製造。一互補型金屬氧化物半導體之金屬層120形成於絕緣層114上。互補型金屬氧化物半導體之金屬層120為另一內連接結構,因此,可透過與上述導電部件116相同的製程及材料而形成。導電接合材料122設置於互補型金屬氧化物半導體之金屬層120的上方。所屬技術領域中具有通常知識者可以理解,可使用鍺對鋁、鋁對鋁、銅對銅或其他接合材料作為接合的材料。此外,互補型金屬氧化物半導體之金屬層120及導電接合材料122共同形成一個接合墊。
請參照第2C圖,在製造過程的此階段中,透過導電晶圓接合法,將互補型金屬氧化物半導體裝置之晶圓124接
合至裝置基板110。在本實施例中,晶圓接合的方法可使用融熔接合法、共晶接合法及/或混成接合法。然而,本發明所屬技術領域中具有通常知識者可以理解,也可使用各種的其他接合方法。如第2C圖所示,互補型金屬氧化物半導體裝置之晶圓124包括一互補型金屬氧化物半導體128,透過合適的互補型金屬氧化物半導體製程而形成於基板130上。為了達成接合,在互補型金屬氧化物半導體裝置之晶圓124上形成另一互補型金屬氧化物半導體之金屬層120(即,接合墊),而將互補型金屬氧化物半導體裝置之晶圓124及基板110接合在一起。本發明所屬技術領域中具有通常知識者可以理解,也可在互補型金屬氧化物半導體裝置之晶圓124的互補型金屬氧化物半導體之金屬層120上塗佈導電接合材料(因而形成一接合墊)。
互補型金屬氧化物半導體裝置之晶圓124更包括一絕緣層126,具有設置於其中的導電部件116。在本實施例中,絕緣層126為氧化層(例如,氧化矽)。絕緣層可另外或額外地包括氮化矽、氮氧化矽、其他合適的材料或其組合。如前所述,導電部件116包括導電材料(例如,金屬)。例如,導電材料也可包括鎢、鈦、鋁、銅、其合金、其他合適的金屬或其合金、或其組合。
基板130為半導體基板(例如,矽基板)。半導體基板可另外或額外地包括一半導體元素(包括鍺)、一半導體化合物(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、一半導體合金(包括矽鍺、磷化鎵砷、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷砷化鎵銦)或其組合。再者,
基板130也可為絕緣體上覆半導體層(SOI),且也可包括各種膜層,其未分開繪示且結合而形成各種微電子元件,微電子元件可包括電晶體(例如,金屬氧化物半導體場效電晶體(MOSFETs)),且電晶體包括互補型金屬氧化物半導體電晶體、雙極性接面電晶體(BJTs)、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體(PFETs/NFETs)、電阻、二極體、電容、電感、保險絲、其他合適的元件或其組合。各種膜層可包括高介電常數的介電層、閘極層、硬式罩幕層、界面層、蓋層、擴散/阻障層、介電層、導電層、其它合適的膜層或其組合。基板130的各種膜層也可包括各種摻雜區域、隔離特徵部件、其他特徵部件或其組合。再者,上述微電子元件可互相內連接,以形成基板130的一部分(例如,邏輯裝置、記憶體裝置(例如,靜態隨機存取記憶體(SRAM)、射頻(RF)裝置、輸入/輸出(I/O)裝置、系統晶片(SoC)裝置、其他合適的類型的裝置或其組合。
請參照第2D圖,以下將說明製造完成的裝置100。如圖所示,透過導電晶圓接合界面(即,接合墊120及122),將互補型金屬氧化物半導體裝置之晶圓124接合至裝置基板110之後,在基板111內形成基板通孔電極132,從基板111的底部延伸至導電部件116的底部。如此一來,基板通孔電極132提供了裝置100的內部及外部電性連接。基板通孔電極132包括一絕緣層115,沿著基板通孔電極132的側壁及基板111的下方形成,且可由相同於上述絕緣層114的材料所構成。基板通孔電極132也包括位於絕緣層115上的一金屬引線134。金屬引線134
接合至焊球或導電凸塊136,並延伸至基板111的下方,以連接導電部件116,進而提供外部的電性連接。在至少一實施例中,金屬引線134完全填入基板通孔電極132的孔洞,且位於絕緣層115的一頂部表面的一部分上。在某些實施例中,金屬引線134沿著基板通孔電極132的側壁而形成,並非完全填入基板通孔電極132的孔洞中而位於絕緣層115的頂部表面的一部分上。之後,鈍化保護材料138設置於基板111的下方且位於基板通孔電極132的上方,以避免發生腐蝕。在本實施例中,鈍化保護材料138為氧化物、氮化物或高分子(例如,環氧樹脂、聚亞醯胺或聚對二甲苯等)。雖然此處僅繪示出一個基板通孔電極132,然而本發明所屬技術領域中具有通常知識者可以理解,也可使用多個基板通孔電極。因此,裝置100整合了多個被動裝置,進而提供了一種在低組裝成本下最小化及穩定不必要的電性寄生效應的裝置。
第3A至3D圖係繪示出根據第1圖中的半導體裝置的製造方法10的各個階段中的另一實施例之裝置200的局部或全部的剖面示意圖。第3A-3D圖的實施例很多方面類似於第2A-2D圖的實施例。然而,最顯著的區別是,第3A-3D圖的實施例利用基板通孔電極來整合,而並非利用第2A-2D圖的實施例所述之導電晶圓接合界面。儘管如此,第3A-3D圖的實施例類似於第2A-2D圖的實施例,例如,裝置200也同樣包括第一裝置晶圓及第二裝置晶圓。因此,為了清楚表示及簡化圖式,第3A-3D圖中類似的特徵部件係使用相同的標號。為了清楚表示進而更加理解本發明的概念,因此簡化了第3A至3D圖的圖
式。可在裝置200中增加額外的特徵部件,且在裝置200的其他實施例中,可替換或省略以下所述的某些特徵部件。
裝置200包括整合了一基板的積體電路裝置(例如,互補型金屬氧化物半導體裝置),該基板具有設置於其中的一個或多個被動電子裝置。在本實施例中所使用的被動裝置為溝槽電容。然而,本發明所屬技術領域中具有通常知識者可以理解,任何類型或組合的主動或其他被動裝置(例如,電感或電阻)也可設置於基板中。在本實施例中,透過一個或多個基板通孔電極,整合互補型金屬氧化物半導體裝置及被動裝置。
請參照第3A圖,裝置200包括一裝置基板110。在本實施例中,裝置基板110包括一基板111,基板111具有複數個溝槽電容112,透過任何合適的製程而設計及形成於基板111內。基板111為半導體基板(例如,矽或陶瓷基板)。半導體基板可另外或額外地包括一半導體元素(包括鍺)、一半導體化合物(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、一半導體合金(包括矽鍺、磷化鎵砷、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷砷化鎵銦)或其組合。再者,基板110也可為絕緣體上覆半導體層(SOI)。
在所示實施例中,基板111也可包括各種膜層,其未分開繪示且結合而形成各種微電子元件,微電子元件可包括電晶體(例如,金屬氧化物半導體場效電晶體(MOSFETs)),且電晶體包括互補型金屬氧化物半導體電晶體、雙極性接面電晶體(BJTs)、高壓電晶體、高頻電晶體、p型通道及/或n型通道場
效電晶體(PFETs/NFETs)、電阻、二極體、電容、電感、保險絲、其他合適的元件或其組合。各種膜層可包括高介電常數的介電層、閘極層、硬式罩幕層、界面層、蓋層、擴散/阻障層、介電層、導電層、其它合適的膜層或其組合。基板111的各種膜層也可包括各種摻雜區域、隔離特徵部件、其他特徵部件或其組合。再者,上述微電子元件可互相內連接,以形成基板111的一部分(例如,邏輯裝置、記憶體裝置(例如,靜態隨機存取記憶體(static random access memory,SRAM)、射頻(radio frequency,RF)裝置、輸入/輸出(input/output,I/O)裝置、系統晶片(system-on-chip,SoC)裝置、其他合適的類型的裝置或其組合。
裝置基板110包括設置於基板111上的一絕緣層114。在本實施例中,絕緣層114由氧化矽材料所構成。然而,本發明所屬技術領域中具有通常知識者可以理解,可使用各種其他的絕緣材料。複數個導電部件116設置於絕緣層114內。導電部件116包括水平及垂直方向的內連接結構,例如接觸窗及/或介層窗及例如導電線。導電部件116內所使用的金屬可包括鋁、鋁矽銅合金、銅、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物或其組合。用來形成導電部件116的製程可包括物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程或其組合。
用來形成各種導電部件116的其他製造技術可包括微影製程及蝕刻製程,以圖案化導電材料,而形成垂直及水平方向的內連接結構。其他的製程可包括熱退火,以形成金屬矽化物。導電部件116內所使用的金屬矽化物可包括矽化鎳、
矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合。另外,導電部件116可為多層銅內連接結構,其包括銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物或其組合。用來形成銅內連接結構的製程可包括物理氣相沉積製程、化學氣相沉積製程或其組合。可以理解導電部件116的數量、材料、大小及/或所繪示的尺寸並不受限制,因此,導電部件116可包括任何數量、材料、大小及/或尺寸,且取決於裝置200的設計需求。
請參照第3B圖,在絕緣層114的上表面上形成一凹口(recess)140或是開口。在本實施例中,凹口140的一下表面142向下延伸至最上層的導電部件116的一下表面116a。可透過合適的製程(例如,微影及蝕刻製程),形成凹口140。
請參照第3C圖,在製造過程的此階段中,透過基板通孔電極,整合互補型金屬氧化物半導體裝置之晶圓124及裝置基板110。如圖所示,互補型金屬氧化物半導體裝置之晶圓124包括一互補型金屬氧化物半導體128,透過合適的互補型金屬氧化物半導體製程而形成於基板130上。為了整合互補型金屬氧化物半導體裝置之晶圓124及裝置基板110,在絕緣層126的下表面上形成另一凹口140或是開口,以匹配形成於裝置基板110上的圖案化氧化物。因此,互補型金屬氧化物半導體裝置之晶圓124也包括具有導電部件116設置於其中的絕緣層126。再者,需注意的是,互補型金屬氧化物半導體裝置之晶圓124的凹口140的上表面144暴露出導電部件116中最下層的表面116b,進而暴露出導電部件116,以形成一接合墊。
在本實施例中,絕緣層126為氧化層(例如,氧化矽層)。絕緣層可另外或額外地包括氮化矽、氮氧化矽、其他合適的材料或其組合。如前所述,導電部件116包括導電材料(例如,金屬)。例如,導電材料也可包括鎢、鈦、鋁、銅、其合金、其他合適的金屬或其合金、或其組合。
基板130的材料及製造方法的細節,可參照在裝置100內的基板130的相關內容,此處不再贅述。在本實施例中,可使用融熔接合法、共晶接合法及/或混成接合法,將互補型金屬氧化物半導體裝置之晶圓124接合至裝置基板110。然而,本發明所屬技術領域中具有通常知識者可以理解,也可使用各種的其他接合方法。
請參照第3D圖,以下將說明製造完成的裝置200。如圖所示,在將裝置基板110的凹口140對準於互補型金屬氧化物半導體裝置之晶圓124之後,互補型金屬氧化物半導體裝置之晶圓124接合至裝置基板110,且在基板111內形成一個或多個基板通孔電極133,以提供裝置200的內部及外部電性連接。在本實施例中,基板通孔電極133從基板111的底部向上延伸而穿透絕緣層114至互補型金屬氧化物半導體裝置之晶圓124的接合墊116b(例如,導電部件116的最下層的表面116b上),而另一基板通孔電極133從基板111的底部向上延伸至裝置基板110的一個或多個接合墊116a(例如,最上層的導電部件116的下表面116a)。
基板通孔電極133包括一絕緣層115,沿著基板通孔電極133的側壁及基板111的下方形成,且可由相同於上述絕
緣層114的材料所構成。基板通孔電極133也包括位於絕緣層115上的一金屬引線134。金屬引線134延伸至基板111的下方,以連接互補型金屬氧化物半導體裝置之晶圓124內的導電部件116,且金屬引線134接合至焊球或導電凸塊136,以提供外部的電性連接。例如,可透過晶種層的沉積製程或銅電鍍製程,形成金屬引線134。在至少一實施例中,金屬引線134完全填入基板通孔電極133的孔洞,且位於絕緣層115的一頂部表面的一部分上。在某些實施例中,金屬引線134沿著基板通孔電極133的側壁而形成,並非完全填入基板通孔電極132的孔洞中而位於絕緣層115的頂部表面的一部分上。之後,鈍化保護材料138沿著基板通孔電極133設置於基板111的下方,以避免發生腐蝕。在本實施例中,鈍化保護材料138為氧化物、氮化物或高分子(例如,環氧樹脂、聚亞醯胺或聚對二甲苯等)。雖然此處繪示出多個基板通孔電極,然而本發明所屬技術領域中具有通常知識者可以理解,也可使用單一個基板通孔電極。因此,裝置200整合了多個被動裝置,進而提供了一種在低組裝成本下最小化及穩定不必要的電性寄生效應的裝置。
本發明實施例可結合各種接合技術。例如,在本發明一實施例的方法中,可利用晶粒對晶圓的接合技術,將所製造出的複數半導體晶粒接合至具有複數電路形成於其中的單一晶圓。另一實施例的方法,可利用晶圓對晶圓的接合技術,將具有複數電路形成於其上的一第一基板及一第二基板互相接合。另外,在接合之後,堆疊的裝置可進行所需的晶圓級封裝製程及切割製程。因此,本發明所屬技術領域中具有通常
知識者可以理解,本發明可結合各種接合技術。
本發明提供了一種裝置,將一個或多個電子裝置與互補型金屬氧化物半導體裝置整合,以最小化及穩定電性寄生效應,且相較於傳統的整合技術,在較低成本下提供了更緊密的系統整合。如本發明實施例所述,電子裝置形成於一裝置基板上,裝置基板對準並接合於另一裝置基板,因而減少了組裝的步驟。由於可精確地對準第一基板及第二基板(例如,誤差小於10μm),因此可良好地控制因內連接所產生的電性寄生效應。由於不需要額外的焊線接合路徑,因此本發明也進一步提供了更緊密的系統整合。
再者,在本發明所述的實施例中,裝置基板包括位於同一晶圓上的一個或多個被動裝置,然而,並不應解釋為本發明的裝置基板限定於上述實施例。例如,也可使用主動裝置。再者,可以設想到本發明的裝置基板可包括彼此堆疊於上方的多個晶圓上的多個裝置基板。再者,裝置基板之間的內連接結構可為晶圓接合界面及/或一個或多個基板通孔電極。
再者,本發明也提供了積體裝置的許多其它實施例。不同的實施例可具有不同的優點,且並非任何的實施例皆具有特定的上述優點。例如,本發明並不限定於基板通孔電極,也可包括其他穿透晶粒的垂直電性連接結構。再者,本發明所述的裝置內可整合一個以上的互補型金屬氧化物半導體裝置。
在一實施例中,一種堆疊半導體裝置的製造方法包括提供一第一基板,具有一第一電子裝置形成於其上。在第
一基板上形成一第一接合墊。提供一第二基板,具有一第二電子裝置形成於其上。在第二基板上形成一第二接合墊。將第一基板及第二基板接合在一起,並形成穿透第一基板的一基板通孔電極,以內連接第一電子裝置及第二電子裝置,因而電性耦接堆疊半導體裝置。
在另一實施例中,提供第一基板的步驟更包括在第一基板上提供複數分離電路,且在第一基板上的每一分離電路上提供一第一接合墊。其中提供第二基板的步驟更包括提供複數半導體晶粒作為第二基板,每一半導體晶粒具有一電子裝置形成於其上,且在每一半導體晶粒上提供一第二接合墊。其中將第一基板及第二基板接合在一起的步驟更包括透過第一接合墊及第二接合墊,將每一半導體晶粒接合至第一基板的一對應的分離電路。
在又另一實施例中,提供第一基板的步驟更包括在第一基板上提供複數分離電路,且在第一基板上的每一分離電路上提供一第一接合墊。其中提供第二基板的步驟更包括在第二基板上提供複數分離電路,且在第二基板上的每一分離電路上提供一第二接合墊。其中將第一基板及第二基板接合在一起的步驟更包括透過第一接合墊及第二接合墊,將第一基板的每一分離電路接合至第二基板的一對應的分離電路。
在另一實施例中,提供第一基板的步驟更包括在第一基板上提供複數分離電路,在第一基板上的每一分離電路上提供一第一接合墊,在第一接合墊上提供一第一絕緣層,且在第一絕緣層上提供一第一開口。其中提供第二基板的步驟更
包括提供複數半導體晶粒作為第二基板,每一半導體晶粒具有一電子裝置形成於其上,在每一半導體晶粒上提供一第二接合墊,在第二接合墊上提供一第二絕緣層,且在第二絕緣層上提供一第二開口。其中將第一基板及第二基板接合在一起的步驟更包括將基板通孔電極延伸穿透第一基板,以電性耦接至第二接合墊。
在又另一實施例中,提供第一基板的步驟更包括在第一基板上提供複數分離電路,在第一基板上的每一分離電路上提供一第一接合墊,在第一接合墊上提供一第一絕緣層,且在第一絕緣層上提供一第一開口。其中提供第二基板的步驟更包括在第二基板上提供複數分離電路,且在第二基板上的每一分離電路上提供一第二接合墊,在第二接合墊上提供一第二絕緣層,且在第二絕緣層上提供一第二開口。其中將第一基板及第二基板接合在一起的步驟更包括將基板通孔電極延伸穿透第一基板,以電性耦接至第二接合墊。
在另一實施例中,提供了一種將堆疊半導體裝置整合於電子系統內的方法。所述裝置包括一第一基板,具有一第一電子裝置形成於其上,一第一接合墊位於第一基板上。一第二基板,具有一第二電子裝置形成於其上,一第二接合墊位於第二基板上。其中第一基板及第二基板接合在一起,且一基板通孔電極穿透第一基板,以內連接第一基板及第二基板,因而電性耦接堆疊半導體裝置。
本發明的又另一實施例提供了一種堆疊半導體裝置,包括一第一基板,具有一第一電子裝置形成於其上,一第
一接合墊位於第一基板上。一第二基板,具有一第二電子裝置形成於其上,一第二接合墊位於第二基板上。其中第一基板及第二基板接合在一起,且一基板通孔電極穿透第一基板,以內連接第一基板及第二基板,因而電性耦接堆疊半導體裝置。
在另一實施例中,一堆疊半導體裝置包括一第一基板,具有一個或多個被動電子裝置形成於其上,而不具有主動裝置形成於其上。例如,被動電子裝置包括電容、線圈、電阻及電感。堆疊半導體裝置也包括一第二基板,具有一互補型金屬氧化物半導體(CMOS)裝置。一內連接結構形成於被動電子裝置與互補型金屬氧化物半導體裝置之間。
在又另一實施例中,一種方法包括提供一第一基板,具有一被動電子裝置形成於其上,且提供一第二基板,具有一互補型金屬氧化物半導體(CMOS)裝置。該方法更包括提供一內連接結構,以連接被動電子裝置及互補型金屬氧化物半導體裝置。
在另一實施例中,一種方法包括將堆疊半導體裝置整合於電子系統內。所述裝置包括一第一基板、一第二基板及其間的一內連接結構。第一基板包括一主動電子裝置形成於其上,且第二基板包括一互補型金屬氧化物半導體(CMOS)裝置。在某些實施例中,內連接結構為導電晶圓接合界面或矽通孔電極(through-silicon-via,TSV)。
在另一實施例中,堆疊半導體裝置包括一第一基板,具有一個或多個被動電子裝置形成於其上,而不具有主動裝置形成於其上。在又另一實施例中,一種方法包括提供一第
一基板,具有一被動電子裝置形成於其上,其中無主動裝置形成於其上,且提供一第二基板,具有一互補型金屬氧化物半導體(CMOS)裝置,以及提供一內連接結構,以連接被動電子裝置及互補型金屬氧化物半導體裝置。
本發明的另一實施例提供一種堆疊半導體裝置的製造方法。該方法包括提供一第一基板,具有一第一電子裝置及位於第一電子裝置上的一第一接合墊,第一電子裝置電性連接至第一接合墊。提供一第二基板,具有一第二電子裝置及位於第二電子裝置上的一第二接合墊,第二電子裝置電性連接至第二接合墊。將第一基板及第二基板接合在一起,其中第一接合墊及第二接合墊電性內連接。在接合之後,形成一基板通孔電極(through-substrate-via,TSV),從相對於第一接合墊的第一基板的一表面,穿透第一基板至第一接合墊。
本發明的又另一實施例提供一種堆疊半導體裝置的製造方法。該方法包括提供一第一基板,具有一第一電子裝置及位於第一電子裝置上的一第一接合墊。在第一基板上的第一接合墊上沉積一第一絕緣層。在第一絕緣層內形成一第一凹口,第一凹口具有一底部表面,低於第一接合墊的一底部表面。提供一第二基板,具有一第二電子裝置及位於第二電子裝置上的一第二接合墊。在第二基板上的第二接合墊上沉積一第二絕緣層。在第二絕緣層內形成一第二凹口,以暴露出第二接合墊的一部份。將第一凹口對準於第二凹口,且將第一絕緣層接合至第二絕緣層。在接合之後,形成一基板通孔電極,其從相對於第一接合墊的第一基板的一表面,穿透第一基板至第一
凹口。
本發明的一實施例提供了一種堆疊半導體裝置。堆疊半導體裝置包括一第一基板。一第一接合墊位於第一基板上。一第二基板包括一第二電子裝置形成於其上。一第二接合墊位於第二基板上的第二電子裝置上,第二接合墊電性連接第二電子裝置。一第二絕緣層位於具有一上表面的第二接合墊上,且第二絕緣層接合至第一基板的第一接合墊。一基板通孔電極,從相對於第一接合墊的一表面,穿透第一基板且穿透第二絕緣層的上表面至第二接合墊。
以上概述了各種實施例的特徵,使得本發明所屬技術領域中具有通常知識者可更佳地理解本發明的型態。本發明所屬技術領域中具有通常知識者應理解,可容易地使用本發明的實施例作為基礎,來設計或修改其他製程及結構,以實現本發明實施例所述的相同目的及/或達到相同的優點。本發明所屬技術領域中具有通常知識者也應理解,等效的構造並不脫離本發明之精神和範圍,且可作各種更動、替代與潤飾,而不脫離本發明之精神和範圍。因此,應可理解本發明並非侷限於所揭示的特定形式。相反地,本發明係用以涵蓋如申請專利範圍所定義的本發明之精神和範圍內的所有修改、等效及替代。
100‧‧‧裝置
110‧‧‧裝置基板
111、130‧‧‧基板
112‧‧‧溝槽電容
114、115、126‧‧‧絕緣層
116‧‧‧導電部件
120‧‧‧互補型金屬氧化物半導體之金屬層/接合墊
122‧‧‧導電接合材料/接合墊
124‧‧‧互補型金屬氧化物半導體裝置之晶圓
128‧‧‧互補型金屬氧化物半導體
132‧‧‧基板通孔電極
134‧‧‧金屬引線
136‧‧‧導電凸塊
138‧‧‧鈍化保護材料
Claims (10)
- 一種堆疊半導體裝置的製造方法,包括:提供一第一基板,具有一第一電子裝置及位於該第一電子裝置上的一第一接合墊,該第一電子裝置電性連接至該第一接合墊;提供一第二基板,具有一第二電子裝置及位於該第二電子裝置上的一第二接合墊,該第二電子裝置電性連接至該第二接合墊;將該第一基板及該第二基板接合在一起,其中該第一接合墊及該第二接合墊電性內連接;以及在接合之後,形成一基板通孔電極,從相對於該第一接合墊的該第一基板的一表面,穿透該第一基板至該第一接合墊,其中形成該基板通孔電極的步驟包括:形成一通孔,從相對於該第一接合墊的該第一基板的該表面,穿透該第一基板至該第一接合墊;以及在將該第一基板及該第二基板接合在一起之後,在該通孔內形成一金屬引線。
- 如申請專利範圍第1項所述之堆疊半導體裝置的製造方法,更包括:沿著該基板通孔電極形成一絕緣層;以及將該堆疊半導體裝置切割為複數個子堆疊半導體裝置。
- 如申請專利範圍第1項所述之堆疊半導體裝置的製造方法,其中:提供該第一基板的步驟更包括: 在該第一基板上形成複數分離晶粒;以及在該第一基板上的該等分離晶粒的每一者上形成該第一接合墊;提供該第二基板的步驟更包括:在該第二基板上形成複數半導體晶粒,該等半導體晶粒的每一者具有該第二電子裝置形成於其上;在該等半導體晶粒的每一者上形成該第二接合墊;以及接合該第一基板及該第二基板的步驟更包括透過該第一接合墊及該第二接合墊,將該第二基板上的該等半導體晶粒的每一者接合至該第一基板上一對應的分離晶粒,且其中該堆疊半導體裝置的製造方法更包括切割該第一基板,以分割出複數堆疊晶粒,該等堆疊晶粒包括該第一基板上的至少一晶粒及該第二基板上的至少另一晶粒。
- 如申請專利範圍第1項所述之堆疊半導體裝置的製造方法,更包括:在該第一基板上提供複數分離晶粒,每一分離晶粒具有該第一電子裝置;在該第一基板上的該等分離晶粒的每一者上形成該第一接合墊;在該第二基板上提供一單一晶粒,該單一晶粒具有該第二電子裝置及位於該第二電子裝置上的該第二接合墊;透過該第一接合墊及該第二接合墊,將該第二基板上的該單一晶粒接合至該第一基板上的該等分離晶粒的至少一者;以及 切割該第一基板,以分割出複數堆疊晶粒,該等堆疊晶粒包括該第二基板上的該單一晶粒及該第一基板上的至少一分離晶粒。
- 如申請專利範圍第1項所述之堆疊半導體裝置的製造方法,更包括:在該第一基板上提供複數分離晶粒;在該第一基板上的該等分離晶粒的每一者上形成該第一接合墊;在該第一接合墊上沉積一第一絕緣層;在該第一絕緣層上形成一第一開口;在該第二基板上提供複數半導體晶粒,該等半導體晶粒的每一者具有該第二電子裝置形成於其上;在該等半導體晶粒的每一者上形成該第二接合墊;在該第二接合墊上沉積一第二絕緣層;以及在該第二絕緣層上形成一第二開口,以暴露出該第二接合墊的一部份;其中接合該第一基板及該第二基板的步驟更包括透過該第一絕緣層及該第二絕緣層,接合該第一基板及該第二基板,以及將該第一開口對準於該第二開口,且其中該金屬引線延伸穿過該第一基板並接觸該第二接合墊,且該基板通孔電極接觸該第二接合墊。
- 一種堆疊半導體裝置的製造方法,包括:提供一第一基板,具有一第一電子裝置及位於該第一電子裝置上的一第一接合墊; 在該第一基板上的該第一接合墊上沉積一第一絕緣層;在該第一絕緣層內形成一第一凹口,該第一凹口具有一底部表面低於該第一接合墊的一底部表面;提供一第二基板,具有一第二電子裝置及位於該第二電子裝置上的一第二接合墊;在該第二基板上的該第二接合墊上沉積一第二絕緣層;在該第二絕緣層內形成一第二凹口,以暴露出該第二接合墊的一部份;將該第一凹口對準於該第二凹口,且將該第一絕緣層接合至該第二絕緣層;以及在接合之後,形成一基板通孔電極,其從相對於該第一接合墊的該第一基板的一表面,穿透該第一基板至該第一凹口。
- 如申請專利範圍第6項所述之堆疊半導體裝置的製造方法,更包括:將一金屬引線形成於該基板通孔電極內並接觸該第二接合墊;在該第一基板上的該金屬引線的一部份上形成一導電凸塊;以及沿著該基板通孔電極的側壁形成一絕緣層。
- 如申請專利範圍第6項所述之堆疊半導體裝置的製造方法,更包括切割該堆疊半導體裝置,以提供複數個子堆疊半導體裝置。
- 一種堆疊半導體裝置,包括: 一第一基板;一第一接合墊,位於該第一基板上;一第二基板,包括一第二電子裝置形成於其上;一第二接合墊,位於該第二基板上的該第二電子裝置上,該第二接合墊電性連接該第二電子裝置;一第二絕緣層,位於具有一上表面的該第二接合墊上,且該第二絕緣層接合至該第一基板的該第一接合墊;以及一基板通孔電極,從相對於該第一接合墊的一表面,穿透該第一基板且穿透該第二絕緣層的該上表面至該第二接合墊。
- 如申請專利範圍第9項所述之堆疊半導體裝置,更包括:一金屬引線,位於接觸該第二接合墊的該基板通孔電極內,以電性內連接該第一基板內的一第一電子裝置及該第二基板內的一第二電子裝置;以及一第一絕緣層,位於該第二絕緣層及該第一基板之間的該第一接合墊上。
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