JP6731061B2 - 多層配線板の製造方法 - Google Patents
多層配線板の製造方法 Download PDFInfo
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- JP6731061B2 JP6731061B2 JP2018543545A JP2018543545A JP6731061B2 JP 6731061 B2 JP6731061 B2 JP 6731061B2 JP 2018543545 A JP2018543545 A JP 2018543545A JP 2018543545 A JP2018543545 A JP 2018543545A JP 6731061 B2 JP6731061 B2 JP 6731061B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H05K3/46—Manufacturing multilayer circuits
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Description
前記金属層の表面に第1配線層を形成する工程と、
前記積層シートの前記第1配線層が形成された面に絶縁層及び配線層を交互に形成して、前記第1配線層が埋込み配線層の形で組み込まれた、多層配線層付積層体を得る工程と、
前記多層配線層付積層体の前記積層シートと反対側の表面に、第2剥離層を介して、前記基材よりもビッカース硬度が低い補強シートを積層する工程と、
前記基材を前記金属層から前記第1剥離層で剥離する工程と、
前記補強シートを前記多層配線層付積層体から前記第2剥離層で剥離して多層配線板を得る工程と、
を含む、多層配線板の製造方法が提供される。
本発明による多層配線板の製造方法は、(1)積層シートの用意、(2)第1配線層の形成、(3)多層配線層付積層体の形成、(4)補強シートの積層、(5)基材の剥離、(6)所望により行われる金属層のエッチング除去、(7)所望により行われる第1配線層の表面処理、(8)所望により行われる電子素子の搭載、及び(9)補強シートの剥離の各工程を含む。積層シートは、基材、第1剥離層及び金属層を順に備えており、それ故、剥離可能な基材を含むといえる。また、補強シートは基材よりもビッカース硬度が低いものである。このように、多層配線板の製造において、剥離可能な基材を含む多層配線層付積層体に、基材よりもビッカース硬度が低い補強シートを積層させることにより、多層配線層を局部的に大きく湾曲させることなく補強することができ、それにより多層配線層の接続信頼性と多層配線層表面の平坦性(コプラナリティ)を向上できる。
図1(a)に示されるように、多層配線板を形成するためのベースとなる積層シート10を用意する。積層シート10は、基材12、第1剥離層14及び金属層16を順に備える。積層シート10は、いわゆるキャリア付銅箔の形態であってもよい。
図1(b)に示されるように、金属層16の表面に第1配線層18を形成する。典型的には、第1配線層18の形成は、公知の手法に従い、フォトレジスト層の形成、電気銅めっき層の形成、フォトレジスト層の剥離、及び所望により銅フラッシュエッチングを経て行われる。例えば、以下のとおりである。まず、金属層16の表面にフォトレジスト層を所定のパターンで形成する。フォトレジストは感光性フィルムであるのが好ましく、例えば感光性ドライフィルムである。フォトレジスト層は、露光及び現像により所定の配線パターンを付与すればよい。金属層16の露出表面(すなわちフォトレジスト層でマスキングされていない部分)に電気銅めっき層を形成する。電気銅めっきは公知の手法により行えばよく、特に限定されない。次いで、フォトレジスト層を剥離する。その結果、電気銅めっき層が配線パターン状に残って第1配線層18を形成し、配線パターンを形成しない部分の金属層16が露出する。
図1(c)に示されるように、積層シート10の第1配線層18が形成された面に絶縁層20及び配線層22を交互に形成して、第1配線層18が埋込み配線層の形で組み込まれた、多層配線層付積層体26を得る。配線層22は1層以上であり、第1配線層18の表現に倣って、第n配線層22(nは2以上の整数)と称することもできる。絶縁層20は1層以上であればよい。すなわち、本発明における多層配線板40は少なくとも2層の配線層(すなわち少なくとも第1配線層18及び第2配線層22)を少なくとも1層の絶縁層20とともに有するものである。第1配線層18、第n配線層22及び絶縁層20で構成される逐次積層構造はビルドアップ層ないしビルドアップ配線層と一般的に称される。本発明の製造方法においては、一般的にプリント配線板において採用される公知のビルドアップ配線層の構成を採用すればよく特に限定されない。
図1(d)に示されるように、多層配線層付積層体26の積層シート10と反対側の表面に、第2剥離層28を介して、基材12よりもビッカース硬度が低い補強シート30を積層する。そして、補強シート30は基材12よりもビッカース硬度が低いことで、補強シート30を積層する際に、基材12よりも優先的に補強シート30自体が撓むことで、積層時に発生しうる応力を補強シート30自体で上手く逃がすことができ、その結果、基材12を含む多層配線層付積層体26の湾曲を効果的に防止ないし抑制することができる。したがって、多層配線層付積層体26は補強シート30によって局部的に大きく湾曲されることなく補強されることができる。すなわち、剥離時の湾曲が効果的に防止ないし抑制される。こうして、湾曲により引き起こされることがあるビルドアップ配線層内部の配線層の断線や剥離を回避して、多層配線層の接続信頼性を向上することができる。また、湾曲が効果的に防止ないし抑制されることで、多層配線層表面の平坦性(コプラナリティ)を向上することができる。
図2(e)に示されるように、基材12を金属層16から第1剥離層14で剥離する。すなわち、基材12、密着金属層(存在する場合)、剥離補助層(存在する場合)、及び第1剥離層14が剥離除去される。この剥離除去は、物理的な剥離により行われるのが好ましい。物理的分離法は、手や治工具、機械等で基材12等をビルドアップ配線層から引き剥がすことにより分離する手法である。このとき、第2剥離層28を介して密着した補強シート30が多層配線層付積層体26を補強していることで、多層配線層付積層体26が局部的に大きく湾曲するのを防止することができる。すなわち、補強シート30は、基材12が剥離される間、引き剥がし力に抗すべく多層配線層付積層体26を補強し、湾曲をより一層効果的に防止ないし抑制することができる。こうして、湾曲により引き起こされることがあるビルドアップ配線層内部の配線層の断線や剥離を回避して、多層配線層の接続信頼性を向上することができる。また、湾曲が効果的に防止ないし抑制されることで、多層配線層表面の平坦性(コプラナリティ)を向上することができる。
所望により、図2(f)に示されるように、基材12の剥離後で、かつ、補強シート30の剥離前に、金属層16をエッチングにより除去する。金属層16のエッチングは、フラッシュエッチング等の公知の手法に基づき行えばよい。
上記工程の後、必要に応じて、第1配線層18の表面には、ソルダ―レジスト層、表面金属処理層(例えば、OSP(Organic Solderbility Preservative)処理層、Auめっき層、Ni−Auめっき層等)、電子素子搭載用の金属ピラー、及び/又ははんだバンプ等が形成されていてもよい。
所望により、図2(g)に示されるように、金属層16の除去後(或いはその後の電気検査後)で、かつ、補強シート30の剥離前に、第1配線層18の表面に電子素子32を搭載させる。本発明の製造方法においては、第2剥離層28及び補強シート30を採用することで、電子素子32の搭載に有利となる優れた表面平坦性(コプラナリティ)を、第1配線層18を埋込み電極として含むビルドアップ配線層の表面において実現することができる。その結果、電子素子搭載の接続歩留まりを高くすることができる。
図3(h)及び(i)に示されるように、補強シート30を多層配線層付積層体26から第2剥離層28で剥離して多層配線板40を得る。この分離工程においては、物理的な分離、化学的な分離等が採用されうる。物理的分離法は、手や治工具、機械等で補強シート30等をビルドアップ配線層から引き剥がすことにより分離する多層配線板40を得る手法である。この場合、第2剥離層28は第1剥離層14よりも高い剥離強度を有している点で、第1剥離層14よりも剥離しにくいといえるが、前述のように、第2剥離層28が発泡剤入り樹脂層の場合、剥離前に熱処理又は紫外線処理を行って第2剥離層28中の発泡剤を発泡させることで、第2剥離層28を脆弱化し、物理的な剥離を容易に行うことができる。あるいは、第2剥離層28が酸可溶型又はアルカリ可溶型樹脂層の場合、薬品(例えば酸溶液又はアルカリ溶液)で第2剥離層28を溶解させることで、物理的な剥離を容易に行うことができる。一方、化学的分離法を採用する場合、補強シート30及び第2剥離層28の両方を溶解するエッチング液を用いて多層配線板40を得ることができる。
基材12及び/又は補強シート30の少なくとも一辺がビルドアップ配線層の端部から延出しているのが好ましい。こうすることで、基材ないし補強シートを剥離する際、端部を把持することが可能となり、剥離を容易にすることができるとの利点がある。
Claims (12)
- 基材、第1剥離層及び金属層を順に備えた積層シートを用意する工程と、
前記金属層の表面に第1配線層を形成する工程と、
前記積層シートの前記第1配線層が形成された面に絶縁層及び配線層を交互に形成して、前記第1配線層が埋込み配線層の形で組み込まれた、多層配線層付積層体を得る工程と、
前記多層配線層付積層体の前記積層シートと反対側の表面に、第2剥離層を介して、前記基材よりもビッカース硬度が低い補強シートを積層する工程と、
前記基材を前記金属層から前記第1剥離層で剥離する工程であって、前記基材を前記金属層から剥離する間、前記補強シートが前記多層配線層付積層体を補強する工程と、
前記補強シートを前記多層配線層付積層体から前記第2剥離層で剥離して多層配線板を得る工程と、
を含む、多層配線板の製造方法。 - 前記基材の剥離後で、かつ、前記補強シートの剥離前に、前記金属層をエッチングにより除去する工程をさらに含む、請求項1に記載の方法。
- 前記補強シートのビッカース硬度が、前記基材のビッカース硬度の2〜99%である、請求項1又は2に記載の方法。
- 前記補強シートのビッカース硬度が、前記基材のビッカース硬度の6〜90%である、請求項1又は2に記載の方法。
- 前記補強シートのビッカース硬度が、前記基材のビッカース硬度の10〜85%である、請求項1又は2に記載の方法。
- 前記補強シートのビッカース硬度が50〜700HVであり、かつ、前記基材のビッカース硬度が500〜3000HVである、請求項1〜5のいずれか一項に記載の方法。
- 前記補強シートのビッカース硬度が150〜550HVであり、かつ、前記基材のビッカース硬度が550〜2500HVである、請求項1〜5のいずれか一項に記載の方法。
- 前記補強シートのビッカース硬度が200〜500HVであり、かつ、前記基材のビッカース硬度が600〜2000HVである、請求項1〜5のいずれか一項に記載の方法。
- JIS H 3130:2012に準拠して測定される、前記補強シートのばね限界値Kb0.1が100〜1500N/mm2である、請求項1〜8のいずれか一項に記載の方法。
- JIS H 3130:2012に準拠して測定される、前記補強シートのばね限界値Kb0.1が150〜1200N/mm2である、請求項1〜8のいずれか一項に記載の方法。
- JIS H 3130:2012に準拠して測定される、前記補強シートのばね限界値Kb0.1が200〜1000N/mm2である、請求項1〜8のいずれか一項に記載の方法。
- 前記基材の剥離後で、かつ、前記補強シートの剥離前に、前記金属層をエッチングにより除去する工程と、
前記金属層の除去後で、かつ、前記補強シートの剥離前に、前記第1配線層の表面に電子素子を搭載させる工程と、
をさらに含む、請求項1及び3〜11のいずれか一項に記載の方法。
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JP6299290B2 (ja) | 2014-03-07 | 2018-03-28 | 富士通株式会社 | 回路基板の製造方法 |
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